Silicon carbide multi-channel longitudinal groove type MOSFET and manufacturing method thereof

Abstract

The invention relates to a silicon carbide multi-channel longitudinal groove type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a manufacturing method thereof, and belongs to the technical field of silicon carbide semiconductors. The device comprises a substrate, a drift region arranged on the substrate and a plurality of grooves arranged in the drift region, wherein the plurality of grooves are periodically arranged along the transverse direction; the groove extends along a direction vertical to the surface of the substrate; gate oxide layers and gates located on the gate oxide layers are arranged on the two sides in the trenches respectively, channel regions are formed between the adjacent trenches and at the bottoms of the trenches in the drift region, source regions and body contact regions are formed in the channel regions, intermetallic dielectric layers are formed between the surfaces of the gates and the source regions, top-layer source metal is formed on the source regions, and bottom-layer source metal is formed on the body contact regions. And an ohmic contact layer is formed between the source electrode region and the top layer source electrode metal. According to the device disclosed by the invention, the inverted conduction channels are simultaneously formed in the side walls and the bottoms of the grooves, so that conduction current flows in parallel in the longitudinal and transverse directions, and the number of the effective conduction channels is remarkably increased.

Description

Technical Field

[0001] This invention belongs to the field of silicon carbide semiconductor technology, specifically relating to a silicon carbide multi-channel longitudinal trench MOSFET and its manufacturing method. Background Technology

[0002] MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) have become core switching devices in modern power electronic systems due to their significant advantages such as low conduction loss, fast switching speed, high input impedance, and low drive loss. They are widely used in various power management and power conversion scenarios, including switching power supplies, inverters, charging piles, and new energy vehicle electronic control systems. With high frequency, miniaturization, and high efficiency becoming the core development trends of power devices, further reducing conduction losses and improving current handling capacity per unit area have become key research focuses. Trench MOSFETs, through etching processes to form vertical trench structures within the semiconductor material, allow the conductive channels to be distributed longitudinally along the trench sidewalls. This significantly increases the effective channel width without changing the chip area, thereby effectively reducing the specific on-resistance and becoming the mainstream structural solution for high-voltage power MOSFETs.

[0003] However, existing trench MOSFETs still have significant performance bottlenecks: these devices typically form longitudinal conduction channels only on the two sidewalls of the trench, with the bottom region of the trench hardly participating in conduction. This results in the semiconductor surface area not being fully utilized, and there is still considerable room for improvement in channel density and conduction performance. In addition, an electric field concentration region easily forms at the bottom of the trench, affecting the device's voltage withstand capability and reliability, making it difficult to meet the stringent requirements of higher voltage and higher power density applications. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide a silicon carbide multi-channel longitudinal trench MOSFET and its manufacturing method.

[0005] The main technical problems solved by this invention include: how to further improve the channel utilization efficiency in trench MOSFETs and improve the electric field distribution at the bottom of the trench, so as to reduce the on-resistance while ensuring the withstand voltage capability.

[0006] The technical solution of the present invention is as follows: This invention provides a silicon carbide multi-channel longitudinal trench MOSFET, including a substrate, a drift region disposed on the substrate, and a plurality of trenches disposed in the drift region, wherein the plurality of trenches are arranged periodically in a transverse direction; the trenches extend in a direction perpendicular to the substrate surface; a gate oxide layer and a gate located on the gate oxide layer are respectively disposed on both sides of the trench; the drift region is provided with a channel region between adjacent trenches and at the bottom of the trench; a source region and a body contact region are disposed in the channel region; an intermetallic dielectric layer is disposed on the side of the gate, the intermetallic dielectric layer extends to the source region; a top source metal is disposed on the source region; an ohmic contact layer is disposed between the source region and the top source metal; a bottom drain metal is disposed below the substrate, and the bottom drain metal forms an ohmic contact with the substrate.

[0007] When a gate voltage is applied to the gate, the device of the present invention forms a longitudinal inverse channel in the trench sidewall, which enables the carriers to conduct along the trench depth direction; at the same time, a transverse inverse channel is formed in the trench region at the bottom of the trench, which enables the carriers to conduct in the transverse direction between adjacent trenches.

[0008] According to a preferred embodiment of the present invention, the substrate is a heavily doped N-type 4H-SiC substrate, the doping element is nitrogen, and the doping concentration is greater than 1×10⁻⁶. 19 cm -3 The substrate is a Si-polar (0001) crystal substrate with a 4° off-cut angle along the [11-20] direction. In this invention, the substrate is used to form the drain region of a semiconductor device and to provide a low-resistance current output channel.

[0009] According to a preferred embodiment of the present invention, the drift region is an N-type lightly doped silicon carbide epitaxial layer, the doping element is nitrogen, and the doping concentration is 5 × 10⁻⁶. 14 cm -3 -5×10 16 cm -3 The doping depth of the drift region in this invention is set according to the voltage withstand requirements of the semiconductor device, and is used to withstand the drain voltage in the device's off state.

[0010] According to a preferred embodiment of the present invention, the trench depth is 1.0 μm-1.5 μm and the trench width is 4.0 μm-6.0 μm.

[0011] According to a preferred embodiment of the present invention, the gate oxide layer is a silicon dioxide layer with a thickness of 40-70 nm. In this invention, the gate oxide layer is used to isolate the gate from the semiconductor region and to ensure the stability of the gate control channel.

[0012] According to a preferred embodiment of the present invention, the gate material is doped polysilicon or a metal gate material. The device of the present invention controls the inversion conduction of the channel region by applying a gate voltage to the gate.

[0013] According to a preferred embodiment of the present invention, the doping element in the channel region is aluminum, and the doping concentration is 5 × 10⁻⁶. 16 -5×10 17 cm -3 The doping depth is 0.8μm-1.3μm. In this invention, the channel region is used to form an inversion channel under the action of the gate voltage.

[0014] According to a preferred embodiment of the present invention, the source region is a heavily doped N-type region, the doping element is nitrogen, and the doping concentration is greater than 1×10⁻⁶. 18 cm -3 The doping depth is 0.3μm-1.0μm.

[0015] According to a preferred embodiment of the present invention, the doping element in the body contact region is aluminum, and the doping concentration is greater than 1×10⁻⁶. 18 cm -3 The doping depth is 0.5μm-1.3μm.

[0016] According to a preferred embodiment of the present invention, the material of the intermetallic dielectric layer is silicon dioxide or a low-dielectric-constant dielectric material, including but not limited to fluorine-doped silicon dioxide (FSG), carbon-doped silicon oxide (SiCOH), and porous low-dielectric-constant materials. In this invention, the intermetallic dielectric layer is used to achieve electrical isolation between the gate, source, and top metal.

[0017] According to a preferred embodiment of the present invention, the top source metal is a stacked structure, the stacked structure including a barrier layer and a conductive layer, the barrier layer being one or more of a titanium layer and a titanium nitride layer, and the conductive layer being an aluminum layer or an aluminum-copper alloy layer, in order to reduce contact resistance and improve reliability.

[0018] The present invention also provides a method for manufacturing the above-mentioned silicon carbide multi-channel longitudinal trench MOSFET.

[0019] A method for manufacturing a silicon carbide multi-channel longitudinal trench MOSFET includes the following steps: (1) A substrate is provided, on which a drift region is formed; (2) Multiple trenches are formed in the drift zone; (3) A channel area is formed between adjacent channels in the drift zone and at the bottom of the channel; (4) A source region and a bulk contact region are formed in the channel region; (5) A gate oxide layer and a gate electrode located on the gate oxide layer are formed on the sidewall of the trench; (6) An intermetallic dielectric layer is formed between the gate surface and the source region, and an ohmic contact layer is fabricated; (7) A top layer of source metal is formed on the source region; (8) A bottom drain metal is formed under the substrate.

[0020] According to a preferred embodiment of the present invention, in step (1), a drift region is formed on the substrate by an epitaxial growth process.

[0021] According to a preferred embodiment of the present invention, in step (2), the method for forming the plurality of trenches includes: forming a first oxide layer on the surface of the drift region by a thermal oxidation process; forming a plurality of etch windows arranged periodically in the transverse direction in the first oxide layer by a photolithography process, using the etch windows as trench etching masks to perform anisotropic etching on the drift region to form a plurality of trenches extending in a direction perpendicular to the substrate surface; preferably, the first oxide layer is a silicon dioxide layer.

[0022] According to a preferred embodiment of the present invention, in step (3), the method for forming the channel region includes: depositing a medium material on the sidewall of the trench to form a spacer layer, implanting aluminum ions into the surface of the drift region, and forming a channel region between adjacent trenches and at the bottom of the trench; preferably, the medium material is silicon dioxide or silicon nitride.

[0023] According to a preferred embodiment of the present invention, in step (4), the method for forming the source region and the body contact region includes: depositing a dielectric material to thicken the spacer layer on the trench sidewall again; using the spacer layer as a self-aligned mask, performing nitrogen ion implantation on the surface of the trench region to form the source region; using a photolithography mask to define the implantation area, performing aluminum ion implantation at the midpoint of the surface of the trench region to form the body contact region; finally cleaning to remove the spacer layer, and performing implantation post-annealing on the wafer surface; preferably, the dielectric material is silicon dioxide or silicon nitride; preferably, the dielectric material is silicon dioxide.

[0024] According to a preferred embodiment of the present invention, in step (5), the method for forming the gate oxide layer and the gate located on the gate oxide layer is as follows: a gate oxide layer is formed on the wafer surface after step (4) by a thermal oxidation process, and a gate thin film is formed on the silicon dioxide layer by a deposition process. The gate oxide layer and the gate thin film are etched to form the gate.

[0025] According to a preferred embodiment of the present invention, in step (6), the process of forming the intermetallic dielectric layer and the ohmic contact layer includes: forming an intermetallic dielectric layer between the gate surface and the source region by plasma-enhanced chemical vapor deposition, opening contact holes by photolithography and etching processes, and creating an ohmic contact layer by opening windows in the source region and the bulk contact region.

[0026] According to a preferred embodiment of the present invention, in step (6), a top layer source metal is formed on the source region by a physical vapor deposition process.

[0027] According to a preferred embodiment of the present invention, in step (7), the formation process of the bottom drain metal is as follows: the wafer after step (6) is passivated, and the bottom drain metal is formed under the substrate by metal deposition and annealing processes.

[0028] The technical features and beneficial effects of this invention are as follows: 1. The silicon carbide multi-channel longitudinal trench MOSFET of the present invention forms inverse conduction channels on both the trench sidewall and the trench bottom, so that the conduction current flows in parallel in the longitudinal and lateral directions, thereby significantly increasing the number of effective conduction channels.

[0029] 2. The silicon carbide multi-channel longitudinal trench MOSFET of the present invention improves the electric field distribution at the bottom of the trench by introducing the bottom region of the trench as an effective conduction region, which helps to reduce local electric field concentration and improve the breakdown voltage and long-term reliability of the device.

[0030] 3. The silicon carbide multi-channel longitudinal trench MOSFET of the present invention achieves a better trade-off between voltage withstand performance and conduction performance by setting a lightly doped N-type drift region and cooperating with a multi-channel parallel conduction structure. Attached Figure Description

[0031] Figure 1 This is a cross-sectional schematic diagram of a silicon carbide multi-channel longitudinal trench MOSFET according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure presented in step (1) of the manufacturing method of silicon carbide multi-channel longitudinal trench MOSFET in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure after forming the etching window in step (2) of the manufacturing method of silicon carbide multi-channel longitudinal trench MOSFET in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure after the trench is formed in step (2) of the manufacturing method of silicon carbide multi-channel longitudinal trench MOSFET in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure presented in step (3) of the manufacturing method of silicon carbide multi-channel longitudinal trench MOSFET in an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure after thickening the spacer layer in step (4) of the manufacturing method of silicon carbide multi-channel longitudinal trench MOSFET in an embodiment of the present invention. Figure 7 This is a schematic diagram of the structure after forming the source region and the body contact region in step (4) of the manufacturing method of silicon carbide multi-channel longitudinal trench MOSFET in an embodiment of the present invention. Figure 8This is a schematic diagram of the structure after removing the spacer layer in step (4) of the manufacturing method of silicon carbide multi-channel longitudinal trench MOSFET in an embodiment of the present invention. Figure 9 This is a schematic diagram of the structure after the formation of the gate oxide layer and the gate film in step (5) of the manufacturing method of silicon carbide multi-channel longitudinal trench MOSFET in an embodiment of the present invention. Figure 10 This is a schematic diagram of the structure after the gate is formed in step (5) of the manufacturing method of silicon carbide multi-channel longitudinal trench MOSFET in an embodiment of the present invention. Figure 11 This is a schematic diagram of the structure presented in step (6) of the manufacturing method of silicon carbide multi-channel longitudinal trench MOSFET in an embodiment of the present invention; Figure 12 This is a schematic diagram of the structure presented in step (7) of the manufacturing method of silicon carbide multi-channel longitudinal trench MOSFET in an embodiment of the present invention; Figure 13 This is a schematic diagram of the structure presented in step (8) of the manufacturing method of silicon carbide multi-channel longitudinal trench MOSFET in an embodiment of the present invention; The components are: 1. Substrate; 2. Drift region; 3. Trench; 4. Channel region; 5. Source region; 6. Bulk contact region; 7. Gate oxide layer; 8. Gate film; 9. Gate; 10. Intermetallic dielectric layer; 11. Ohmic contact layer; 12. Top source metal; 13. Bottom drain metal; 14. Spacer layer. Detailed Implementation

[0032] The present invention will be further described below with reference to embodiments and accompanying drawings, but is not limited thereto. The described embodiments are some embodiments of the present invention. Based on these embodiments, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] In the description of this invention, it should be noted that the terms "upper" and "lower" and other terms indicating orientation or positional relationship are only for the convenience of describing this invention and simplifying the description, and should not be construed as limiting this invention.

[0034] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. Unless otherwise specified in the embodiments of the present invention, all techniques existing in the art can be used.

[0035] Example 1 like Figure 1As shown, a silicon carbide multi-channel longitudinal trench MOSFET includes a substrate 1, a drift region 2 disposed on the substrate 1, and a plurality of trenches 3 disposed in the drift region 2. The plurality of trenches 3 are arranged periodically in a transverse direction. The trenches 3 extend in a direction perpendicular to the surface of the substrate 1. A gate oxide layer 7 and a gate 9 located on the gate oxide layer 7 are respectively disposed on both sides of the trenches 3. A channel region 4 is disposed between adjacent trenches 3 and at the bottom of the trenches 3. A source region 5 and a body contact region 6 are disposed in the channel region 4. An intermetallic dielectric layer 10 is disposed on the side of the gate 9 and extends to the source region 5. A top source metal 12 is disposed on the source region 5. An ohmic contact layer 11 is disposed between the source region 5 and the top source metal 12. A bottom drain metal 13 is disposed below the substrate 1 and forms an ohmic contact with the substrate 1. When a gate voltage is applied to the gate 9, the channel region 4 forms a longitudinal inversion channel on the sidewall of the trench 3, allowing the carriers to conduct along the depth direction of the trench 3; at the same time, a transverse inversion channel is formed in the channel region 4 at the bottom of the trench 3, allowing the carriers to conduct in the transverse direction between adjacent trenches 3.

[0036] In this embodiment, substrate 1 is a heavily doped N-type 4H-SiC substrate, with nitrogen as the doping element and a doping concentration of 2 × 10⁻⁶. 19 cm -3 Substrate 1 is a Si polar (0001) crystal substrate with a 4° off-cut angle along the [11-20] direction. Substrate 1 is used to form the drain region of the semiconductor device and provide a low-resistance current output channel.

[0037] In this embodiment, drift region 2 is an N-type lightly doped silicon carbide epitaxial layer, with nitrogen as the dopant element and a doping concentration of 5 × 10⁻⁶. 15 cm -3 The drift region 2 has a doping depth of 9μm, which is set according to the voltage withstand requirements of semiconductor devices to withstand a drain voltage of 1200V in the device's off state.

[0038] In this embodiment, the depth of groove 3 is 1.0 μm and the width of groove 3 is 4.0 μm.

[0039] In this embodiment, the gate oxide layer 7 is a silicon dioxide layer with a thickness of 50 nm. The gate oxide layer 7 is used to isolate the gate 9 from the semiconductor region and to ensure the stability of the gate 9 control channel.

[0040] In this embodiment, the gate 9 is made of doped polysilicon, and the inversion conduction of the channel region 4 is controlled by applying a gate voltage to the gate 9.

[0041] In this embodiment, the doping element in channel region 4 is aluminum, and the doping concentration is 1×10⁻⁶. 17 cm -3 The doping depth is 0.8 μm. Channel region 4 is used to form an inversion channel under the voltage of gate 9.

[0042] In this embodiment, source region 5 is a heavily doped N-type region, with nitrogen as the dopant and a doping concentration of 2 × 10⁻⁶. 19 cm -3 The doping depth is 0.5 μm.

[0043] In this embodiment, the doping element in the body contact region 6 is aluminum, and the doping concentration is 2×10⁶. 18 cm -3 The doping depth is 0.8 μm.

[0044] In this embodiment, the material of the intermetallic dielectric layer 10 is silicon dioxide, which is used to achieve electrical isolation between the gate 9, the source, and the top metal.

[0045] In this embodiment, the top source metal 12 is a stacked structure of titanium nitride layer and aluminum layer to reduce contact resistance and improve reliability.

[0046] The above-mentioned method for manufacturing silicon carbide multi-channel longitudinal trench MOSFETs, such as Figures 2-13 As shown, the steps include: (1) Provide a substrate 1, and form a drift region 2 on the substrate 1 by an epitaxial growth process.

[0047] (2) A first oxide layer is formed on the surface of the drift region 2 by thermal oxidation process. The first oxide layer is a silicon dioxide layer. Multiple etching windows are formed in the first oxide layer by photolithography process, arranged periodically in the lateral direction. The etching windows are used as etching masks for trench 3. Anisotropic etching is performed on the drift region 2 to form multiple trenches 3 extending in the direction perpendicular to the surface of the substrate 1.

[0048] (3) Deposit a medium material, which is silicon dioxide, on the sidewall of the trench 3 to form a spacer layer 14, implant aluminum ions into the surface of the drift region 2, and form a channel region 4 between adjacent trenches 3 and at the bottom of the trench 3.

[0049] (4) A dielectric material is deposited again on the sidewall of trench 3 to thicken the spacer layer 14. The dielectric material is silicon dioxide. Using the spacer layer 14 as a self-aligned mask, nitrogen ions are implanted into the surface of the channel region 4 to form the source region 5. A photolithography mask is used to define the implantation area, and aluminum ions are implanted into the midpoint of the surface of the channel region 4 to form the bulk contact region 6. Finally, the spacer layer 14 is cleaned and removed, and the wafer surface is implanted and annealed.

[0050] (5) A gate oxide layer 7 is formed on the wafer surface after step (4) by thermal oxidation process. The gate oxide layer 7 is a silicon dioxide layer. A gate thin film 8 is formed on the silicon dioxide layer by deposition process. The gate thin film 8 is a polysilicon thin film. The gate oxide layer 7 and the gate thin film 8 are etched to form the gate 9.

[0051] (6) A metal-to-metal dielectric layer 10 is formed between the gate 9 surface and the source region 5 by plasma-enhanced chemical vapor deposition, and contact holes are made by photolithography and etching, and ohmic contact layer 11 is made by opening windows in the source region 5 and the bulk contact region 6.

[0052] (7) A top layer of source metal 12 is formed on the source region 5 by physical vapor deposition.

[0053] (8) Passivate the wafer after step (7) and form the bottom drain metal 13 under the substrate 1 by metal deposition and annealing process.

[0054] Example 2 A silicon carbide multi-channel longitudinal trench MOSFET and its manufacturing method are described in Example 1, except that: The doping concentration of drift region 2 is 4 × 10⁻⁶. 15 cm -3 The doping depth is 11μm, which is used to withstand the 1700V drain voltage in the device off state; The trench 3 has a depth of 1.5 μm and a width of 6.0 μm; The thickness of gate oxide layer 7 is 40 nm; The doping concentration of channel region 4 is 5 × 10⁻⁶. 16 cm -3 The doping depth is 1.3 μm; The doping depth of source region 5 is 1.0 μm; The doping depth of the body contact region 6 is 0.5 μm.

[0055] The other steps and conditions are the same as in Example 1.

[0056] Example 3 A silicon carbide multi-channel longitudinal trench MOSFET and its manufacturing method are described in Example 1, except that: The doping concentration of drift region 2 is 8 × 10⁻⁶. 15 cm -3 The doping depth is 6μm, which is used to withstand the 650V drain voltage in the device off state; The depth of trench 3 is 1.2 μm, and the width of trench 3 is 5.0 μm; The thickness of gate oxide layer 7 is 70 nm; The doping concentration of channel region 4 is 5 × 10⁻⁶. 17 cm -3 The doping depth is 1.0 μm; The doping depth of source region 5 is 0.3 μm; The doping depth of the body contact region 6 is 1.3 μm.

[0057] The other steps and conditions are the same as in Example 1.

[0058] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Those skilled in the art can make various modifications and variations to the present invention without departing from its spirit and principles. Any modifications, equivalent substitutions, or improvements made within the scope of the spirit and principles of the present invention should fall within the protection scope of the present invention.

Claims

1. A silicon carbide multi-channel longitudinal trench MOSFET, characterized in that, The device includes a substrate, a drift region disposed on the substrate, and a plurality of trenches disposed in the drift region, wherein the plurality of trenches are arranged periodically in a transverse direction; the trenches extend in a direction perpendicular to the substrate surface; a gate oxide layer and a gate on the gate oxide layer are respectively disposed on both sides of the trench; a channel region is disposed between adjacent trenches and at the bottom of the trench in the drift region; a source region and a body contact region are disposed in the channel region; an intermetallic dielectric layer is disposed on the side of the gate and extends to the source region; a top source metal is disposed on the source region; an ohmic contact layer is disposed between the source region and the top source metal; and a bottom drain metal is disposed below the substrate, forming an ohmic contact with the substrate.

2. The silicon carbide multi-channel longitudinal trench MOSFET according to claim 1, characterized in that, The drift region is an N-type lightly doped silicon carbide epitaxial layer, with nitrogen as the dopant element and a doping concentration of 5 × 10⁻⁶. 14 cm -3 -5×10 16 cm -3 .

3. The silicon carbide multi-channel longitudinal trench MOSFET according to claim 1, characterized in that, The trench depth is 1.0μm-1.5μm and the trench width is 4.0μm-6.0μm.

4. The silicon carbide multi-channel longitudinal trench MOSFET according to claim 1, characterized in that, The gate oxide layer is a silicon dioxide layer with a thickness of 40-70 nm.

5. The silicon carbide multi-channel longitudinal trench MOSFET according to claim 1, characterized in that, The gate material is doped polycrystalline silicon or a metal gate material.

6. The silicon carbide multi-channel longitudinal trench MOSFET according to claim 1, characterized in that, The channel region is doped with aluminum at a concentration of 5 × 10⁻⁶. 16 -5×10 17 cm -3 The doping depth is 0.8μm-1.3μm.

7. The silicon carbide multi-channel longitudinal trench MOSFET according to claim 1, characterized in that, Includes one or more of the following conditions: a. The substrate is a heavily doped N-type 4H-SiC substrate, with nitrogen as the doping element and a doping concentration greater than 1×10⁻⁶. 19 cm -3 The substrate is a Si polar (0001) crystal plane substrate, and has a 4° off-cut angle along the [11-20] direction; b. The source region is a heavily doped N-type region, with nitrogen as the dopant and a doping concentration greater than 1 × 10⁻⁶. 18 cm -3 The doping depth is 0.3μm-1.0μm; c. The doping element in the body contact region is aluminum, and the doping concentration is greater than 1×10⁻⁶. 18 cm -3 The doping depth is 0.5μm-1.3μm; d. The material of the intermetallic dielectric layer is silicon dioxide or a low dielectric constant dielectric material, wherein the low dielectric constant dielectric material is selected from one or more of fluorine-doped silicon dioxide, carbon-doped silicon oxide, and porous low dielectric constant materials; e. The top-layer source metal has a stacked structure, which includes a barrier layer and a conductive layer. The barrier layer is one or more of a titanium layer and a titanium nitride layer, and the conductive layer is an aluminum layer or an aluminum-copper alloy layer.

8. A method for manufacturing a silicon carbide multi-channel longitudinal trench MOSFET, used in the silicon carbide multi-channel longitudinal trench MOSFET of claim 1, characterized in that, Including the following steps: (1) A substrate is provided, on which a drift region is formed; (2) Multiple trenches are formed in the drift zone; (3) A channel area is formed between adjacent channels in the drift zone and at the bottom of the channel; (4) A source region and a bulk contact region are formed in the channel region; (5) A gate oxide layer and a gate electrode located on the gate oxide layer are formed on the sidewall of the trench; (6) An intermetallic dielectric layer is formed between the gate surface and the source region, and an ohmic contact layer is fabricated; (7) A top layer of source metal is formed on the source region; (8) A bottom drain metal is formed under the substrate.

9. The method for manufacturing a silicon carbide multi-channel longitudinal trench MOSFET according to claim 8, characterized in that, Includes one or more of the following conditions: i. In step (1), a drift region is formed on the substrate by an epitaxial growth process; ii. In step (2), the method for forming the plurality of trenches includes: forming a first oxide layer on the surface of the drift region by a thermal oxidation process; forming a plurality of etch windows arranged periodically in the transverse direction in the first oxide layer by a photolithography process, using the etch windows as trench etching masks to perform anisotropic etching on the drift region to form a plurality of trenches extending in a direction perpendicular to the substrate surface; the first oxide layer is a silicon dioxide layer; iii. In step (3), the method for forming the channel region includes: depositing a dielectric material on the sidewall of the trench to form a spacer layer, implanting aluminum ions into the surface of the drift region, and forming a channel region between adjacent trenches and at the bottom of the trench; the dielectric material is silicon dioxide or silicon nitride. iv. In step (4), the method for forming the source region and the body contact region includes: depositing a dielectric material to thicken the spacer layer on the trench sidewall again; using the spacer layer as a self-aligned mask, performing nitrogen ion implantation on the surface of the trench region to form the source region; using a photolithography mask to define the implantation area, performing aluminum ion implantation at the midpoint of the surface of the trench region to form the body contact region; finally cleaning to remove the spacer layer, and performing implantation annealing on the wafer surface; the dielectric material is silicon dioxide or silicon nitride.

10. The method for manufacturing a silicon carbide multi-channel longitudinal trench MOSFET according to claim 8, characterized in that, Includes one or more of the following conditions: In step (5), the gate oxide layer and the gate located on the gate oxide layer are formed by: forming a gate oxide layer on the wafer surface after step (4) by thermal oxidation process, forming a gate thin film on the silicon dioxide layer by deposition process, and etching the gate oxide layer and the gate thin film to form the gate. In step (6), the formation process of the intermetallic dielectric layer and the ohmic contact layer includes: forming an intermetallic dielectric layer between the gate surface and the source region by plasma-enhanced chemical vapor deposition, opening contact holes by photolithography and etching processes, and creating an ohmic contact layer by opening windows in the source region and the bulk contact region. In step (6), a top layer of source metal is formed on the source region by physical vapor deposition. In step (7), the process of forming the bottom drain metal is as follows: the wafer after step (6) is passivated, and the bottom drain metal is formed under the substrate by metal deposition and annealing.

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