Method for improving noise of three-dimensional anisotropic magnetoresistive sensor product and product

Abstract

The invention provides a method for improving noise of a three-dimensional anisotropic magnetoresistive sensor product and the product. The method comprises the following steps: providing a substrate with a lower metal layer, a dielectric layer and a through hole; designing and forming a top metal layer connected with the lower metal layer through a through hole, wherein a bonding pad area is arranged on the top metal layer; the layout of the through holes is optimized below the bonding pad area, the through hole pitch is set to be larger than 3 micrometers, the data ratio is set to be smaller than 10%, and therefore holes generated when the through holes are filled with the top metal layer are reduced; and forming a passivation protection layer on the top metal layer and opening the bonding pad region. By optimizing the layout of the through holes, the hole defect of the top metal layer is eliminated, the material residue during the development of the passivation layer is avoided, and the contact resistance is reduced, so that the noise performance of the product is remarkably improved, and the yield is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method and product for improving the noise of a three-dimensional anisotropic magnetoresistive sensor. Background Technology

[0002] Micro-Electro-Mechanical Systems (MEMS) are miniature integrated systems that utilize integrated circuit technology and micromachining technology to fabricate microstructures, microprocessors, control circuits, and even interface circuits, communication circuits, and power supply circuits on one or more chips. Among them, magnetoresistive sensors (such as anisotropic magnetoresistive sensors, AMRs) are an important MEMS product, widely used in fields such as geomagnetic detection and current detection.

[0003] To meet the requirements of modern electronic devices for miniaturization, high performance, and high reliability, MEMS products typically employ wafer-level chip-scale packaging (WLCSP) technology, particularly using ball-mounting for packaging. This packaging method offers advantages such as small package size, low parasitic parameters, and high signal quality. The WLCSP process mainly involves polyimide (PI) processing and redistribution layer (RDL) processing.

[0004] In traditional 3D AMR product design and manufacturing processes, to enhance the reliability of interlayer connections and expand the process window, as many vias as possible are typically designed below the pads to connect the top metal and the lower metal (e.g., Metal 1). Figure 1 The schematic diagram of the conventional process structure shown shows an interlayer dielectric (IMD) layer covering the lower metal layer (Metal 1), with dense vias (VIA) formed in the IMD, and the top metal layer deposited and filling these vias.

[0005] However, this traditional design approach has led to new problems in actual manufacturing processes. Specifically, combining... Figure 1 As shown, when a thicker aluminum layer is used as the top layer metal to fill these dense vias, the morphology of the IMD step location often leads to voids within the top layer metal (e.g., Figure 1 (The area shown in the middle circle).

[0006] In subsequent packaging processes, especially during the photolithography and development of the polyimide (PI) layer, insufficient development can leave PI material residue in the voids of the top metal layer, areas that should have been completely removed. This PI residue can significantly increase the contact resistance between the subsequently formed redistribution layer (RDL) and the top metal pads. This abnormally high contact resistance severely interferes with the magnetoelectric signal conversion of MEMS products, leading to noise and ultimately reducing chip yield and reliability.

[0007] Therefore, there is an urgent need for an optimized design and manufacturing method that can effectively eliminate the PI residue problem caused by the top metal voids while ensuring the interlayer bonding performance, thereby improving the noise performance of AMR products. Summary of the Invention

[0008] This application provides a method for improving the noise of a three-dimensional anisotropic magnetoresistive sensor product and a three-dimensional anisotropic magnetoresistive sensor product, in order to solve the problem in the prior art that the dense arrangement of vias under the pads causes voids in the top metal layer, which in turn causes passivation protective layer residue, increased contact resistance and deterioration of product noise performance.

[0009] This application provides a method for improving the noise of a three-dimensional anisotropic magnetoresistive sensor product. The method includes the following steps: Step 1: Providing a substrate, on which an interconnect layer is provided, the interconnect layer including a lower metal layer, a dielectric layer and vias formed in the dielectric layer;

[0010] Step 2: Design and form a top metal layer, which is electrically connected to the lower metal layer through the via, and has pad areas on the top metal layer;

[0011] Step 3: Form a passivation protective layer on the top metal layer and open the pad area to expose part of the top metal layer for subsequent packaging connection;

[0012] In step two, the layout of the vias located below the pad area is optimized. The optimization design includes controlling the spacing between the vias and the distribution density of the vias in the pad area to reduce void defects generated when the top metal layer fills the vias.

[0013] Preferably, in step two, the layout optimization design of the vias specifically includes setting the spacing between adjacent vias within the pad area to be greater than 3 micrometers.

[0014] Preferably, in step two, the layout optimization design of the vias specifically includes controlling the data ratio of the vias within the pad area to be less than 10%.

[0015] Preferably, in step two, the optimized design is achieved by reducing the number of vias in the middle region of the pad area.

[0016] Preferably, in step two, the material of the top metal layer is selected from at least one of aluminum, copper, aluminum-copper alloy, aluminum-silicon-copper alloy, tungsten, titanium, titanium nitride, tantalum, and tantalum nitride.

[0017] Preferably, after step three, the method is further used in a wafer-level chip-scale packaging process, the wafer-level chip-scale packaging process including: forming a redistribution layer and setting solder balls, the solder balls being electrically connected to the pad area through the redistribution layer.

[0018] Preferably, the passivation protective layer comprises a polyimide material; the optimized design is used to avoid the polyimide material remaining at the void defects in the top metal layer during the development process of the passivation protective layer.

[0019] Preferably, in step one, the dielectric layer is an interlayer dielectric layer.

[0020] This application also provides a three-dimensional anisotropic magnetoresistive sensor product, manufactured using the method described above, the product comprising:

[0021] Base;

[0022] The lower metal layer is located above the substrate;

[0023] A dielectric layer, covering the underlying metal layer, and having through-holes;

[0024] A top metal layer is located above the dielectric layer and is electrically connected to the lower metal layer through the via. The top metal layer has pad areas.

[0025] A passivation protective layer partially covers the top metal layer;

[0026] The vias located below the pad area have a spacing greater than 3 micrometers, and the percentage of vias located inside the pad area is less than 10%.

[0027] As described above, the method and product for improving the noise of a three-dimensional anisotropic magnetoresistive sensor according to the present invention have the following beneficial effects:

[0028] This invention optimizes the via layout below the pad area before the top metal layer is formed. Specifically, the via spacing within the pads is increased to greater than 3 micrometers, and the via data ratio is controlled to less than 10%, effectively solving the surface morphology problem of the dielectric layer caused by dense vias. This design results in a denser and smoother deposited top metal layer (especially a thick aluminum layer), eliminating voids and defects inside and on the surface of the metal layer. Furthermore, in the subsequent passivation protection layer (such as polyimide) development process, it avoids the problem of photosensitive material being trapped deep in metal voids and unable to be removed. Eliminating polyimide residue ensures low and stable contact resistance between the top metal pads and the subsequently formed redistribution layer, thereby significantly reducing noise caused by abnormal contact resistance. In particular, it greatly improves the noise performance of AMR products, increasing the signal-to-noise ratio, measurement accuracy, and final wafer testing yield. Attached Figure Description

[0029] Figure 1 The diagram shows a cross-sectional view of the voids formed when the top metal layer is filled with dense through-holes in the conventional process of this application.

[0030] Figure 2 The diagram shows a flowchart illustrating the method for improving the noise of a three-dimensional anisotropic magnetoresistive sensor product according to this application.

[0031] Figure 3 This diagram illustrates a comparison of noise variability between the sensor product and other batches of products in this application embodiment. Detailed Implementation

[0032] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] This application provides a method for improving the noise of a three-dimensional anisotropic magnetoresistive sensor product, such as... Figure 2 The flowchart shown below illustrates the method, which includes the following steps:

[0034] Step 1: Provide a substrate with an interconnect layer on it. The interconnect layer includes a lower metal layer, a dielectric layer, and vias formed in the dielectric layer.

[0035] In some embodiments, the substrate may include a semiconductor substrate. The semiconductor substrate may be an elemental semiconductor, such as silicon (Si) or germanium (Ge); a compound semiconductor, such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); or an alloy semiconductor, such as silicon-germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium arsenide phosphide (GaInAsP). Furthermore, the substrate may also be a semiconductor-on-insulator (SOI) structure, such as silicon-on-insulator or germanium-on-insulator. The substrate may include various doping configurations, such as p-type or n-type substrates, depending on design requirements.

[0036] Various device elements can be formed on or within a substrate. These device elements include active and passive devices. Examples of active devices include, but are not limited to: transistors (e.g., MOSFETs, CMOS transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field-effect transistors (PFETs / NFETs), three-dimensional transistors), diodes, photodiodes, and / or magnetic sensing elements (such as Hall effect devices or AMR devices). Examples of passive devices include, but are not limited to: capacitors, resistors, inductors, fuses, and / or antifuses. These device elements can be formed in the front-end process (FEOL) of the substrate using any suitable semiconductor fabrication process (e.g., deposition, etching, implantation, photolithography, annealing, and / or other processes). Furthermore, isolation structures can be formed on the substrate to isolate the various device elements on the substrate. Isolation structures can include shallow trench isolation (STI) structures, localized silicon oxide (LOCOS) structures, or other suitable isolation components. Methods for forming isolation structures may include etching trenches in a substrate and filling the trenches with an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. An interconnect layer sits above the device elements and the isolation structure and is part of the back-to-order process (BEOL). The interconnect layer connects the device elements to each other through a series of conductivity characteristics to form a functional circuit.

[0037] The underlying metal layer is part of a multilayer interconnect structure on a substrate. The underlying metal layer can be formed using a single damascene process, a dual damascene process, or a deposition-etch process. Materials for the underlying metal layer can include copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), gold (Au), silver (Ag), titanium (Ti), tantalum (Ta), ruthenium (Ru), manganese (Mn), or combinations thereof. For example, the underlying metal layer can be formed of an aluminum-copper alloy (AlCu) sandwiched between a barrier / adhesion layer composed of titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). In another example, the underlying metal layer can include copper interconnects formed in a dielectric material and surrounded by a diffusion barrier layer (such as TaN / Ta). The formation process of the underlying metal layer can include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electrochemical plating (ECP), electroless plating, or other suitable deposition processes. After depositing the metal material, excess material can be removed and the surface planarized using a chemical mechanical planarization (CMP) process.

[0038] In some embodiments, the dielectric layer is an interlayer dielectric (IMD). The dielectric layer may include one or more layers of dielectric material. The material of the dielectric layer is selected from silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), fluorosilicone glass (FSG), silicon phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), undoped silicon glass (USG), and low-k dielectric materials (k value less than 3.9) or ultra-low-k (ELK) dielectric materials (k value less than 2.5). Examples of low-k dielectric materials include, but are not limited to, degelatinized gels, aerogels, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), polyimide, etc. The dielectric layer can be deposited by processes such as spin coating, CVD, high-density plasma CVD (HDP-CVD), plasma-enhanced CVD (PECVD), or flow CVD (FCVD). After deposition, a CMP process or an etch-back process can be performed to planarize the top surface of the dielectric layer.

[0039] Vias formed in a dielectric layer are used to electrically connect different metal layers in a vertical direction (e.g., connecting a lower metal layer and a subsequently formed top metal layer). The formation process of vias typically involves: forming a patterned photoresist layer on the dielectric layer; transferring the pattern into the dielectric layer to form a via opening, exposing a portion of the lower metal layer; and filling the via opening with a conductive material. Anisotropic dry etching processes (e.g., reactive ion etching, RIE) can be used to form the via opening. Before filling with conductive material, a pad layer or diffusion barrier layer (e.g., Ti, TiN, Ta, TaN) can be deposited along the sidewalls and bottom of the via opening. The conductive material filling the via can include tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru), or alloys thereof. For example, tungsten plugs can be deposited to fill the via using a CVD process. In another configuration, the via can be integrally formed with the upper-layer conductive lines using a dual damascene process and filled using a copper plating process. After filling, CMP process is used to remove excess conductive material from the surface of the dielectric layer, so that the top surface of the via is flush with the top surface of the dielectric layer.

[0040] Step 2: Design and form the top metal layer. The top metal layer is electrically connected to the lower metal layer through vias, and a pad area is provided on the top metal layer.

[0041] In some embodiments, the material of the top metal layer is selected from at least one of aluminum, copper, aluminum-copper alloy, aluminum-silicon-copper alloy, tungsten, titanium, titanium nitride, tantalum, and tantalum nitride. For example, an aluminum-copper alloy can be deposited as the main conductive layer using a sputtering process. Prior to this, titanium or titanium nitride can be deposited as a barrier or adhesion layer to prevent metal diffusion and enhance adhesion. In some embodiments, the top metal layer is made of thick aluminum material, which has good conductivity and ductility, making it suitable as a pad contact surface.

[0042] In step two, the layout of the vias located below the pad area is optimized. This optimization includes controlling the spacing between vias and their distribution density within the pad area to reduce void defects generated when the top metal layer fills the vias. Through this optimized design, the flatness of the dielectric layer surface can be improved, resulting in a denser and smoother deposited top metal layer, thereby eliminating or reducing void formation at its source.

[0043] In some embodiments, the via layout optimization design in step two specifically includes setting the spacing between adjacent vias within the pad area to be greater than 3 micrometers. By increasing the via spacing, the metal deposition process above each via becomes relatively independent, reducing stress concentration and morphological interference caused by adjacent vias, allowing the top layer metal to more fully fill and cover the via area, and avoiding micropores formed due to incomplete filling.

[0044] In some embodiments, step two, the via layout optimization design specifically includes: controlling the data ratio of vias within the pad area to less than 10%. The data ratio reflects the density of vias per unit area. Controlling this ratio to below 10% means that more flat dielectric layer support areas are retained below the pads, reducing the complexity of the surface topography and helping to obtain a smooth top metal layer.

[0045] In some embodiments, in step two, the optimized design is achieved by reducing the number of vias in the central region of the pad area. Typically, the central region of the pad experiences concentrated stress during encapsulation and is prone to becoming a void-prone area during metal deposition. Reducing the number of vias in the central region appropriately disperses the connection points to the periphery, ensuring electrical connectivity while avoiding areas prone to process defects, thereby improving product yield.

[0046] Step 3: Form a passivation protective layer on the top metal layer and create openings in the pad areas to expose portions of the top metal layer for subsequent packaging connections. The passivation protective layer provides moisture protection, corrosion protection, and mechanical protection. Materials typically used are photosensitive polyimide (PI), silicon nitride, or silicon oxide. The opening process is usually completed using photolithography and development (for photosensitive materials) or photolithography and etching (for non-photosensitive materials).

[0047] In some embodiments, the passivation protective layer comprises a polyimide (PI) material; the optimized design prevents polyimide material from remaining at voids in the top metal layer during the development process of the passivation protective layer. Polyimide is typically coated on the wafer surface as a photosensitive material. If voids or depressions exist on the surface of the top metal layer due to dense vias underneath, liquid or semi-solid PI material can seep into these microscopic defects. In subsequent development steps, the PI material trapped deep within the voids is difficult to completely rinse away by the developer, forming "PI residue." PI is an insulating material, and its residue directly covers the top metal surface. By optimizing the via layout in the aforementioned steps, voids on the metal surface are eliminated, resulting in a smooth metal surface under the PI layer. This allows the developer to flow smoothly and wash away all the PI material that should be removed, thereby exposing a clean metal contact surface.

[0048] In some embodiments, after step three, the method is further used in a wafer-level chip-scale packaging process, which includes forming a redistribution layer and setting solder balls, wherein the solder balls are electrically connected to the pad area through the redistribution layer.

[0049] Before forming the redistribution layer (RDL), a first polymer layer is typically deposited to cover the passivation protection layer and the exposed pad areas. The first polymer layer can be formed of polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, silicone resin, acrylate, photosensitive material, or other suitable dielectric material. Deposition processes can include spin coating, lamination, or chemical vapor deposition (CVD). Subsequently, the first polymer layer is patterned (e.g., by photolithography and etching / development) to form openings that expose the pad areas of the underlying top metal layer.

[0050] A redistribution layer (RDL) is formed on the first polymer layer and extends into the opening to make physical and electrical contact with the pad area. The redistribution layer is used to reroute the device's input / output (I / O) terminals from peripheral pad locations to other locations on the chip surface to accommodate an array of solder balls. The redistribution layer may include one or more conductive layers. The material of the redistribution layer may be selected from copper (Cu), aluminum (Al), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), tungsten (W), or alloys thereof. Methods for forming the redistribution layer may include: depositing a seed layer (e.g., a titanium / copper layer); forming a photoresist layer with an RDL pattern on the seed layer; depositing a conductive material (such as copper) on the exposed seed layer by electroplating or electroless plating processes; stripping the photoresist layer; and etching away portions of the seed layer not covered by the conductive material. In some embodiments, the redistribution layer may include a portion of an under-bump metal structure.

[0051] After forming the redistribution layer, a second polymer layer can be formed over the redistribution layer and the first polymer layer. The material and formation method of the second polymer layer can be similar to those of the first polymer layer. The second polymer layer is patterned to form an exposed portion of the under-bump metal structure opening of the redistribution layer. Solder balls or conductive bumps are placed on the redistribution layer at the under-bump metal structure opening. The solder balls achieve electrical connection to the pad area of ​​the top metal layer through the redistribution layer. The material of the solder balls can include lead (Pb), tin (Sn), silver (Ag), copper (Cu), bismuth (Bi), or alloys thereof. For example, the solder balls can be lead-free solders, such as tin-silver (Sn-Ag) or tin-silver-copper (SAC) solders. The conductive bumps can also be copper pillars, solder caps on copper pillars, or combinations thereof. The formation process of the solder balls or conductive bumps can include ball placement, electroplating, printing, or evaporation. After the solder balls are placed, a reflow soldering process is usually performed to melt the solder and form a good intermetallic compound bond with the underlying redistribution layer or under-bump metal structure layer.

[0052] In the WLCSP process, if PI residue exists in the preceding steps, it can cause an abnormal increase in the contact resistance between the RDL layer and the top metal pad (e.g., from the milliohm level to the ohm level or even an open circuit). The increase and instability of the contact resistance introduces additional thermal noise and shot noise, interfering with the weak magnetic signal detection of the AMR sensor, especially the signal readout in the vertical direction.

[0053] Figure 3 This is a graph showing the variability of noise. The horizontal axis represents different test batches or wafers, and the vertical axis represents the specific noise values. From... Figure 3 As can be seen, in the absence of this optimization method (or in traditional batches with low yield), the data points (black dots) exhibit significant divergence, with some noise values ​​reaching as high as 30 to 40, corresponding to high noise levels caused by unstable contact resistance. However, the product optimized using this embodiment (corresponding to the area close to the bottom or low-value data points in the figure) shows noise values ​​that are essentially stable near a baseline of 0, with excellent consistency and no obvious outliers. This further quantitatively confirms that the method of this application significantly reduces the noise of AMR products and improves the signal-to-noise ratio and measurement accuracy of the sensor by improving contact resistance stability. It is worth noting that throughout the packaging process, since the voids in the top metal layer have been eliminated through via layout optimization in the preceding steps, no polymer material remains on the metal surface near the pad area when coating the first polymer layer (such as the PI layer) or the second polymer layer. This ensures that the contact resistance between the redistribution layer and the pad area, as well as between the solder ball and the redistribution layer, remains at an extremely low level.

[0054] Accordingly, this application also provides a three-dimensional anisotropic magnetoresistive sensor product, manufactured using the method of any of the foregoing embodiments, the product comprising:

[0055] Base;

[0056] The lower metal layer is located above the substrate;

[0057] A dielectric layer that covers the underlying metal layer and has through-holes;

[0058] The top metal layer is located above the dielectric layer and is electrically connected to the lower metal layer through vias. The top metal layer has pad areas.

[0059] Passivation protective layer, partially covering the top metal layer;

[0060] Among them, the spacing of vias located below the pad area is greater than 3 micrometers, and the data ratio of vias located inside the pad area is less than 10%.

[0061] Sensors with this structure exhibit superior electrical contact characteristics by eliminating top-layer metal voids and the subsequent risk of PI residue. In packaging and testing, the product demonstrates higher consistency and reliability, avoiding yield losses due to excessive contact resistance. It is particularly suitable for applications requiring high magnetic field detection accuracy, such as smartphones, drones, and automotive electronics.

[0062] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0063] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving the noise of a three-dimensional anisotropic magnetoresistive sensor product, characterized in that, At least including: Step 1: Provide a substrate having an interconnect layer on the substrate, the interconnect layer including a lower metal layer, a dielectric layer and vias formed in the dielectric layer; Step 2: Design and form a top metal layer, which is electrically connected to the lower metal layer through the via, and has pad areas on the top metal layer; Step 3: Form a passivation protective layer on the top metal layer and open the pad area to expose part of the top metal layer for subsequent packaging connection; In step two, the layout of the vias located below the pad area is optimized. The optimization design includes controlling the spacing between the vias and the distribution density of the vias in the pad area to reduce void defects generated when the top metal layer fills the vias.

2. The method for improving the noise of a three-dimensional anisotropic magnetoresistive sensor product according to claim 1, characterized in that: In step two, the layout optimization design of the vias specifically includes setting the spacing between adjacent vias within the pad area to be greater than 3 micrometers.

3. The method for improving the noise of a three-dimensional anisotropic magnetoresistive sensor product according to claim 1, characterized in that: In step two, the layout optimization design of the vias specifically includes controlling the data ratio of the vias within the pad area to be less than 10%.

4. The method for improving the noise of a three-dimensional anisotropic magnetoresistive sensor product according to claim 1, characterized in that: In step two, the optimized design is achieved by reducing the number of vias in the middle region of the pad area.

5. The method for improving the noise of a three-dimensional anisotropic magnetoresistive sensor product according to claim 1, characterized in that: In step two, the material of the top metal layer is selected from at least one of aluminum, copper, aluminum-copper alloy, aluminum-silicon-copper alloy, tungsten, titanium, titanium nitride, tantalum, and tantalum nitride.

6. The method for improving the noise of a three-dimensional anisotropic magnetoresistive sensor product according to claim 5, characterized in that: After step three, the method is also used in a wafer-level chip-scale packaging process, which includes forming a redistribution layer and setting solder balls, wherein the solder balls are electrically connected to the pad area through the redistribution layer.

7. The method for improving the noise of a three-dimensional anisotropic magnetoresistive sensor product according to claim 6, characterized in that: The passivation protective layer comprises a polyimide material; the optimized design is used to avoid the polyimide material remaining at the void defects in the top metal layer during the development process of the passivation protective layer.

8. The method for improving the noise of a three-dimensional anisotropic magnetoresistive sensor product according to claim 1, characterized in that: In step one, the dielectric layer is an interlayer dielectric layer.

9. An improved three-dimensional anisotropic magnetoresistive sensor product, characterized in that, Manufactured using the method described in any one of claims 1 to 8, comprising: Base; The lower metal layer is located above the substrate; A dielectric layer, covering the underlying metal layer, and having through-holes; A top metal layer is located above the dielectric layer and is electrically connected to the lower metal layer through the via. The top metal layer has pad areas. A passivation protective layer partially covers the top metal layer; The vias located below the pad area have a spacing greater than 3 micrometers, and the percentage of vias located inside the pad area is less than 10%.

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