Method, system and device for detecting parasitic resistance and preparation method of transistor

Abstract

The invention provides a method, a system and equipment for detecting parasitic resistance and a preparation method of a transistor. The method comprises the following steps: providing a device to be tested; each transistor in the to-be-tested device comprises a front source-drain metal and a back source-drain metal which are oppositely arranged; applying excitation current between two adjacent front source drain metals, and measuring a generated bottom channel voltage value; applying excitation current between two adjacent back source drain metals, and measuring a generated top channel voltage value; applying excitation current between the front source-drain metal and the back source-drain metal which are oppositely arranged, and measuring a generated middle channel voltage value; determining a parasitic resistance value of each transistor based on the bottom channel voltage value, the middle channel voltage value, the top channel voltage value, and the current value and the voltage value of the excitation source; the parasitic resistance value includes at least one of the following: a front contact resistance value, a back contact resistance value, a front epitaxial resistance value, a back epitaxial resistance value, and a channel resistance value.

Description

Technical Field

[0001] This application relates to semiconductor detection technology, and more particularly to a method, system, apparatus for detecting parasitic resistance, and a method for fabricating transistors. Background Technology

[0002] With the trend of advanced semiconductor devices moving towards three-dimensional stacked and double-sided interconnect architectures, accurately measuring various parasitic resistances within the devices has become a key challenge for performance characterization and process optimization. Traditional resistance testing methods are usually based on the assumption of single-sided contact and planar current path, which are difficult to apply to novel device structures with vertically stacked channels, double-sided electrodes, and complex current paths. This makes it impossible to independently analyze the resistance contribution of different physical regions, limiting further optimization of the device structure. Summary of the Invention

[0003] This application provides a method, system, device for detecting parasitic resistance, and a method for fabricating a transistor, which can achieve independent extraction and separation of parasitic resistance in different physical regions of a transistor.

[0004] The technical solution of this application embodiment is implemented as follows:

[0005] This application provides a method for detecting parasitic resistance, comprising: providing a device under test (DUT); the DUT includes at least three transistors arranged side-by-side in a first direction, wherein each transistor includes a front source / drain metal and a back source / drain metal disposed opposite to each other; applying an excitation current between two adjacent front source / drain metals and measuring the resulting bottom channel voltage; applying an excitation current between two adjacent back source / drain metals and measuring the resulting top channel voltage; applying an excitation current between the opposite front source / drain metals and the back source / drain metals and measuring the resulting middle channel voltage; determining the parasitic resistance value of each transistor based on the bottom channel voltage value, the middle channel voltage value, the top channel voltage value, the current value and voltage value of the excitation source; the parasitic resistance value includes at least one of the following: front contact resistance value, back contact resistance value, front epitaxial resistance value, back epitaxial resistance value, and channel resistance value.

[0006] In some possible implementations, two adjacent transistors share a pair of front source / drain metals and back source / drain metals; the front source / drain metals of at least three transistors arranged side-by-side in a first direction include: a first front source / drain metal, a second front source / drain metal, a third front source / drain metal, and a fourth front source / drain metal; the back source / drain metals of the three transistors arranged side-by-side in a first direction include: a first back source / drain metal, a second back source / drain metal, a third back source / drain metal, and a fourth back source / drain metal; each transistor also includes a front source / drain lead-out structure and a back source / drain lead-out structure; the front source / drain lead-out structure is electrically connected to the front source / drain metal; the back source / drain lead-out structure is electrically connected to the back source / drain metal.

[0007] In some possible implementations, applying an excitation current between two adjacent front-side source-drain metals and measuring the resulting bottom channel voltage includes: allowing the excitation current to flow into the third front-side source-drain metal and out of the second front-side source-drain metal through a test node electrically connected to the second and third front-side source-drain metals; and measuring the bottom channel voltage through a test node electrically connected to the second and third back-side source-drain metals in a first circuit path in which the excitation current is generated.

[0008] In some possible implementations, applying an excitation current between two adjacent back-side source-drain metals and measuring the resulting top-channel voltage includes: allowing the excitation current to flow into the third back-side source-drain metal and out of the second back-side source-drain metal via a test node electrically connected to the third and second back-side source-drain metals; and measuring the top-channel voltage via a test node electrically connected to the second and third front-side source-drain metals in a second circuit path in which the excitation current is generated.

[0009] In some possible implementations, applying an excitation current between opposing front and back source / drain metals and measuring the resulting mid-channel voltage includes: allowing the excitation current to flow into the second front source / drain metal and out of the second back source / drain metal through a test node electrically connected to the second front and back source / drain metals; and measuring the mid-channel voltage through a test node electrically connected to the first back source / drain metal in a third circuit path where the excitation current is generated.

[0010] In some possible implementations, a first source / drain interconnect via is provided between the second front source / drain metal and the second back source / drain metal, and a second source / drain interconnect via is provided between the third front source / drain metal and the third back source / drain metal; the method further includes: electrically connecting a first test node to the second front source / drain metal through the first source / drain interconnect via; electrically connecting a sixth test node to the third front source / drain metal through the second source / drain interconnect via; electrically connecting a second test node to the second back source / drain metal, a third test node to the first back source / drain metal, a fourth test node to the fourth back source / drain metal, and a fifth test node to the third back source / drain metal through a back source / drain lead-out structure.

[0011] In some possible implementations, the method further includes: electrically connecting a first test node to a second front-side source / drain metal via a first via and an eighth test node; the first via providing a conductive path between the first test node and the eighth test node, the eighth test node being electrically connected to the second front-side source / drain metal; electrically connecting a sixth test node to a third front-side source / drain metal via a second via and a ninth test node; the second via providing a conductive path between the sixth test node and the ninth test node, the ninth test node being electrically connected to the third front-side source / drain metal; and electrically connecting a second test node to a second back-side source / drain metal, a third test node to a first back-side source / drain metal, a fourth test node to a fourth back-side source / drain metal, and a fifth test node to a third back-side source / drain metal via a back-side source / drain lead-out structure.

[0012] In some possible implementations, the parasitic resistance value of each transistor is determined based on the bottom channel potential value, the middle channel potential value, the top channel potential value, the current value and voltage value of the excitation source, including at least one of the following: calculating the channel resistance value based on the current value of the excitation source, the bottom channel potential value, the middle channel potential value, and the top channel potential value; calculating the front epitaxial resistance value and the back epitaxial resistance value based on the current value and voltage value of the excitation source and the middle channel potential value; calculating the front contact resistance value based on the front epitaxial resistance value, the current value and voltage value of the excitation source, and the middle channel potential value; and calculating the back contact resistance value based on the back epitaxial resistance value, the middle channel resistance value, and the current value of the excitation source.

[0013] This application provides a method for fabricating a transistor, which is applied to the above-mentioned method for detecting parasitic resistance. The method for fabricating the transistor includes: forming an active structure on a substrate; forming a source-drain epitaxial layer based on the active structure; forming a front-side source-drain metal on a first surface of the source-drain epitaxial layer, and forming a front-side source-drain lead-out structure on the front-side source-drain metal; flipping the wafer; forming a back-side source-drain metal on a second surface of the source-drain epitaxial layer, and forming a back-side source-drain lead-out structure on the back-side source-drain metal.

[0014] This application provides a parasitic resistance detection system for performing the above-described method for detecting parasitic resistance. The detection system includes: a first measurement module for acquiring the bottom channel voltage value of a device under test (DUT); the DUT includes at least three transistors arranged side-by-side in a first direction, wherein each transistor includes a front-side source / drain metal and a back-side source / drain metal disposed opposite to each other; the bottom channel voltage value is generated by applying an excitation current between two adjacent front-side source / drain metals; and a second measurement module for acquiring the top channel voltage value of the DUT; the top channel voltage value is generated by applying an excitation current between two adjacent front-side source / drain metals. The voltage is generated by applying an excitation current between two adjacent back-side source / drain metals; a third measurement module is used to acquire the middle channel voltage value of the device under test; the middle channel voltage value is generated by applying an excitation current between the front-side source / drain metals and the back-side source / drain metals that are arranged opposite to each other; a calculation module is used to determine the parasitic resistance value of the device under test based on the bottom channel voltage value, the middle channel voltage value, the top channel voltage value, the current value and voltage value of the excitation source; the parasitic resistance value includes at least one of the following: front contact resistance value, back contact resistance value, front epitaxial resistance value, back epitaxial resistance value and channel resistance value.

[0015] This application provides a testing device, including: one or more processors; and a storage device for storing one or more programs, which, when executed by one or more processors, cause the one or more processors to perform the above-described method for detecting parasitic resistance.

[0016] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0017] In the embodiments of this application, by introducing different current application strategies and utilizing the double-sided electrical access capability provided by the back contact structure, the parasitic resistance of different physical regions in the transistor can be independently extracted and separated.

[0018] Furthermore, the method described in this application embodiment is based on the double-sided electrical design of transistors, which can solve the fundamental defect of traditional single-sided Kelvin testing that cannot distinguish between the front contact resistance and the back contact resistance, as well as the front epitaxial resistance and the back epitaxial resistance values.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0021] Figure 1This is a schematic diagram illustrating one implementation process of the transistor fabrication method in this application.

[0022] Figure 2 This is a design layout of a transistor in an embodiment of this application.

[0023] Figures 3 to 11 This is a schematic flowchart of a transistor fabrication method in an embodiment of this application.

[0024] Figure 12 This is a schematic diagram illustrating one implementation process of the method for detecting parasitic resistance in this application.

[0025] Figure 13 This is a schematic diagram of the structure of the device under test in an embodiment of this application.

[0026] Figure 14 This is a schematic diagram of the current for the first excitation strategy in the embodiments of this application.

[0027] Figure 15 This is a schematic diagram of the current for the second excitation strategy in the embodiments of this application.

[0028] Figure 16 This is a schematic diagram of the current for the third excitation strategy in the embodiments of this application.

[0029] Figure 17 This is the first design layout of the device under test in the embodiments of this application.

[0030] Figure 18 This is a schematic diagram of the first connection method in the embodiments of this application.

[0031] Figure 19 This is a second design layout of the device under test in the embodiments of this application.

[0032] Figure 20 This is a schematic diagram of the second connection method in the embodiments of this application.

[0033] Figure 21 This is a schematic diagram of the resistor network of the device under test in an embodiment of this application.

[0034] Figure 22 This is a schematic diagram of the resistor network of the device under test under the first excitation strategy in an embodiment of this application.

[0035] Figure 23 This is a schematic diagram of the resistor network of the device under test under the second excitation strategy in an embodiment of this application.

[0036] Figure 24 This is a schematic diagram of the resistor network of the device under test under the third excitation strategy in an embodiment of this application.

[0037] Figure 25This is a schematic diagram of the parasitic resistance detection system in the embodiments of this application.

[0038] The reference numerals and names in the figure are as follows:

[0039] 11-Substrate; 12-Stacked structure; 13-Buffer oxide layer; 14-First hard mask; 15-Shallow trench isolation layer; 16-Pseudo-gate structure; 17-Sidewall; 18-Second hard mask; 19-Inner sidewall; 20-Placement structure; 21-Source / drain epitaxy; 22-Nanosheet structure; 23-Gate; 24-Front-side source / drain metal; 25-Interlayer dielectric layer; 26-Back-side source / drain metal. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0041] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0042] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0043] Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the embodiments of this application is for the purpose of describing the embodiments of this application only and is not intended to limit this application.

[0044] In gate-all-around field-effect transistors (GAA FETs), the total parasitic resistance mainly includes key components such as contact resistance (RCNT), epitaxial resistance, and internal channel resistance (RINT). Current methods for measuring parasitic resistance heavily rely on simulation and modeling, lacking physical verifiability and inline measurement capabilities. Traditional Kelvin testing methods can only measure current and voltage from the front side of the wafer, failing to distinguish the resistance contributions from the front and back sides of the device. Especially for multilayer stacked nanosheet structures, only the overall total equivalent resistance value can be obtained, without further analysis of the resistance composition of different layers or epitaxial regions. Furthermore, with the application of backside contact (BSC) technology, current paths can be formed on both the front and back sides of the device, making single-sided testing methods insufficient for measuring various parasitic resistances.

[0045] To address the aforementioned technical problems, embodiments of this application provide a method, system, device for detecting parasitic resistance, and a method for fabricating transistors, which can achieve independent extraction and separation of parasitic resistance in different physical regions of a transistor.

[0046] Figure 1 This is a schematic diagram of an implementation process of the transistor fabrication method in this application. See also... Figure 1 As shown, the method for fabricating the above-mentioned transistor includes:

[0047] In step 101, an active structure is formed on the substrate.

[0048] In some embodiments, a substrate is provided, and the substrate is subjected to processes such as photolithography and etching to form an active structure.

[0049] In some embodiments, the transistor may be a full-around-gate field-effect transistor.

[0050] In some embodiments, the active structure in a fully all-around gate field-effect transistor is a nanosheet structure.

[0051] In step 102, source-drain epitaxy is formed based on the active structure.

[0052] It should be noted that in the embodiments of this application, "source and drain" is an abbreviation for "source and / or drain".

[0053] In some embodiments, the active structure located in the source / drain region is etched to form a source / drain groove; a semiconductor material is epitaxially grown in the source / drain groove to form a source / drain epitaxy.

[0054] In some embodiments, the source / drain epitaxy can be formed by chemical vapor deposition (CVD), and the thickness and doping concentration of the source / drain epitaxy can be adjusted according to specific application requirements.

[0055] In step 103, a front source / drain metal is formed on the first surface of the source / drain epitaxial layer, and a front source / drain lead-out structure is formed on the front source / drain metal.

[0056] In some embodiments, trenches are etched on the surface of the source-drain epitaxial layer away from the substrate (i.e., the first surface) to form a front-side source-drain metal trench; conductive material is deposited in the front-side source-drain metal trench to form a front-side source-drain metal. The front-side source-drain metal is used to electrically connect the source-drain epitaxial layer and external circuitry on the front side of the transistor.

[0057] In some embodiments, a dielectric material is deposited on the front source / drain metal to form a first dielectric layer, and a first groove is formed by photolithography and etching of the first dielectric layer; a conductive material is deposited in the first groove to form a front source / drain lead-out structure; the front source / drain lead-out structure is used to electrically connect the front source / drain metal and an external circuit.

[0058] In step 104, the wafer is flipped.

[0059] In some embodiments, after the front structure of the transistor is fabricated on the front side, a wafer flipping (i.e., wafer flipping) process is performed. After flipping, the substrate is removed so that the back side of the wafer is placed facing up, which facilitates the continuation of subsequent processes.

[0060] In step 105, a back source / drain metal is formed on the second surface of the source / drain epitaxial layer, and a back source / drain lead-out structure is formed on the back source / drain metal.

[0061] In some embodiments, trenches are etched on a surface (i.e., a second surface) disposed opposite to the first surface in the source-drain epitaxial layer to form a back-side source-drain metal groove; conductive material is deposited in the back-side source-drain metal groove to form a back-side source-drain metal. The back-side source-drain metal is used to electrically connect the source-drain epitaxial layer and external circuitry on the back side of the transistor.

[0062] In some embodiments, a dielectric material is deposited on the back source / drain metal to form a second dielectric layer, and a second groove is formed by photolithography and etching of the second dielectric layer; a conductive material is deposited in the second groove to form a back source / drain lead-out structure; the back source / drain lead-out structure is used to electrically connect the back source / drain metal and an external circuit.

[0063] In one example, Figure 2 This is a design layout of a transistor in an embodiment of this application; Figures 3 to 11This is a schematic flowchart illustrating a method for fabricating a transistor according to an embodiment of this application. Below, we will take a fully all-around gate field-effect transistor as an example, combined with... Figures 2 to 11 The method for fabricating transistors is explained.

[0064] It should be noted that each step of the fabrication process diagram includes three cross-sectional views, corresponding to the sections a, b, and c marked on the design layout.

[0065] Step 1: See Figure 3 As shown, a stacked structure 12 is formed by alternately depositing a first semiconductor material (such as silicon-germanium) and a second semiconductor material (such as silicon) on a substrate 11. A buffer oxide layer 13 and a first hard mask 14 are formed on the stacked structure 12.

[0066] Step 2: See Figure 4 As shown, under the etch blocking effect of the first hard mask 14, the stacked structure 12 and the substrate 11 are etched to remove the first hard mask 14, and an oxide of a predetermined height is deposited in the groove formed by the etching to form a shallow trench isolation (STI) layer 15; then, polysilicon is deposited in the gate region to form a pseudo gate structure 16; sidewalls 17 are formed on the sidewalls of the pseudo gate structure 16; and a second hard mask 18 is formed.

[0067] Step 3: See Figure 5 As shown, under the etch blocking effect of the second hard mask 18, the stacked structure 12 located in the source and drain regions is etched to expose the source and drain regions; and the first semiconductor material in the stacked structure 12 is etched laterally, and an insulating medium is deposited in the trench formed by the lateral etching of the stacked structure 12 to form the inner sidewall 19.

[0068] Step 4: See Figure 6 As shown, in the source / drain region, a substrate 11 of a predetermined height is etched, and an insulating material is deposited in the groove formed by the etching to form a vacancy structure 20; a source / drain epitaxial layer 21 is formed; and a dielectric material is deposited to form an inter-layer dielectric (ILD) layer 25.

[0069] Step 5: See Figure 7 As shown, the pseudo-gate structure 16 is removed, and the first semiconductor material in the stacked structure 12 is removed to release the channel and form a nanosheet structure 22; the gate region is filled with metal (such as tungsten) to form a gate 23.

[0070] Step 6: See Figure 8 As shown, trenches are etched on the first surface of the source / drain epitaxial layer 21 to form a front source / drain metal groove, and conductive material is deposited in the front source / drain metal groove and on the source / drain epitaxial layer to form a front source / drain metal 24.

[0071] Step 7: See Figure 9 As shown, the substrate 11 is flipped and removed. The trench formed after removing the substrate 11 is filled with dielectric material to form an interlayer dielectric layer 25, which is then ground flat.

[0072] Step 8: See Figure 10 As shown, the occupant structure 20 is removed, and trenches are etched on the second surface of the source-drain epitaxial layer 21 to form a back source-drain metal groove. Conductive material is deposited in the back source-drain metal groove and the groove left after removing the occupant structure 20 to form the back source-drain metal 26.

[0073] Step 9: See Figure 11 As shown, the wafer is flipped, and the transistor fabrication is complete.

[0074] The embodiments of this application are based on a method for detecting parasitic resistance using a transistor prepared according to the above method.

[0075] Figure 12 This is a schematic diagram illustrating one implementation process of the method for detecting parasitic resistance in this application. See also... Figure 12 As shown, the above method for detecting parasitic resistance includes:

[0076] In step 1201, a device under test is provided.

[0077] In some embodiments, the device under test includes at least three transistors arranged side by side in a first direction, wherein each transistor includes a front source / drain metal and a back source / drain metal arranged opposite to each other.

[0078] In some embodiments, the device under test includes three or more transistors to provide the necessary electrical connection nodes.

[0079] In some possible implementations, two adjacent transistors share a pair of front source / drain metals and back source / drain metals; the front source / drain metals of at least three transistors arranged side-by-side in a first direction include: a first front source / drain metal, a second front source / drain metal, a third front source / drain metal, and a fourth front source / drain metal; the back source / drain metals of the three transistors arranged side-by-side in a first direction include: a first back source / drain metal, a second back source / drain metal, a third back source / drain metal, and a fourth back source / drain metal; each transistor also includes a front source / drain lead-out structure and a back source / drain lead-out structure; the front source / drain lead-out structure is electrically connected to the front source / drain metal; the back source / drain lead-out structure is electrically connected to the back source / drain metal.

[0080] In one example, Figure 13 This is a schematic diagram of the structure of the device under test in one embodiment of this application. Figure 13The device under test shown includes three transistors, T1, T2, and T3. Each transistor has a front-side source-drain metal layer on the front side of its source-drain epitaxial layer and a back-side source-drain metal layer on the back side. Adjacent transistors share a single pair of source-drain metal layers (i.e., front-side and back-side source-drain metal layers), which simplifies layout design and reduces the number of test nodes.

[0081] See Figure 13 As shown, in the first direction, from left to right, the front-side source / drain metals in the device under test include: a first front-side source / drain metal, a second front-side source / drain metal, a third front-side source / drain metal, and a fourth front-side source / drain metal. The second and third front-side source / drain metals are shared front-side source / drain metals.

[0082] See Figure 13 As shown, in the first direction, from left to right, the back-side source / drain metals in the device under test include: a first back-side source / drain metal, a second back-side source / drain metal, a third back-side source / drain metal, and a fourth back-side source / drain metal. The second and third back-side source / drain metals are shared back-side source / drain metals.

[0083] It should be noted that, Figure 13 The transistor shown includes three channels for illustrative purposes only, representing a top channel, a middle channel, and a bottom channel. This application does not impose a specific limitation on the number of channels in a transistor; during testing, it is sufficient to divide the channels into top, middle, and bottom channels.

[0084] In some embodiments, each source / drain metal has a corresponding source / drain lead-out structure. For example, in a first direction, the front-side source / drain lead-out structures in the device under test include: a first front-side source / drain lead-out structure, a second front-side source / drain lead-out structure, a third front-side source / drain lead-out structure, and a fourth front-side source / drain lead-out structure; each corresponding to a first front-side source / drain metal, a second front-side source / drain metal, a third front-side source / drain metal, and a fourth front-side source / drain metal, respectively. Similarly, the back-side source / drain lead-out structures in the device under test include: a first back-side source / drain lead-out structure, a second back-side source / drain lead-out structure, a third back-side source / drain lead-out structure, and a fourth back-side source / drain lead-out structure; each corresponding to a first back-side source / drain metal, a second back-side source / drain metal, a third back-side source / drain metal, and a fourth back-side source / drain metal, respectively.

[0085] In some embodiments, the source / drain metal is electrically connected to the corresponding source / drain metal lead-out structure. For example, the first front source / drain metal is electrically connected to the first front source / drain lead-out structure, and the first back source / drain metal is electrically connected to the first back source / drain lead-out structure.

[0086] In some embodiments, the source-drain lead-out structure (including a front source-drain lead-out structure and a back source-drain lead-out structure) provides an electrical connection between external test equipment (such as test pads or probe contacts) and the source-drain metal; enabling the excitation current from the excitation source to be accurately injected and the voltage signal to be accurately measured.

[0087] In step 1202, an excitation current is applied between two adjacent front source / drain metals, and the resulting bottom channel voltage is measured.

[0088] In some embodiments, according to the first excitation strategy, two terminals from the excitation source are respectively connected to two adjacent front-side source-drain lead-out structures. Since the front-side source-drain lead-out structures are electrically connected to the front-side source-drain metal, the excitation current can flow in and out between the two adjacent front-side source-drain metals. In the closed loop generated under the first excitation strategy, the main current path is distributed at the top and middle of the channel, while the current flowing through the bottom channel is very small. It is this tiny current flowing through the bottom channel that generates a precisely measurable voltage drop across its own channel resistance.

[0089] In step 1203, an excitation current is applied between two adjacent back-side source-drain metals, and the resulting top channel voltage is measured.

[0090] In some embodiments, according to the second excitation strategy, the two terminals from the excitation source are respectively connected to two adjacent back-side source-drain lead-out structures. Since the back-side source-drain lead-out structures are electrically connected to the back-side source-drain metal, the excitation current can flow in and out between the two adjacent back-side source-drain metals. In the closed loop generated under the second excitation strategy, the main current path is distributed at the bottom and middle of the channel, while the current flowing through the top channel is very small. It is this tiny current flowing through the top channel that generates a precisely measurable voltage drop across its own channel resistance.

[0091] In step 1204, an excitation current is applied between the front source / drain metal and the back source / drain metal that are positioned opposite each other, and the resulting mid-channel voltage value is measured.

[0092] In some embodiments, according to the third excitation strategy, two terminals from the excitation source are connected to the front source-drain lead-out structure and the corresponding back source-drain lead-out structure, respectively, so that the excitation current flows in from the front source-drain metal and flows out from the corresponding back source-drain metal. In the third excitation strategy, the current flow path is vertical, and almost no current is shunted into the middle channel. It is precisely under the premise of no channel current shunting that the accurate middle channel voltage value can be measured.

[0093] In step 1205, the parasitic resistance value of each transistor is determined based on the bottom channel voltage value, the middle channel voltage value, the top channel voltage value, the current value and voltage value of the excitation source current; the parasitic resistance value includes at least one of the following: front contact resistance value, back contact resistance value, front epitaxial resistance value, back epitaxial resistance value and channel resistance value.

[0094] In some embodiments, based on all the electrical measurement data obtained in steps 1202 to 1204, the parasitic resistance values ​​generated in different physical regions of the device under test can be calculated by solving a system of equations. It should be noted that the parasitic resistance value of the device under test represents the parasitic resistance value of each transistor in the device under test.

[0095] In some embodiments, the parasitic resistance value includes at least one of the following: front contact resistance value, back contact resistance value, front epitaxial resistance value, back epitaxial resistance value, and channel resistance value. Different parasitic resistance values ​​correspond to different physical regions and interfaces within the transistor.

[0096] In the embodiments of this application, by introducing different current application strategies and utilizing the double-sided electrical access capability provided by the back contact structure, the parasitic resistance of different physical regions in the transistor can be independently extracted and separated.

[0097] Furthermore, the method described in the embodiments of this application is based on the double-sided electrical design of transistors, which can solve the fundamental defect of traditional single-sided Kelvin testing that cannot distinguish between the front contact resistance and the back contact resistance, as well as the front epitaxial resistance and the back epitaxial resistance values.

[0098] In some possible implementations, step 1202 may include: a test node electrically connected to the second front source-drain metal and the third front source-drain metal, such that excitation current flows into the third front source-drain metal and flows out of the second front source-drain metal; and in the first circuit path in which the excitation current is generated, a test node electrically connected to the second back source-drain metal and the third back source-drain metal measures the bottom channel voltage value.

[0099] In some embodiments, Figure 14 This is a schematic diagram of the current for the first excitation strategy in the embodiments of this application; see also Figure 14 As shown, according to the first excitation strategy, the two terminals of the excitation source are electrically connected to the third and second front-side source / drain metals in the device under test (DUT) through the front-side source / drain lead-out structure, respectively, so that the excitation current flows in from the third front-side source / drain metal and flows out from the second front-side source / drain metal. The current flows through the top channel, the middle channel, and the bottom channel.

[0100] In some embodiments, the current path generated by the first excitation strategy is a first circuit path. See also Figure 14 As shown, the second and third back-side source / drain metals are electrically connected to the test node via a back-side source / drain lead-out structure to measure the bottom channel voltage. The first and fourth back-side source / drain metals are electrically connected to the test node to measure the middle channel voltage. Figure 14 The dashed line represents the measurement path of the test voltage, and the solid line represents the first circuit path of the excitation current.

[0101] In some possible implementations, step 1203 may include: an excitation current flowing into the third back-side source-drain metal and out of the second back-side source-drain metal via a test node electrically connected to the third back-side source-drain metal and the second back-side source-drain metal; and measuring the top channel voltage value via a test node electrically connected to the second front-side source-drain metal and the third front-side source-drain metal in the second circuit path in which the excitation current is generated.

[0102] In some embodiments, Figure 15 This is a schematic diagram of the current for the second excitation strategy in an embodiment of this application; see also Figure 15 As shown, according to the second excitation strategy, the two terminals of the excitation source are electrically connected to the third and second back-side source-drain metals in the device under test through the back-side source-drain lead-out structure, respectively, so that the excitation current flows in from the third back-side source-drain metal and flows out from the second back-side source-drain metal. The current flows through the top channel, the middle channel, and the bottom channel.

[0103] In some embodiments, the current path generated by the second excitation strategy is a second circuit path. See also Figure 15 As shown, the second and third front-side source / drain metals are electrically connected to the test node via a front-side source / drain lead-out structure to measure the top channel voltage. The first and fourth back-side source / drain metals are electrically connected to the test node to measure the middle channel voltage. Figure 15 The dashed line represents the measurement path of the test voltage, and the solid line represents the second circuit path of the excitation current.

[0104] In some possible implementations, step 1204 may include: allowing excitation current to flow into the second front source-drain metal and out of the second back source-drain metal via a test node electrically connected to the second front source-drain metal and the second back source-drain metal; and measuring the middle channel voltage value via a test node electrically connected to the first back source-drain metal in a third circuit path in which the excitation current is generated.

[0105] In some embodiments, Figure 16 This is a schematic diagram of the current for the third excitation strategy in the embodiments of this application; see also Figure 16As shown, according to the third excitation strategy, the two terminals of the excitation source are electrically connected to the second front-side source-drain metal and the second back-side source-drain metal in the device under test through the front-side source-drain junction and the back-side source-drain structure, respectively, so that the excitation current flows in from the second front-side source-drain metal and flows out from the second back-side source-drain metal. The current flows longitudinally from the second front-side source-drain metal to the second back-side source-drain metal.

[0106] In some embodiments, the current path generated by the third excitation strategy is a third circuit path. See also Figure 16 As shown, the first back-side source / drain metal is electrically connected to the test node through the back-side source / drain lead-out structure to measure the voltage value of the middle channel. Figure 16 The dashed line represents the measurement path of the test voltage, and the solid line represents the third circuit path of the excitation current.

[0107] In some possible implementations, to simplify the testing method, the test nodes can be arranged on the same side of the device under test; for example, if the test nodes are arranged on the back side of the device under test, in order to achieve electrical connection between the test nodes and the front source / drain metal, a source / drain interconnect via can be provided between the front source / drain metal and the back source / drain metal, so that the test nodes on the back side can be electrically connected to the front source / drain metal from the back side through the source / drain interconnect via.

[0108] In some possible implementations, a first source-drain interconnect via is provided between the second front source-drain metal and the second back source-drain metal, and a second source-drain interconnect via is provided between the third front source-drain metal and the third back source-drain metal; the above-described method for detecting parasitic resistance may further include: electrically connecting a first test node to the second front source-drain metal through the first source-drain interconnect via; electrically connecting a sixth test node to the third front source-drain metal through the second source-drain interconnect via; electrically connecting a second test node to the second back source-drain metal, a third test node to the first back source-drain metal, a fourth test node to the fourth back source-drain metal, and a fifth test node to the third back source-drain metal through a back source-drain lead-out structure.

[0109] In some embodiments, Figure 17 This is the first design layout of the device under test in this application embodiment. Figure 17 Figure (a) in the image is the front view. Figure 17 Figure (b) in the diagram is the reverse side view. (Participate) Figure 17 As shown, the device under test includes a gate lead-out structure and a source-drain interconnect via, in addition to the source-drain metal and source-drain lead-out structure. The gate lead-out structure is used to electrically connect the gate to external circuitry, and the source-drain interconnect via is used to electrically connect the back source-drain metal and the front source-drain metal.

[0110] In the embodiments of this application, the active region refers to a portion of semiconductor material on a substrate (such as a silicon wafer) that, after being defined and processed by a specific process, can form the effective working area of ​​a transistor. In a fully all-around gate field-effect transistor, the active region is a plurality of parallel nanosheets.

[0111] It should be noted that the structures, shapes and relative positions shown in the schematic diagrams and design layouts of the various fabrication processes in the embodiments of this application are merely illustrative and are used to illustrate the structural features and positional relationships of the transistors in the embodiments of this application. They are not intended to precisely limit the actual size, proportion or process details of the device.

[0112] See Figure 17 As shown, to avoid short circuits after power-on, the back source / drain metal is disconnected. The disconnected back source / drain metal is divided into two parts. One part of the back source / drain metal has only a back source / drain lead-out structure to provide a conductive path from the outside to the back source / drain metal. The other part of the back source / drain metal has source / drain interconnect vias and a back source / drain lead-out structure. The positions of the source / drain interconnect vias and the back source / drain lead-out structure can overlap to provide a conductive path from the outside to the back source / drain metal, as well as a conductive path from the back source / drain metal to the front source / drain metal.

[0113] The following explains... Figure 17 The connection method used to detect parasitic resistance on the device under test is shown. Figure 18 This is a schematic diagram of the first connection method in the embodiments of this application; see also Figure 18 As shown, the first test node (Pad1) is electrically connected to the second front source / drain metal via a first source / drain interconnect on the second back source / drain metal. The sixth test node (Pad6) is electrically connected to the third front source / drain metal via a second source / drain interconnect on the third back source / drain metal. The second test node (Pad2) is electrically connected to the second back source / drain metal via a second back source / drain lead-out structure. The third test node (Pad3) is electrically connected to the first back source / drain metal via a first back source / drain lead-out structure. The fourth test node (Pad4) is electrically connected to the fourth back source / drain metal via a fourth back source / drain lead-out structure. The fifth test node (Pad5) is electrically connected to the third back source / drain metal via a third back source / drain lead-out structure. The gate lead-out structures in the device under test are connected in parallel and electrically connected to the seventh test node (Pad7), which is connected to a constant voltage source.

[0114] See one example. Figure 18 As shown, in the first excitation strategy, the excitation current enters the device under test from the sixth test node and flows out from the first test node. The bottom channel voltage is measured through the second and fifth test nodes. The middle channel voltage is measured through the third and fourth test nodes.

[0115] See one example. Figure 18 As shown, in the second excitation strategy, the excitation current enters the device under test from the fifth test node and flows out from the second test node. The top channel voltage is measured through the first and sixth test nodes. The middle channel voltage is measured through the third and fourth test nodes.

[0116] See one example. Figure 18 As shown, in the third excitation strategy, the excitation current enters the device under test from the first test node and flows out from the second test node. The mid-channel voltage is measured through the third test node.

[0117] In some possible implementations, to simplify the testing method, vias can be provided between the test nodes on the front and back sides to provide a conductive path between the test nodes at both ends. This allows for electrical connection between the source / drain metal on the front side and the test nodes located on the back side of the device under test.

[0118] In some possible implementations, the above-described method for detecting parasitic resistance may further include: electrically connecting a first test node to a second front-side source / drain metal via a first via and an eighth test node; the first via providing a conductive path between the first test node and the eighth test node, the eighth test node being electrically connected to the second front-side source / drain metal; electrically connecting a sixth test node to a third front-side source / drain metal via a second via and a ninth test node; the second via providing a conductive path between the sixth test node and the ninth test node, the ninth test node being electrically connected to the third front-side source / drain metal; and electrically connecting a second test node to a second back-side source / drain metal, a third test node to a first back-side source / drain metal, a fourth test node to a fourth back-side source / drain metal, and a fifth test node to a third back-side source / drain metal via a back-side source / drain lead-out structure.

[0119] In some embodiments, Figure 19 This is a second design layout of the device under test in this application embodiment. Figure 19 Figure (a) in the image is the front view. Figure 18 Figure (b) in the diagram is the reverse side view. (Participate) Figure 19 As shown, the device under test includes a gate lead-out structure in addition to the source / drain metal and source / drain lead-out structure. The gate lead-out structure is used to electrically connect the gate to external circuitry.

[0120] The following explains... Figure 19 The connection method used to detect parasitic resistance on the device under test is shown. Figure 20 This is a schematic diagram of the second connection method in the embodiments of this application; see also Figure 20As shown, the first test node (Pad1) and the eighth test node (Pad8) are electrically connected through the first via, with the eighth test node connected to the second front-side source / drain metal; the first test node is electrically connected to the second front-side source / drain metal through the eighth test node and the first via. The sixth test node (Pad6) and the ninth test node (Pad9) are electrically connected through the second via, with the ninth test node connected to the third front-side source / drain metal; the sixth test node is electrically connected to the third front-side source / drain metal through the ninth test node and the second via. The second test node (Pad2) is electrically connected to the second back-side source / drain metal through the second back-side source / drain lead-out structure. The third test node (Pad3) is electrically connected to the first back-side source / drain metal through the first back-side source / drain lead-out structure. The fourth test node (Pad4) is electrically connected to the fourth back-side source / drain metal through the fourth back-side source / drain lead-out structure. The fifth test node (Pad5) is electrically connected to the third back-side source / drain metal through the third back-side source / drain lead-out structure. The gate lead-out structures in the device under test are connected in parallel and electrically connected to the seventh test node (i.e., Pad7), which is connected to a constant voltage source.

[0121] See one example. Figure 20 As shown, in the first excitation strategy, the excitation current enters the device under test from the sixth test node. The sixth test node is electrically connected to the ninth test node through the second via. The ninth test node is electrically connected to the third front-side source-drain metal, which is electrically connected to the second front-side source-drain metal. The excitation current flows from the second front-side source-drain metal into the eighth excitation power supply and finally flows out from the first test node. The bottom channel voltage is measured through the second and fifth test nodes. The middle channel voltage is measured through the third and fourth test nodes.

[0122] See one example. Figure 20 As shown, in the second excitation strategy, the excitation current enters the device under test from the fifth test node and flows out from the second test node. The top channel voltage is measured through the first and sixth test nodes. The middle channel voltage is measured through the third and fourth test nodes.

[0123] See one example. Figure 20 As shown, in the third excitation strategy, the excitation current enters the device under test from the first test node and flows out from the second test node. The mid-channel voltage is measured through the third test node.

[0124] In some embodiments, Figure 21 This is a schematic diagram of the resistor network of the device under test in an embodiment of this application. Figure 21 As shown, R FCNT R represents the front contact resistance. BCNT R represents the back contact resistance. epi1R represents the front-side epitaxial resistance. epi2 R represents the back-side epitaxial resistance. INT1 R represents the top channel resistance. INT2 R represents the resistance of the middle channel. INT3 This indicates the bottom channel resistance.

[0125] In some embodiments, Figure 22 This is a schematic diagram of the resistor network of the device under test under the first excitation strategy in an embodiment of this application. See also... Figure 22 As shown, the direction of the excitation current is indicated by arrows. The top, middle, and bottom channels are connected in parallel, and the excitation current enters and exits from the front. The test voltage signal is represented by dashed lines. Figure 22 The bid was successful.

[0126] In some embodiments, Figure 23 This is a schematic diagram of the resistor network of the device under test under the second excitation strategy in an embodiment of this application. See also... Figure 23 As shown, the direction of the excitation current is indicated by arrows. The top, middle, and bottom channels are connected in parallel, and the excitation current enters from the back and flows out from the back. The test voltage signal is represented by dashed lines. Figure 23 The bid was successful.

[0127] In some embodiments, Figure 24 This is a schematic diagram of the resistor network of the device under test under the third excitation strategy in an embodiment of this application. See also... Figure 24 As shown, the direction of the excitation current is indicated by arrows. The front source / drain metal, front source / drain epitaxial layer, back source / drain epitaxial layer, and back source / drain metal are connected in series. The excitation current enters from the front and flows out from the back. The test voltage signal is represented by dashed lines. Figure 24 The bid was successful.

[0128] In some possible implementations, step 1205 may include at least one of the following: calculating the channel resistance value based on the current value of the excitation source, the bottom channel potential value, the middle channel potential value, and the top channel potential value; calculating the front epitaxial resistance value and the back epitaxial resistance value based on the current value and voltage value of the excitation source and the middle channel potential value; calculating the front contact resistance value based on the front epitaxial resistance value, the current value and voltage value of the excitation source, and the middle channel potential value; and calculating the back contact resistance value based on the back epitaxial resistance value, the middle channel resistance value, and the current value of the excitation source.

[0129] In some embodiments, the expression (1) for calculating the channel resistance value based on the current value of the excitation source, the bottom channel potential value, the middle channel potential value, and the top channel potential value is as follows:

[0130] (1)

[0131] In expression (1), I Force I represents the current value of the excitation source (the current value of the excitation source is known). INT Represents the channel current, ΔU INT R represents the average of the bottom channel voltage, the middle channel voltage, and the top channel voltage. INT This indicates the channel resistance value.

[0132] In some embodiments, based on the current and voltage values ​​of the excitation source and the potential value of the middle channel, the expression (2) for calculating the front epitaxial resistance value and the back epitaxial resistance value is as follows:

[0133] (2)

[0134] In expression (2), I INT U represents the channel current. Force U represents the voltage value of the excitation source (the voltage value of the excitation source is known). Mid R represents the middle channel voltage value. Epi1 R represents the front-side epitaxial resistance value. Epi2 This indicates the value of the back-side epitaxial resistance.

[0135] In some embodiments, based on the front epitaxial resistance value, the current and voltage values ​​of the excitation source, and the potential value of the middle channel, the expression (3) for calculating the front contact resistance value is as follows:

[0136] (3)

[0137] In expression (3), U Force U represents the voltage value of the excitation source (the voltage value of the excitation source is known). Mid Indicates the middle channel voltage value, I Force R represents the current value of the excitation source (the current value of the excitation source is known). Epi1 R represents the front-side epitaxial resistance value. FCNT This indicates the resistance value of the front contact.

[0138] In some embodiments, based on the back epitaxial resistance value, the middle channel resistance value, and the current value of the excitation source, the expression (4) for calculating the back contact resistance value is as follows:

[0139] (4)

[0140] In expression (4), I Force U represents the current value of the excitation source (the current value of the excitation source is known). Mid R represents the middle channel voltage value. Epi2 R represents the back-side epitaxial resistance value.BCNT This indicates the back contact resistance value.

[0141] The following describes an exemplary structure of the parasitic resistance detection system provided in this application embodiment as a software module. Figure 25 This is a schematic diagram of a parasitic resistance detection system according to an embodiment of this application. In some embodiments, such as Figure 25 As shown, the software modules in the parasitic resistance detection system 2500 may include: a first measurement module 2501 for acquiring the bottom channel voltage value of the device under test; the device under test includes at least three transistors arranged side-by-side in a first direction, wherein each transistor includes front-side source-drain metals and back-side source-drain metals arranged opposite each other; the bottom channel voltage value is generated by applying an excitation current between two adjacent front-side source-drain metals; a second measurement module 2502 for acquiring the top channel voltage value of the device under test; the top channel voltage value is generated by applying an excitation current between two adjacent back-side source-drain metals. The third measurement module 2503 is used to acquire the middle channel voltage value of the device under test; the middle channel voltage value is generated by applying an excitation current between the front source / drain metal and the back source / drain metal that are disposed opposite to each other; the calculation module 2504 is used to determine the parasitic resistance value of the device under test based on the bottom channel voltage value, the middle channel voltage value, the top channel voltage value, the current value and the voltage value of the excitation source; the parasitic resistance value includes at least one of the following: front contact resistance value, back contact resistance value, front epitaxial resistance value, back epitaxial resistance value and channel resistance value.

[0142] In some possible implementations, the calculation module 2504 is used to calculate the channel resistance value based on the current value of the excitation source, the bottom channel potential value, the middle channel potential value, and the top channel potential value; to calculate the front epitaxial resistance value and the back epitaxial resistance value based on the current value and voltage value of the excitation source and the middle channel potential value; to calculate the front contact resistance value based on the front epitaxial resistance value, the current value and voltage value of the excitation source, and the middle channel potential value; and to calculate the back contact resistance value based on the back epitaxial resistance value, the middle channel resistance value, and the current value of the excitation source.

[0143] This application provides a testing device, including: one or more processors; and a storage device for storing one or more programs, which, when executed by one or more processors, cause the one or more processors to perform a method for detecting parasitic resistance.

[0144] In some embodiments, a test device refers to a device composed of a variety of electronic components that is capable of performing a specific function.

[0145] The above are merely preferred embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for detecting parasitic resistance, characterized in that, include: Provide a device under test; The device under test includes at least three transistors arranged side by side in a first direction, wherein each transistor includes a front source / drain metal and a back source / drain metal arranged opposite to each other; An excitation current is applied between two adjacent front-side source-drain metals, and the resulting bottom channel voltage is measured. The excitation current is applied between two adjacent back-side source-drain metals, and the resulting top-channel voltage is measured. An excitation current is applied between the front and back source / drain metals that are positioned opposite each other, and the resulting mid-channel voltage is measured. Based on the bottom channel voltage value, the middle channel voltage value, the top channel voltage value, the current value and voltage value of the excitation source, the parasitic resistance value of each transistor is determined; the parasitic resistance value includes at least one of the following: front contact resistance value, back contact resistance value, front epitaxial resistance value, back epitaxial resistance value and channel resistance value.

2. The method according to claim 1, characterized in that, Two adjacent transistors share a pair of front-side source-drain metal and back-side source-drain metal; The front source / drain metals of the at least three transistors arranged side by side in the first direction include: a first front source / drain metal, a second front source / drain metal, a third front source / drain metal, and a fourth front source / drain metal; The back-side source / drain metals of the three transistors arranged side-by-side in the first direction include: a first back-side source / drain metal, a second back-side source / drain metal, a third back-side source / drain metal, and a fourth back-side source / drain metal; Each transistor further includes a front-side source / drain lead-out structure and a back-side source / drain lead-out structure; the front-side source / drain lead-out structure is electrically connected to the front-side source / drain metal; the back-side source / drain lead-out structure is electrically connected to the back-side source / drain metal.

3. The method according to claim 2, characterized in that, The step of applying an excitation current between two adjacent front-side source / drain metals and measuring the resulting bottom channel voltage includes: The test node, which is electrically connected to the second and third front source / drain metals, allows the excitation current to flow into the third front source / drain metal and out of the second front source / drain metal. In the first circuit path where the excitation current is generated, the bottom channel voltage is measured through a test node that is electrically connected to the second back source / drain metal and the third back source / drain metal.

4. The method according to claim 2, characterized in that, The step of applying the excitation current between two adjacent back-side source-drain metals and measuring the resulting top-channel voltage includes: The test node, which is electrically connected to the third and second back-side source / drain metals, allows the excitation current to flow into the third back-side source / drain metal and out of the second back-side source / drain metal. In the second circuit path where the excitation current is generated, the top channel voltage is measured through a test node that is electrically connected to the second front source / drain metal and the third front source / drain metal.

5. The method according to claim 2, characterized in that, The step of applying an excitation current between the opposing front and back source / drain metals and measuring the resulting mid-channel voltage includes: The test node is electrically connected to the second front source / drain metal and the second back source / drain metal, so that the excitation current flows in from the second front source / drain metal and flows out from the second back source / drain metal. In the third circuit path where the excitation current is generated, the middle channel voltage is measured through a test node that is electrically connected to the first back-side source-drain metal.

6. The method according to claim 2, characterized in that, A first source / drain interconnect via is provided between the second front source / drain metal and the second back source / drain metal, and a second source / drain interconnect via is provided between the third front source / drain metal and the third back source / drain metal. The method further includes: The first test node is electrically connected to the second front-side source / drain metal through the first source / drain interconnect via; The sixth test node is electrically connected to the third front-side source / drain metal via the second source / drain interconnect via; Through the back-side source / drain lead-out structure, the second test node is electrically connected to the second back-side source / drain metal, the third test node is electrically connected to the first back-side source / drain metal, the fourth test node is electrically connected to the fourth back-side source / drain metal, and the fifth test node is electrically connected to the third back-side source / drain metal.

7. The method according to claim 2, characterized in that, The method further includes: The first test node is electrically connected to the second front-side source / drain metal via a first via and an eighth test node; the first via provides a conductive path between the first test node and the eighth test node, and the eighth test node is electrically connected to the second front-side source / drain metal. The sixth test node is electrically connected to the third front-side source / drain metal via the second via and the ninth test node; the second via is used to provide a conductive path between the sixth test node and the ninth test node, and the ninth test node is electrically connected to the third front-side source / drain metal. Through the back-side source / drain lead-out structure, the second test node is electrically connected to the second back-side source / drain metal, the third test node is electrically connected to the first back-side source / drain metal, the fourth test node is electrically connected to the fourth back-side source / drain metal, and the fifth test node is electrically connected to the third back-side source / drain metal.

8. The method according to claim 1, characterized in that, The determination of the parasitic resistance value of each transistor based on the bottom channel potential value, the middle channel potential value, the top channel potential value, the current value and voltage value of the excitation source includes at least one of the following: The channel resistance value is calculated based on the current value of the excitation source, the bottom channel potential value, the middle channel potential value, and the top channel potential value. Based on the current and voltage values ​​of the excitation source and the potential value of the middle channel, the front epitaxial resistance value and the back epitaxial resistance value are calculated. The front contact resistance value is calculated based on the front epitaxial resistance value, the current and voltage values ​​of the excitation source, and the potential value of the middle channel. The back contact resistance value is calculated based on the back epitaxial resistance value, the middle channel resistance value, and the current value of the excitation source.

9. A method for fabricating a transistor, characterized in that, The transistor is applied to the method for detecting parasitic resistance as described in any one of claims 1 to 8; the method for fabricating the transistor includes: An active structure is formed on the substrate; Based on the aforementioned active structure, a source-drain epitaxial layer is formed; A front-side source / drain metal is formed on the first surface of the source / drain epitaxial layer, and a front-side source / drain lead-out structure is formed on the front-side source / drain metal; Flip the wafer; A back source / drain metal is formed on the second surface of the source / drain epitaxial layer, and a back source / drain lead-out structure is formed on the back source / drain metal.

10. A system for detecting parasitic resistance, characterized in that, The detection system is used to perform the method for detecting parasitic resistance according to any one of claims 1 to 8, the detection system comprising: A first measurement module is used to acquire the bottom channel voltage value of the device under test; the device under test includes at least three transistors arranged side by side in a first direction, wherein each transistor includes a front source / drain metal and a back source / drain metal arranged opposite to each other; the bottom channel voltage value is generated by applying an excitation current between two adjacent front source / drain metals; The second measurement module is used to acquire the top channel voltage value of the device under test; the top channel voltage value is generated by applying the excitation current between two adjacent back-side source-drain metals; The third measurement module is used to acquire the middle channel voltage value of the device under test; the middle channel voltage value is generated by applying an excitation current between the front source / drain metal and the back source / drain metal that are disposed opposite to each other; The calculation module is used to determine the parasitic resistance value of the device under test based on the bottom channel voltage value, the middle channel voltage value, the top channel voltage value, the current value and voltage value of the excitation source; the parasitic resistance value includes at least one of the following: front contact resistance value, back contact resistance value, front epitaxial resistance value, back epitaxial resistance value and channel resistance value.

11. A testing device, characterized in that, include: One or more processors; A storage device for storing one or more programs, which, when executed by one or more processors, cause the one or more processors to perform the method for detecting parasitic resistance as described in any one of claims 1 to 8.

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