Bridging chip and chip packaging structure with same

Abstract

The invention discloses a bridge chip and a chip packaging structure with the same. The bridge chip comprises a substrate; the metal wiring layer is formed on the substrate and comprises a plurality of interconnection wires; the micro convex point group is formed on the substrate, the micro convex point group comprises a first micro convex point array and a second micro convex point array, and the first micro convex point array and the second micro convex point array are respectively used for being connected with two adjacent bare chips; the first micro-convex point array comprises a plurality of first micro-convex points arranged in a set array form, the second micro-convex point array comprises a plurality of second micro-convex points arranged in a set array form, and the set array form is a rectangular array or a staggered array; the first micro-convex points, the second micro-convex points and the interconnection wires are the same in number and are in one-to-one correspondence, each corresponding first micro-convex point and second micro-convex point are electrically connected through one interconnection wire, and the length sizes of the interconnection wires are consistent. According to the invention, high-density and short-distance interconnection between the first micro salient points and the second micro salient points can be realized.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, specifically to a bridging chip and a chip packaging structure having the same. Background Technology

[0002] With the continuous development of semiconductor technology, multi-chip packages (MCPs) and system-in-packages (SiPs) have attracted widespread attention due to their ability to integrate multiple functional chips, improve system performance, and achieve miniaturization. In these package structures, multiple dies (such as processors and memory) need to be interconnected efficiently and reliably to achieve data transmission and signal exchange. Traditional interconnection methods typically employ wire bonding or wiring interconnection via the package substrate. However, existing wiring interconnection schemes suffer from low wiring density, long wiring distances, and increased layer counts. Low wiring density limits the data transmission bandwidth between adjacent dies and requires a large wiring space, hindering the miniaturization of the package structure. Long wiring distances and increased layer counts lead to signal delays, crosstalk, and also increase power consumption and cost. Summary of the Invention

[0003] This application aims to address one of the technical problems in related technologies to a certain extent. To this end, this application provides a bridging chip and a chip package structure having the same.

[0004] To achieve the above objectives, this application adopts the following technical solution: a bridging chip for interconnecting two adjacent dies in a chip package structure, comprising:

[0005] Substrate;

[0006] A metal wiring layer formed on the substrate, the metal wiring layer including a plurality of interconnecting wires;

[0007] A microbump group formed on the substrate, the microbump group including a first microbump array and a second microbump array, the first microbump array and the second microbump array are respectively used for bonding and interconnecting with two adjacent dies in a one-to-one correspondence.

[0008] The first micro-bump array includes a plurality of first micro-bumps arranged in a predetermined array, and the second micro-bump array includes a plurality of second micro-bumps arranged in the predetermined array, wherein the predetermined array is a rectangular array or an interleaved array.

[0009] The number of the first microbump, the second microbump, and the interconnecting wire are the same and correspond one-to-one. Each corresponding first microbump and second microbump are electrically connected by an interconnecting wire, and the interconnecting wire has the same length.

[0010] The application of this application has the following beneficial effects: A first microbump array and a second microbump array are provided for bonding interconnection with two adjacent dies respectively. The corresponding first and second microbumps are then directly connected point-to-point via interconnecting wires. The distribution of the microbumps in the first and second microbump arrays is designed to be a rectangular or staggered array. This achieves high-density, short-distance interconnection between the first and second microbumps, improving space utilization, significantly enhancing signal transmission efficiency and reliability, reducing signal delay, and decreasing power consumption.

[0011] Optionally, the array configuration is a rectangular array, with a first predetermined spacing in the horizontal direction and a second predetermined spacing in the vertical direction between any two corresponding first micro-bumps and second micro-bumps. The interconnecting wire includes a first vertical segment extending vertically and a first bent segment extending outwardly from both ends of the first vertical segment.

[0012] Optionally, the rectangular array has a third predetermined spacing between two adjacent micro-protrusions arranged horizontally and a fourth predetermined spacing between two adjacent micro-protrusions arranged vertically, wherein the first predetermined spacing is equal to the third predetermined spacing.

[0013] Optionally, the array configuration is an interleaved array, which includes multiple columns of micro-bumps arranged horizontally, with adjacent columns of micro-bumps offset vertically from each other, and any two corresponding first micro-bumps and second micro-bumps having a first predetermined interval horizontally and a second predetermined interval vertically.

[0014] Optionally, each of the micro-bump columns includes a plurality of micro-bumps arranged vertically, and the interconnecting wire includes a second vertical segment extending vertically and a second bent segment extending outwardly from both ends of the second vertical segment; or, each of the micro-bump columns includes a plurality of micro-bumps arranged relatively vertically in an inclined direction, and the interconnecting wire extends vertically as a whole.

[0015] Optionally, each of the micro-bump columns includes a plurality of micro-bumps arranged vertically, and two adjacent micro-bump columns have a third predetermined interval in the lateral direction, wherein the first predetermined interval is equal to the third predetermined interval.

[0016] Optionally, two adjacent micro-bump columns are vertically offset from each other by a fourth predetermined interval, and two adjacent micro-bumps in each micro-bump column have a fifth predetermined interval vertically. The fourth predetermined interval is half of the fifth predetermined interval, and the third predetermined interval L is a fraction of the fourth predetermined interval t. times.

[0017] In addition, this application also provides a chip packaging structure, including a first die, a second die, and a bridging chip as described in any of the above technical solutions. The first die has a third microbump array in the area that mates with the bridging chip, and the second die has a fourth microbump array in the area that mates with the bridging chip.

[0018] The third microbump array includes multiple third microbumps arranged in the set array form, and the number of the third microbumps is the same as that of the first microbumps and they are flip-bonded in a one-to-one correspondence.

[0019] The fourth microbump array includes a plurality of fourth microbumps arranged in the set array form, and the number of the fourth microbumps is the same as that of the second microbumps and they are flip-bonded in a one-to-one correspondence.

[0020] The chip packaging structure provided in this application is similar to the reasoning process of the beneficial effects of the aforementioned bridging chip, and will not be repeated here.

[0021] Optionally, the first die is manufactured using a first process technology matching its function, and the second die is manufactured using a second process technology matching its function, wherein the first process technology and the second process technology are different; or, the first die and the second die are manufactured using the same process technology. By integrating dies that support different process technologies, a single large-size chip can be modularly divided into multiple sub-dies according to different functions. The multiple sub-dies can be interconnected using the bridging chip provided in this application to obtain the desired large-size chip. This significantly reduces chip design and manufacturing difficulty, while significantly improving chip yield and reducing manufacturing costs.

[0022] These features and advantages of this application will be disclosed in detail in the following specific embodiments and accompanying drawings. The best embodiments or means of this application will be shown in detail in conjunction with the accompanying drawings, but are not intended to limit the technical solutions of this application. In addition, each of these features, elements and components appearing in the following text and drawings is multiple and is labeled with different symbols or numbers for convenience, but all represent parts with the same or similar structure or function. Attached Figure Description

[0023] The following description, in conjunction with the accompanying drawings, further illustrates this application:

[0024] Figure 1 A schematic diagram of a bridging chip provided in an embodiment of this application;

[0025] Figure 2 This is a schematic diagram showing the interconnection between the two columns of first micro-bumps and the corresponding two columns of second micro-bumps in this embodiment;

[0026] Figure 3This is a schematic diagram of a bridging chip in another implementation.

[0027] Figure 4 This is a schematic diagram showing the interconnection between four columns of first micro-bumps and four corresponding columns of second micro-bumps in another embodiment;

[0028] Figure 5 This is a schematic diagram of a bridging chip in other implementations;

[0029] Figure 6 A schematic diagram of a chip package structure using the bridging chip provided in this embodiment;

[0030] Figure 7 This is a schematic diagram of the first and second dies in a chip package structure.

[0031] Among them, 1 is a bridging chip; 10 is a substrate; 11 is an interconnect wire; 110 is a first vertical segment; 111 is a first bent segment; 112 is a second vertical segment; 113 is a second bent segment; 12 is a first microbump array; 120 is a first microbump; 13 is a second microbump array; 130 is a second microbump; 14 is a microbump array; 2 is a first die; 20 is a third microbump array; 3 is a second die; 30 is a fourth microbump array. Detailed Implementation

[0032] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described are intended to explain this application and should not be construed as limiting it.

[0033] The terms "an embodiment," "example," or "example" used in this specification refer to a particular feature, structure, or characteristic described in connection with the embodiment itself that may be included in at least one embodiment disclosed in this application. The phrase "in an embodiment" appearing in various places throughout the specification does not necessarily refer to the same embodiment.

[0034] In the description of this application, it should be understood that the terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In the description of this application, "a plurality of" means two or more, unless otherwise precisely specified.

[0035] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected," "linked," and "connected" should be interpreted broadly. For example, they can refer to a fixed connection, a connection through an intermediary, or a connection within two elements or an interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0036] This embodiment provides a bridging chip, such as Figure 6 As shown, the bridge chip 1 is used to interconnect two adjacent dies in a chip package structure. Figure 1 As shown, the bridging chip 1 includes a substrate 10, a metal wiring layer formed on the substrate 10, and a microbump array formed on the substrate 10. The metal wiring layer includes multiple interconnect wires 11, and the microbump array includes a first microbump array 12 and a second microbump array 13. The first microbump array 12 and the second microbump array 13 are respectively used for bonding interconnection with two adjacent dies in a one-to-one correspondence.

[0037] In this embodiment, the first microbump array 12 includes a plurality of first microbumps 120 arranged in a predetermined array, and the second microbump array 13 includes a plurality of second microbumps 130 arranged in the aforementioned predetermined array. The predetermined array can be a rectangular array or an interleaved array. The number of first microbumps 120, second microbumps 130, and interconnecting wires 11 are the same and correspond one-to-one. Each corresponding first microbump 120 and second microbump 130 are electrically connected by an interconnecting wire 11, and the interconnecting wires 11 have the same length.

[0038] By setting up a first microbump array 12 and a second microbump array 13 for bonding interconnection with two adjacent dies respectively, and then directly connecting the corresponding first microbumps 120 and second microbumps 130 point-to-point via interconnecting wires 11, and designing the distribution of microbumps in the first microbump array 12 and the second microbump array 13 to be arranged in a rectangular array or an interlaced array, high-density, short-distance interconnection between the first microbump 120 and the second microbump 130 can be achieved. This improves space utilization, significantly enhances signal transmission efficiency and reliability, reduces signal delay, and reduces power consumption.

[0039] like Figure 1 and Figure 2As shown, in this embodiment, the first micro-bump 120 and the second micro-bump 130 are arranged in a rectangular array; that is, the aforementioned array configuration is a rectangular array in this embodiment. Any two corresponding first micro-bumps 120 and second micro-bumps 130 have a first predetermined spacing D in the horizontal direction and a second predetermined spacing H in the vertical direction. The interconnecting wire 11 includes a first vertical segment 110 extending vertically and first bent segments 111 extending outwardly from both ends of the first vertical segment 110. Using the above-described micro-bump arrangement design, high-density, short-distance interconnection between the first micro-bump 120 and the second micro-bump 130 can be achieved.

[0040] Furthermore, such as Figure 2 As shown, in the rectangular array, there is a third predetermined spacing d between two adjacent microbumps arranged horizontally, and a fourth predetermined spacing h between two adjacent microbumps arranged vertically. The first predetermined spacing D is equal to the third predetermined spacing d. Designing the first predetermined spacing D to be equal to the third predetermined spacing d optimizes the routing of the interconnect wires 11 and avoids intersections between adjacent interconnect wires 11. Furthermore, the second predetermined spacing H and the fourth predetermined spacing h can be designed according to the area of ​​the substrate 10 and the values ​​of the first predetermined spacing D and the third predetermined spacing d. It is easy to understand that the value of the first predetermined spacing D directly affects the distribution density of the interconnect wires 11 in the horizontal direction, and the distribution density of the interconnect wires 11 in the horizontal direction directly affects the number of the first microbumps 120 and the second microbumps 130 distributed vertically and the corresponding value of the fourth predetermined spacing h. Preferably, the value of the second predetermined spacing H can be determined according to the area of ​​the substrate 10, and the value of the fourth predetermined spacing h is less than or equal to the value of the first predetermined spacing D or the third predetermined spacing d.

[0041] Meanwhile, designing the fourth predetermined spacing h to be smaller than the first predetermined spacing D can increase the vertical distribution density of the micro-protrusions. It is easy to understand that the phrase "a third predetermined spacing d between two adjacent micro-protrusions arranged horizontally in the rectangular array" in this embodiment refers to both the third predetermined spacing d between two adjacent first micro-protrusions 120 arranged horizontally and the third predetermined spacing d between two adjacent second micro-protrusions 130 arranged horizontally. Similarly, the phrase "a fourth predetermined spacing h between two adjacent micro-protrusions arranged vertically" in this embodiment also refers to the fourth predetermined spacing h between two adjacent first micro-protrusions 120 arranged vertically and between two adjacent second micro-protrusions 130 arranged vertically.

[0042] The microbump arrangement scheme in the bridging chip 1 provided in this embodiment enables high-density, short-distance interconnection between adjacent dies. Specifically, the center-to-center distance between two adjacent interconnecting wires 11 is 1 μm. In other optional embodiments, the center-to-center distance between two adjacent interconnecting wires 11 is no greater than 2 μm.

[0043] In this embodiment, the size of the bridging chip 1 is set according to the arrangement requirements of the microbump group. For example, the arrangement range of the microbump group on the bridging chip 1 is equal to a specified value, which is 2mm*5mm (2mm horizontally and 5mm vertically). It should be noted that the horizontal length of the bridging chip 1 shown in the attached drawings is greater than the vertical length only for illustrative purposes and does not represent the actual size of the bridging chip 1. Furthermore, considering the blank area at the edge and the required spacing between the first and second microbump arrays, the horizontal dimension of the bridging chip 1 should be no less than 2mm, and considering the packaging gap between the dies, the vertical dimension should be no less than 5mm. The actual size of the bridging chip 1 is based on the packaging process. Figure 2 Taking the matrix arrangement of the first micro-bump array 12 and the second micro-bump array 13 as an example: If the first preset spacing D is designed to be 50 μm, then the first micro-bump array 12 and the second micro-bump array 13 can each have 40 first micro-bumps 120 and 40 second micro-bumps 130 arranged laterally (correspondingly forming 39 intervals). If the center spacing between the two interconnecting wires 11 is designed to be 1 μm, then 50 interconnecting wires 11 can be arranged laterally between any two corresponding first micro-bumps 120 and second micro-bumps 130. Accordingly, the first micro-bump array 12 and the second micro-bump array 13 can each have 50 first micro-bumps 120 and 50 second micro-bumps 130 arranged vertically. Thus, the first micro-bump array 12 has 2000 first micro-bumps 120, and the second micro-bump array 13 has 2000 second micro-bumps 130. If the lateral dimension in the specified value is increased to 8mm, the first micro-bump array 12 has 8000 first micro-bumps 120 and the second micro-bump array 13 has 8000 second micro-bumps 130, and the arrangement density of the micro-bumps is significantly improved.

[0044] Figure 3 and Figure 5 Two other implementations of the configuration array are shown, in which the configuration array in the bridge chip 1 is an interleaved array. The interleaved array includes a plurality of microbump columns 14 arranged laterally, and adjacent microbump columns 14 are offset from each other vertically. Any two corresponding first microbumps 120 and second microbumps 130 are separated by a first predetermined interval M in the lateral direction and a second predetermined interval N in the vertical direction.

[0045] Furthermore, with Figure 3Taking the illustrated array configuration as an example, each micro-bump column 14 includes multiple micro-bumps arranged vertically; that is, the multiple micro-bumps (first micro-bump 120 or second micro-bump 130) in each micro-bump column 14 are arranged sequentially along the vertical direction. The interconnecting wire 11 includes a second vertical segment 112 extending vertically and a second bent segment 113 extending outwardly from both ends of the second vertical segment 112. Using the above-described micro-bump arrangement design, high-density, short-distance interconnection between the first micro-bump 120 and the second micro-bump 130 can also be achieved.

[0046] Or, with Figure 5 Taking the illustrated array configuration as an example, each micro-bump column 14 includes multiple micro-bumps arranged vertically along an inclined direction. That is, the multiple micro-bumps (first micro-bump 120 or second micro-bump 130) in each micro-bump column 14 are arranged sequentially along the inclined direction. The interconnecting wire 11 extends vertically as a whole. Using the above-described micro-bump arrangement design, high-density, short-distance interconnection between the first micro-bump 120 and the second micro-bump 130 can also be achieved. Furthermore, this scheme allows the interconnecting wire 11 to be straight, reducing the length of the interconnecting guide 11 while avoiding bending, thereby improving signal quality. It also improves area utilization and reduces wasted area at the left and right ends.

[0047] Combination Figure 4 As shown, for Figure 3 The bridge chip 1 shown includes a plurality of vertically arranged microbumps in each microbump column 14. Adjacent microbump columns 14 have a third predetermined interval L in the lateral direction. The first predetermined interval M is equal to the third predetermined interval L. Designing the first predetermined interval M to be equal to the third predetermined interval L can optimize the routing of the interconnect wires 11 and avoid crossing between adjacent interconnect wires 11.

[0048] Furthermore, in this embodiment, adjacent micro-bump arrays 14 are vertically offset from each other by a fourth predetermined interval t, and adjacent micro-bumps in each micro-bump array 14 are vertically separated by a fifth predetermined interval T. The fourth predetermined interval t is half of the fifth predetermined interval T, and the third predetermined interval L is half of the fourth predetermined interval t. The size of the package can be increased several times. Taking the first microbump group 120 as an example, after adopting the above microbump arrangement scheme, any two vertically arranged and adjacent first microbumps 120 in the first microbump group 120 and a horizontally adjacent microbump can form an equilateral triangle. This can further optimize the layout of the microbumps, making the arrangement of the microbumps more compact and further reducing the overall package size.

[0049] like Figure 6 and Figure 7As shown, the bridging chip 1 provided in this embodiment can be applied to a chip packaging structure, which includes a first die 2, a second die 3, and the bridging chip 1 provided in this embodiment. The first die 2 has a third microbump array 20 in the area that mates with the bridging chip 1. The third microbump array 20 includes multiple third microbumps arranged in a predetermined array. The number of third microbumps is the same as the number of first microbumps 120, and they are flip-chip bonded in a one-to-one correspondence. The second die 3 has a fourth microbump array 30 in the area that mates with the bridging chip 1. The fourth microbump array 30 includes multiple fourth microbumps arranged in a predetermined array. The number of fourth microbumps is the same as the number of second microbumps 130, and they are flip-chip bonded in a one-to-one correspondence. The bridging chip 1 provided in this embodiment interconnects two adjacent dies to form a compact chip packaging structure.

[0050] Furthermore, by dividing the large chip functionality into multiple sub-dies, the design and manufacturing complexity of each sub-die is reduced, thereby lowering the risk and cost of a single tape-out and improving the overall yield. To this end, in this embodiment, the first die 2 is manufactured using a first process technology matching its function, and correspondingly, the second die 3 is manufactured using a second process technology matching its function. The first and second process technologies are different. By integrating dies that support different process technologies, a single large-size chip can be modularly divided into multiple sub-dies according to different functions. The bridge chip 1 provided in this application is used to interconnect these multiple sub-dies to obtain the desired large-size chip. This significantly reduces chip design and manufacturing difficulty, while significantly improving chip yield and reducing manufacturing costs. For example, the various functional units (such as arithmetic logic units, memory units, acceleration units, etc.) of a large target chip can be fabricated into several sub-dies according to performance requirements and physical coupling, and then these sub-dies can be arranged adjacently and interconnected using the bridge chip 1 provided in this embodiment.

[0051] It is easy to understand that, in other alternative embodiments, the first die 2 and the second die 3 can also be manufactured using the same process.

[0052] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Those skilled in the art should understand that this application includes, but is not limited to, the contents described in the accompanying drawings and the specific embodiments above. Any modifications that do not depart from the functional and structural principles of this application will be included within the scope of the claims.

Claims

1. A bridging chip for interconnecting two adjacent dies in a chip package structure, characterized in that, include: Substrate; A metal wiring layer formed on the substrate, the metal wiring layer including a plurality of interconnecting wires; A microbump group formed on the substrate, the microbump group including a first microbump array and a second microbump array, the first microbump array and the second microbump array are respectively used for bonding and interconnecting with two adjacent dies in a one-to-one correspondence. The first micro-bump array includes a plurality of first micro-bumps arranged in a predetermined array, and the second micro-bump array includes a plurality of second micro-bumps arranged in the predetermined array, wherein the predetermined array is a rectangular array or an interleaved array. The number of the first microbump, the second microbump, and the interconnecting wire are the same and correspond one-to-one. Each corresponding first microbump and second microbump are electrically connected by an interconnecting wire, and the interconnecting wire has the same length.

2. The bridging chip as described in claim 1, characterized in that, The array is a rectangular array, with a first predetermined spacing in the horizontal direction and a second predetermined spacing in the vertical direction between any two corresponding first micro-bumps and second micro-bumps. The interconnecting wire includes a first vertical segment extending vertically and a first bent segment extending outwardly from both ends of the first vertical segment.

3. The bridging chip as described in claim 2, characterized in that, The rectangular array has a third predetermined spacing between two adjacent micro-protrusions arranged horizontally and a fourth predetermined spacing between two adjacent micro-protrusions arranged vertically, wherein the first predetermined spacing is equal to the third predetermined spacing.

4. The bridging chip as described in claim 1, characterized in that, The set array is an interlaced array, which includes multiple columns of micro-bumps arranged horizontally, and adjacent columns of micro-bumps are offset from each other vertically. Any two corresponding first micro-bumps and second micro-bumps have a first set interval in the horizontal direction and a second set interval in the vertical direction.

5. The bridging chip as described in claim 4, characterized in that, Each of the micro-bump columns includes a plurality of micro-bumps arranged vertically, and the interconnecting wire includes a second vertical segment extending vertically and a second bent segment extending outwardly from both ends of the second vertical segment; Alternatively, each of the micro-bump columns includes multiple micro-bumps arranged relatively vertically along an inclined direction, and the interconnecting wires extend vertically as a whole.

6. The bridging chip as described in claim 5, characterized in that, Each of the micro-bump columns includes multiple micro-bumps arranged vertically, and adjacent micro-bump columns have a third predetermined interval in the horizontal direction, wherein the first predetermined interval is equal to the third predetermined interval.

7. The bridging chip as described in claim 6, characterized in that, Two adjacent micro-bump columns are offset from each other vertically by a fourth predetermined interval. Each adjacent micro-bump column has a fifth predetermined interval vertically between two adjacent micro-bumps. The fourth predetermined interval is half of the fifth predetermined interval, and the third predetermined interval L is a fraction of the fourth predetermined interval t. times.

8. A chip packaging structure, characterized in that, The device includes a first die, a second die, and a bridging chip as described in any one of claims 1 to 7, wherein the first die has a third microbump array in the area that mates with the bridging chip, and the second die has a fourth microbump array in the area that mates with the bridging chip. The third microbump array includes multiple third microbumps arranged in the set array form, and the number of the third microbumps is the same as that of the first microbumps and they are flip-bonded in a one-to-one correspondence. The fourth microbump array includes a plurality of fourth microbumps arranged in the set array form, and the number of the fourth microbumps is the same as that of the second microbumps and they are flip-bonded in a one-to-one correspondence.

9. The chip packaging structure as described in claim 8, characterized in that, The first die is manufactured based on a first process technology that matches its function, and the second die is manufactured based on a second process technology that matches its function, wherein the first process technology and the second process technology are different; Alternatively, the first and second dies may be manufactured using the same process.

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