Chip wafer level test anomaly detection method based on multi-dimensional parameter correlation analysis

Abstract

The invention relates to the technical field of wafer-level test anomaly detection, and discloses a chip wafer-level test anomaly detection method based on multi-dimensional parameter correlation analysis, which comprises the following steps: acquiring and preprocessing wafer test core parameters and equipment operation parameters, constructing a dynamic parameter correlation reference model, and establishing a dynamic parameter correlation reference model; the fusion correlation deviation degree of real-time parameters and a normal correlation coefficient matrix is calculated, a scene exclusive dynamic threshold value is set, explicit and implicit anomaly judgment is completed in combination with a single parameter specification, and anomaly source tracing is achieved through a dynamic correlation list, feature screening and time sequence-space two-dimensional detection. The hybrid algorithm is adopted to calculate the correlation deviation degree, linear and nonlinear methods are fused to screen features, the defect that only dominant anomalies can be recognized in the prior art is broken through, collaborative accurate detection of hidden anomalies and dominant anomalies in specifications is achieved, meanwhile, the anomaly root can be traced, dynamic changes of the wafer manufacturing process are adapted, and the detection accuracy is improved. And the comprehensiveness and accuracy of anomaly detection are improved.

Description

Technical Field

[0001] This invention relates to the field of wafer-level test anomaly detection technology, specifically a chip wafer-level test anomaly detection method based on multidimensional parameter correlation analysis. Background Technology

[0002] In integrated circuit manufacturing, wafer-level testing is a crucial step in ensuring chip quality and reliability. By applying electrical signals to each chip cell on the wafer and collecting response parameters, it achieves preliminary verification of the chip's electrical performance. This allows for early screening of faulty cells, preventing them from entering subsequent packaging processes, thereby reducing manufacturing costs and improving product yield. As chip manufacturing processes advance to 3nm and below, chip structures become increasingly complex. The number of electrical parameters and equipment operating parameters that need to be collected during wafer testing is constantly increasing, and the correlations between these parameters exhibit both linear and nonlinear characteristics, placing higher demands on the accuracy and comprehensiveness of anomaly detection.

[0003] Currently, various technical solutions have emerged in the field of wafer-level test anomaly detection. Existing technologies mainly determine anomalies by setting fixed threshold values ​​for individual test parameters or by using multi-parameter fusion. For example, invention patent CN117688499A discloses a multi-index anomaly detection method, device, electronic device, and storage medium. It determines threshold values ​​through multi-index reconstruction sequences to detect multi-index anomalies. However, this method does not focus on the wafer testing scenario and does not distinguish between parameter out-of-specification anomalies and in-specification collaborative anomalies. Invention patent CN119164969A discloses a wafer quality inspection method in an ultra-clean environment. It mainly detects physical defects on the wafer surface and inside through laser scanning, infrared thermography, and ultrasonic testing, without involving correlation analysis between wafer test parameters. Other existing technologies use fixed correlation lists to group and correlate test parameters or only use a single algorithm to capture linear correlations between parameters. These technologies cannot adapt to changes in parameter correlations caused by dynamic process changes and are difficult to accurately identify latent anomalies. In general, existing anomaly detection methods all use whether parameters exceed preset specifications as the core criterion for judgment, focusing on identifying obvious anomalies where a single parameter exceeds the specification.

[0004] However, in actual wafer testing, numerous latent anomalies exist where individual parameters are within preset specifications, but the synergistic relationships between multiple parameters deviate from normal patterns. These latent anomalies cannot be identified by existing detection methods, leading to missed detections. This allows potentially defective chips to enter subsequent processes, ultimately increasing the probability of chip failure and impacting product quality and market competitiveness. Therefore, there is an urgent need for a wafer-level testing anomaly detection method capable of accurately identifying these latent anomalies with synergistic relationships between multiple parameters within specifications, thus solving the aforementioned problems. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a chip wafer-level test anomaly detection method based on multidimensional parameter correlation analysis. This method aims to solve the problem that existing wafer-level test anomaly detection methods rely on whether parameters exceed preset specifications as the core judgment criterion. They can only identify explicit anomalies where a single parameter exceeds the specification, but cannot identify implicit anomalies where a single parameter is within the preset specification range but the synergistic correlation of multiple parameters deviates from the normal pattern. This leads to the problem of missed anomaly detection and an increased probability of chip product failure.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: a chip wafer-level test anomaly detection method based on multidimensional parameter correlation analysis, comprising the following steps: Step 1, collecting core parameters and related data of wafer testing, and preprocessing the collected data; Step 2: Construct a dynamic parameter association benchmark model based on the preprocessed historical normal data. The dynamic parameter association benchmark model has the ability to be updated in real time. Step 3: Calculate the correlation deviation between the real-time test parameters and the normal correlation coefficient matrix output by the dynamic parameter correlation benchmark model; Step 4: Set scenario-specific dynamic thresholds based on wafer manufacturing process and chip model; Step 5: Based on the comparison results between the correlation deviation and the dynamic threshold, and combined with the individual parameter specifications, determine the anomaly and output the result; Step six involves simultaneously generating a dynamic correlation list, performing feature filtering on high-dimensional test parameters, and integrating temporal and spatial parameters for dual-dimensional correlation detection to achieve root cause tracing of anomalies.

[0007] Furthermore, the calculation of the correlation deviation between the real-time test parameters and the normal correlation coefficient matrix output by the dynamic parameter correlation benchmark model employs a hybrid algorithm that fuses cosine similarity and Euclidean distance. The specific calculation process includes: first, using the Pearson correlation coefficient method to calculate the correlation coefficients between the parameters after real-time preprocessing, obtaining the real-time correlation coefficient matrix; then, calculating the cosine similarity and Euclidean distance between the real-time correlation coefficient matrix and the normal correlation coefficient matrix; finally, calculating the fused correlation deviation using the fusion formula, which is: ,in The correlation deviation is a core indicator used to determine anomalies in the collaborative correlation of multiple parameters within a specification. Cosine similarity is used to characterize the directional consistency between the real-time correlation coefficient matrix and the normal correlation coefficient matrix. =Euclidean distance, used to characterize the degree of numerical difference between the real-time correlation coefficient matrix and the normal correlation coefficient matrix; 0.6 and 0.4 are the weight coefficients of cosine similarity and Euclidean distance, respectively, used to balance the influence of the two on the deviation of the fused correlation.

[0008] Furthermore, the generation of the dynamic correlation list specifically includes: without manually pre-setting association rules, combining real-time wafer test data and historical process data, updating parameter clustering rules in real time through an adaptive clustering algorithm; automatically identifying the correlation between new test parameters and existing test parameters, deleting invalid parameter association rules, and supplementing new parameter association relationships; the dynamic correlation list is updated synchronously with the dynamic parameter association benchmark model to ensure that the parameter clustering rules are consistent with the parameter association rules and adapt to the dynamic changes in wafer manufacturing processes.

[0009] Furthermore, feature screening is performed on the high-dimensional test parameters using a hybrid linear-nonlinear correlation feature screening model. Specifically, this includes: initially screening and refining the high-dimensional test parameters by fusing Pearson correlation coefficients and kernel functions; capturing the linear correlation between test parameters using Pearson correlation coefficients to eliminate redundant linear parameters irrelevant to anomaly detection; capturing the nonlinear correlation between test parameters using kernel functions to retain nonlinear correlation parameters that influence anomaly detection; and outputting key test parameters after screening as input parameters for the dynamic parameter correlation benchmark model, providing a reliable parameter basis for correlation deviation calculation and anomaly determination.

[0010] Furthermore, the integrated timing and spatial parameter dual-dimensional correlation detection specifically includes: collecting timing parameters from multiple tests on the same chip and spatial parameters from adjacent chips; processing the timing parameters using timing analysis algorithms to capture parameter drift trends; processing the spatial parameters using spatial neighborhood calculation methods to capture local parameter anomalies; constructing a timing-space dual-dimensional correlation model to perform correlation analysis between the parameter drift trends captured by the timing parameters and the local anomalies captured by the spatial parameters, thereby achieving collaborative detection of instantaneous spatial anomalies and temporally gradual anomalies, ensuring the comprehensiveness of anomaly detection.

[0011] Furthermore, the specific dynamic threshold setting for the scenario includes: calculating the correlation deviation result based on preprocessed historical normal data, and taking a specified quantile as the initial threshold value; after completing a preset number of real-time tests on wafers, calculating the average correlation deviation of the normal wafers in that batch; if the average correlation deviation of the batch fluctuates more than a preset range compared to the previous batch, then the current threshold is fine-tuned; at the same time, a threshold range limit is set to ensure that the threshold is always within a reasonable range, adapting to the testing requirements of different manufacturing processes and different chip models, and avoiding misjudgments and missed detections caused by unreasonable thresholds.

[0012] Furthermore, the specific implementation of anomaly root cause tracing includes: while performing feature screening and anomaly determination on high-dimensional test parameters, establishing a mapping relationship between parameter-related anomalies and wafer manufacturing processes and test equipment status; tracing back the specific root cause of the anomaly through the correlation features of the anomaly parameters; the anomaly root cause includes wafer manufacturing process deviations and test equipment operation anomalies, wherein wafer manufacturing process deviations include lithography process deviations, and test equipment operation anomalies include probe contact failures; after tracing is completed, the anomaly root cause information and anomaly determination results are output synchronously to provide a basis for process optimization and equipment maintenance.

[0013] Furthermore, the acquisition of core wafer testing parameters and related data also includes the acquisition of test equipment operating parameters. Specifically, the core wafer testing parameters acquired are the essential electrical parameters for wafer testing, and the test equipment operating parameters acquired include probe contact force, temperature control platform temperature, and test voltage stability. The core wafer testing parameters and test equipment operating parameters are integrated to construct a chip-equipment parameter correlation model. This model is used to analyze parameter correlations, distinguish between chip defects and anomalies caused by equipment interference, and ensure the accuracy of anomaly determination.

[0014] Furthermore, in the process of calculating the correlation deviation and constructing the dynamic parameter correlation benchmark model, a lightweight CART correlation analysis algorithm is adopted, which specifically includes: retaining key correlation parameters and eliminating irrelevant parameters through an adaptive parameter dimension pruning method; optimizing the decision tree node splitting rules to simplify the algorithm calculation steps; reducing the algorithm's computational complexity and improving its computational efficiency without changing the detection logic and judgment criteria, adapting to the needs of rapid testing of mass-produced wafers, and ensuring the timeliness of real-time detection.

[0015] Furthermore, in the process of constructing the dynamic parameter correlation benchmark model and calculating the correlation deviation, a dynamic parameter weight allocation mechanism is adopted, which specifically includes: constructing a parameter weight allocation model based on the degree of influence of each test parameter on chip performance and the abnormal contribution rate of each parameter in historical abnormal data; automatically allocating the weight of each test parameter in the correlation analysis through this model, with key parameters that have a greater impact on chip performance and a higher abnormal contribution rate being assigned higher weights; and dynamically adjusting the parameter weights in sync with the updates of historical abnormal data to ensure the pertinence and accuracy of correlation analysis and anomaly judgment.

[0016] Compared with existing technologies, this chip wafer-level test anomaly detection method based on multidimensional parameter correlation analysis has the following advantages: I. This invention constructs a dynamic parameter correlation benchmark model with real-time update capability by performing correlation analysis on multi-dimensional parameters of wafer testing. It uses a hybrid algorithm that integrates cosine similarity and Euclidean distance to calculate the correlation deviation. Combined with scene-specific dynamic thresholds and individual parameter specifications, it conducts anomaly judgment, breaking through the limitation of existing technologies that only use parameter out-of-specification as the judgment basis. It can accurately identify hidden anomalies where a single parameter is within the specification range but multiple parameters deviate from the normal pattern in a coordinated correlation. At the same time, it can effectively detect explicit anomalies, solve the problem of anomaly missed detection in existing methods, reduce the number of chips with potential defects entering subsequent processes, reduce the failure probability of finished chip products, and improve the quality and market competitiveness of chip products.

[0017] Second, this invention achieves adaptive updates of parameter association rules by generating a dynamic correlation list, uses a linear-nonlinear hybrid correlation feature screening model to accurately screen high-dimensional parameters, integrates temporal and spatial parameters to achieve dual-dimensional correlation detection, and can establish a mapping relationship between parameter correlation anomalies and manufacturing processes and equipment status to trace the root cause of anomalies. At the same time, it combines a lightweight CART algorithm and a dynamic parameter weight allocation mechanism to improve detection efficiency, distinguishes between anomalies caused by chip defects and equipment interference, adapts to the dynamic changes in wafer manufacturing processes, provides specific basis for wafer manufacturing process optimization and test equipment maintenance, and meets the real-time requirements of rapid testing of mass-produced wafers.

[0018] Other advantages, objectives and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination or study, or may be learned from the practice of the invention. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0020] Figure 1 This is a flowchart of the method of the present invention; Figure 2 This is the logical diagram for tracing the root cause of an anomaly in this invention, using a two-dimensional approach. Detailed Implementation

[0021] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the following detailed description of the specific implementation methods, structures, features, and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided below.

[0022] like Figure 1 and Figure 2 As shown, a chip wafer-level testing anomaly detection method based on multi-dimensional parameter correlation analysis can accurately detect explicit anomalies and implicit anomalies resulting from the synergistic correlation of multiple parameters within specifications during wafer testing, while simultaneously tracing the root cause of the anomalies. The method includes the following steps: Step 1: Collect core parameters and related data for wafer testing and perform data preprocessing. Specifically, the data acquisition module of the wafer testing machine completes the real-time acquisition of core wafer testing parameters and test equipment operating parameters. The acquisition frequency matches the wafer testing cycle to ensure the real-time and synchronous acquisition of parameters. Among them, the core wafer testing parameters are the essential electrical parameters for wafer testing, including basic parameters for wafer-level electrical performance testing such as chip leakage current, threshold voltage, and on-resistance. The test equipment operating parameters include probe contact force, temperature control platform temperature, and test voltage stability. Integrating the core wafer testing parameters and test equipment operating parameters provides a data foundation for the subsequent construction of a chip-equipment parameter correlation model.

[0023] The collected mixed dataset underwent standardized preprocessing, which included three sub-steps: data cleaning, data normalization, and data completion. Data cleaning removed invalid and outlier values ​​caused by equipment communication failures and signal interference during the acquisition process. Data normalization employed a maximum-minimum standardization method to map parameters of different dimensions and orders of magnitude to the same numerical range, eliminating the impact of dimensional differences on subsequent association analysis. Data completion used neighborhood interpolation to fill in any missing parameter values, ensuring the integrity of the dataset. The preprocessed standardized dataset provides a high-quality data foundation for subsequent model construction and association analysis, effectively avoiding interference from noise in the original data.

[0024] Step 2: Construct a dynamic parameter correlation benchmark model based on preprocessed historical normal data. The dynamic parameter association benchmark model constructed in this step has real-time update capability. The model construction process integrates the lightweight CART association analysis algorithm and the dynamic parameter weight allocation mechanism, and at the same time completes the basic training of the model and the construction of dynamic update capability. The specific implementation method is as follows.

[0025] During the basic training phase of the model, a lightweight CART correlation analysis algorithm is used to perform correlation analysis on the preprocessed historical normal dataset. An adaptive parameter pruning method is employed to filter parameters in the historical normal data, retaining key correlation parameters strongly related to chip performance and removing irrelevant redundant parameters. The node splitting rules of the CART decision tree are optimized, using the correlation between parameters as the core basis for node splitting. This simplifies the algorithm's computational steps, reducing computational complexity and improving computational efficiency without changing the detection logic and judgment criteria, thus adapting to the real-time requirements of rapid testing of mass-produced wafers.

[0026] A dynamic parameter weight allocation mechanism is embedded in the model construction process. Based on the impact of each test parameter on chip performance and the anomaly contribution rate of each parameter in historical anomaly data, a parameter weight allocation model is constructed. This model automatically assigns weights to each test parameter in the correlation analysis, allocating higher weights to key parameters that have a greater impact on chip performance and a higher anomaly contribution rate, making the correlation analysis results more closely reflect the actual performance characteristics of the chip. The parameter weights are dynamically adjusted synchronously with the continuous updates of historical anomaly data, ensuring the relevance and accuracy of the correlation analysis.

[0027] After completing the basic training of the model, a real-time update mechanism for the model is established. After each preset batch of wafer testing is completed, the wafer test data in that batch that is determined to be normal is preprocessed and integrated into the historical normal dataset. The dynamic parameter correlation benchmark model is then iteratively trained and updated to enable the model to adapt to the dynamic changes in wafer manufacturing processes. This ensures the timeliness and accuracy of the normal correlation coefficient matrix output by the model and avoids the problem of model failure due to process adjustments.

[0028] Step 3: Calculate the correlation deviation between the real-time test parameters and the normal correlation coefficient matrix. This step uses a hybrid algorithm that combines cosine similarity and Euclidean distance to calculate the association deviation. The calculation process is based on the lightweight CART association analysis algorithm to ensure computational efficiency. It is divided into three sub-steps, and the calculation process and parameter definitions of each sub-step are as follows.

[0029] Calculate the real-time correlation coefficient matrix The correlation coefficient between parameters after real-time preprocessing was calculated using the Pearson correlation coefficient method. The formula for calculating the Pearson correlation coefficient is as follows:

[0030] In the formula, Let be the Pearson correlation coefficient between the i-th parameter and the j-th parameter. For the k-th sampled value of the i-th parameter, For the k-th sample value of the j-th parameter, Let be the mean of the sampled values ​​of the i-th parameter. Let be the mean of the sampled values ​​of the j-th parameter, and n be the number of parameters sampled. This formula is used to calculate the pairwise correlation coefficients between all parameters after real-time preprocessing, forming a real-time correlation coefficient matrix. The normal correlation coefficient matrix output by the dynamic parameter correlation benchmark model is: .

[0031] The cosine similarity and Euclidean distance are calculated to determine the cosine similarity between the real-time correlation coefficient matrix and the normal correlation coefficient matrix. The formula is as follows:

[0032] In the formula Cosine similarity, representing the directional consistency of two matrices, takes values ​​in the range of [...]. The closer the value is to 1, the stronger the directional consistency between the two matrices.

[0033] The Euclidean distance between the real-time correlation coefficient matrix and the normal correlation coefficient matrix is ​​calculated using the following formula:

[0034] In the formula, The Euclidean distance characterizes the degree of numerical difference between two matrices. The dimension of the correlation coefficient matrix. The element in the i-th row and j-th column of the real-time correlation coefficient matrix. The element in the i-th row and j-th column of the normal correlation coefficient matrix is ​​D. The larger the value of D, the more obvious the numerical difference between the two matrices.

[0035] The fusion correlation deviation is calculated by weighting the cosine similarity and Euclidean distance using a fusion formula, which is as follows:

[0036] In the formula, The correlation deviation is the core indicator for judging the anomaly of multi-parameter collaborative correlation within the specification. 0.6 and 0.4 are the weighting coefficients of cosine similarity and Euclidean distance. These weighting coefficients are determined based on statistical analysis of a large amount of historical wafer testing data. They can take into account the contribution of directional consistency and numerical difference to the correlation deviation, and achieve effective integration of the two indicators.

[0037] Step 4: Set scenario-specific dynamic thresholds based on wafer manufacturing process and chip model. Setting a scenario-specific dynamic threshold involves three sub-steps: determining the initial threshold value, dynamic adjustment, and range limitation. This allows the threshold to adapt to the testing requirements of different manufacturing processes and chip models. The specific implementation method is as follows.

[0038] Based on the correlation deviation result calculated from the preprocessed historical normal data, a specified quantile is taken as the initial value of the threshold. This specified quantile is determined according to the stability of the wafer manufacturing process and the characteristics of the chip model. Wafer manufacturing processes with higher process stability select a higher quantile as the initial value of the threshold to reduce the probability of abnormal misjudgment.

[0039] A dynamic threshold adjustment mechanism is established. After a preset number of wafers are tested in real time, the average correlation deviation of the normal wafers in that batch is calculated. If the average correlation deviation of the batch fluctuates more than the preset range compared with the previous batch, the current threshold is fine-tuned. The fine-tuning range is adapted according to the fluctuation size. The larger the fluctuation, the larger the fine-tuning range is, ensuring the matching of the threshold with the actual test data.

[0040] Setting reasonable upper and lower limits for the threshold forms a threshold range restriction, ensuring that the threshold always stays within this range. This avoids excessive threshold adjustment due to slight fluctuations in the process or data deviations, effectively preventing misjudgments and missed detections caused by unreasonable thresholds, and enabling the threshold to adapt to the testing requirements of different manufacturing processes and different chip models.

[0041] Step 5: Combine the correlation deviation with the individual parameter specification to determine anomalies and output the results. This step achieves the collaborative determination of explicit and implicit anomalies. Specifically, the fusion correlation deviation calculated in step three is compared with the scene-specific dynamic threshold set in step four. If the fusion correlation deviation exceeds the dynamic threshold, it indicates that the collaborative correlation between multiple parameters deviates from the normal pattern, and it is determined that there is an implicit anomaly within the specification. At the same time, the specification of a single test parameter is determined by comparing each real-time test parameter with the preset specification threshold of that parameter. If the parameter value exceeds its specification threshold, it is determined that there is an explicit anomaly.

[0042] This method unifies the labeling of both latent and explicit anomalies, and organizes and standardizes the output of information such as anomaly type, corresponding parameter information, correlation deviation value, and the magnitude of parameter out-of-specification, providing basic information for subsequent anomaly handling and root cause tracing. This judgment method considers both explicit and latent anomalies, overcoming the technical limitation of existing technologies that can only identify explicit anomalies, and improving the comprehensiveness of anomaly detection.

[0043] Step 6 generates a dynamic relevance list and completes feature selection, two-dimensional detection, and anomaly tracing. This step involves the coordinated execution of multiple sub-steps, simultaneously completing the generation of a dynamic correlation list, the screening of high-dimensional parameter features, the detection of temporal-spatial dual-dimensional correlations, and the tracing of the root causes of anomalies. The sub-steps cooperate with each other to form a complete anomaly analysis and tracing system. The specific implementation method is as follows.

[0044] Generate a dynamic correlation list Without requiring manual pre-setting of association rules, the system combines real-time wafer test data and historical process data, using an adaptive clustering algorithm to update parameter clustering rules in real time. It automatically identifies the correlation between new test parameters and existing test parameters. For test parameters added after wafer manufacturing process adjustments, the adaptive clustering algorithm assigns them to their corresponding parameter groups and establishes associations with existing parameters within those groups. Simultaneously, it automatically deletes invalid parameter association rules and adds new parameter associations, ensuring the effectiveness of the parameter association rules. The dynamic correlation list is updated synchronously with the dynamic parameter association benchmark model, ensuring that the parameter clustering rules and parameter association patterns remain consistent, enabling the correlation list to adapt to dynamic changes in wafer manufacturing processes.

[0045] Feature filtering of high-dimensional test parameters A linear-nonlinear hybrid correlation feature screening model is adopted, which integrates Pearson correlation coefficient and kernel function to perform initial screening and refinement of high-dimensional test parameters. Specifically, the Pearson correlation coefficient is used to capture the linear correlation between test parameters, calculate the linear correlation between each parameter and the anomaly detection results, and eliminate linear redundant parameters irrelevant to anomaly detection, thus completing the initial parameter screening. The kernel function is used to capture the nonlinear correlation between test parameters, employing the Gaussian kernel function as the implementation method. The calculation formula for the Gaussian kernel function is as follows:

[0046] In the formula Let be the kernel function value of the i-th parameter and the j-th parameter, representing the degree of nonlinear correlation between them. This is the bandwidth parameter of the kernel function, used to adjust the capture range of nonlinear correlations. The kernel function calculates the nonlinear correlation between each parameter and the anomaly detection results, retaining the nonlinear correlation parameters that affect anomaly detection, thus completing parameter selection.

[0047] After screening, key test parameters are output and used as input parameters for the dynamic parameter association benchmark model. This provides a reliable parameter basis for association deviation calculation and anomaly detection, effectively reducing the computational complexity caused by high-dimensional parameters and improving the efficiency of association analysis.

[0048] Integrating temporal and spatial parameters for two-dimensional correlation detection Timing parameters from multiple tests of the same chip and spatial parameters from adjacent chips are collected. Timing parameters are the same type of parameters collected from different testing stages of the same chip during wafer testing, while spatial parameters are the same type of test parameters from adjacent chips within the same location area on the wafer. Timing parameters are processed using timing analysis algorithms, employing a sliding window method to capture parameter drift trends. By setting a fixed-length sliding window, the timing parameters within the window are fitted to determine if there are slow, gradual drift characteristics. Spatial parameters are processed using a spatial neighborhood calculation method, employing a neighborhood mean deviation method to capture local parameter anomalies. The mean of the same type of parameters from adjacent chips is calculated, and the parameter values ​​of a single chip are compared with the neighborhood mean to determine if there are local parameter anomalies.

[0049] A temporal-spatial dual-dimensional correlation model is constructed to correlate the parameter drift trend captured by temporal parameters with the local anomalies captured by spatial parameters. The two types of features are integrated into the model for collaborative judgment, realizing the collaborative detection of instantaneous spatial anomalies and temporal gradual anomalies, and ensuring the comprehensiveness of anomaly detection.

[0050] Achieve root cause tracing of anomalies While completing the above feature screening and anomaly determination, a mapping relationship between parameter correlation anomalies and wafer manufacturing process and test equipment status is established. This mapping relationship is constructed based on a large amount of historical wafer testing anomaly data and corresponding process and equipment fault records. Through the correlation characteristics of abnormal parameters, the specific root cause of the anomaly is traced back. The root cause of the anomaly includes wafer manufacturing process deviation and test equipment operation anomaly. Among them, wafer manufacturing process deviation includes photolithography process deviation, and test equipment operation anomaly includes probe contact failure.

[0051] After tracing is completed, the root cause information of the anomaly and the anomaly judgment result are output synchronously, providing specific basis for the optimization of wafer manufacturing process and the maintenance of testing equipment, realizing the integration of anomaly detection and root cause tracing.

[0052] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A chip wafer-level test anomaly detection method based on multidimensional parameter correlation analysis, characterized in that, Includes the following steps: Step 1: Collect core parameters and related data for wafer testing, and preprocess the collected data; Step 2: Construct a dynamic parameter association benchmark model based on the preprocessed historical normal data. The dynamic parameter association benchmark model has the ability to be updated in real time. Step 3: Calculate the correlation deviation between the real-time test parameters and the normal correlation coefficient matrix output by the dynamic parameter correlation benchmark model; Step 4: Set scenario-specific dynamic thresholds based on wafer manufacturing process and chip model; Step 5: Based on the comparison results between the correlation deviation and the dynamic threshold, and combined with the individual parameter specifications, determine the anomaly and output the result; Step six involves simultaneously generating a dynamic correlation list, performing feature filtering on high-dimensional test parameters, and integrating temporal and spatial parameters for dual-dimensional correlation detection to achieve root cause tracing of anomalies.

2. The chip wafer-level test anomaly detection method based on multidimensional parameter correlation analysis according to claim 1, characterized in that, The calculation of the correlation deviation between the real-time test parameters and the normal correlation coefficient matrix output by the dynamic parameter correlation benchmark model employs a hybrid algorithm that fuses cosine similarity and Euclidean distance. The specific calculation process includes: first, using the Pearson correlation coefficient method to calculate the correlation coefficients between the parameters after real-time preprocessing, obtaining the real-time correlation coefficient matrix; then, calculating the cosine similarity and Euclidean distance between the real-time correlation coefficient matrix and the normal correlation coefficient matrix; finally, calculating the fused correlation deviation using the fusion formula, which is: ,in The correlation deviation is a core indicator used to determine anomalies in the collaborative correlation of multiple parameters within a specification. Cosine similarity is used to characterize the directional consistency between the real-time correlation coefficient matrix and the normal correlation coefficient matrix. =Euclidean distance, used to characterize the degree of numerical difference between the real-time correlation coefficient matrix and the normal correlation coefficient matrix; 0.6 and 0.4 are the weight coefficients of cosine similarity and Euclidean distance, respectively, used to balance the influence of the two on the deviation of the fused correlation.

3. The chip wafer-level test anomaly detection method based on multidimensional parameter correlation analysis according to claim 1, characterized in that, The generation of the dynamic correlation list specifically includes: updating parameter clustering rules in real time through an adaptive clustering algorithm without requiring manual preset association rules; automatically identifying the correlation between new test parameters and existing test parameters, deleting invalid parameter association rules, and supplementing new parameter association relationships; and updating the dynamic correlation list synchronously with the dynamic parameter association benchmark model to ensure that the parameter clustering rules are consistent with the parameter association rules and adapt to the dynamic changes in wafer manufacturing processes.

4. The chip wafer-level test anomaly detection method based on multidimensional parameter correlation analysis according to claim 1, characterized in that, Feature screening of high-dimensional test parameters is performed using a hybrid linear-nonlinear correlation feature screening model. Specifically, this includes: initially screening and refining high-dimensional test parameters by fusing Pearson correlation coefficient and kernel function; capturing the linear correlation between test parameters using Pearson correlation coefficient and eliminating redundant linear parameters irrelevant to anomaly detection; capturing the nonlinear correlation between test parameters using kernel function and retaining nonlinear correlation parameters that affect anomaly detection; and outputting key test parameters after screening as input parameters for the dynamic parameter correlation benchmark model, providing a reliable parameter basis for correlation deviation calculation and anomaly determination.

5. The chip wafer-level test anomaly detection method based on multidimensional parameter correlation analysis according to claim 1, characterized in that, The integrated timing and spatial parameter dual-dimensional correlation detection specifically includes: collecting timing parameters from multiple tests on the same chip and spatial parameters from adjacent chips; processing the timing parameters using timing analysis algorithms to capture parameter drift trends; processing the spatial parameters using spatial neighborhood calculation methods to capture local parameter anomalies; constructing a timing-spatial dual-dimensional correlation model to perform correlation analysis between the parameter drift trends captured by the timing parameters and the local anomalies captured by the spatial parameters, thereby achieving collaborative detection of instantaneous spatial anomalies and temporally gradual anomalies, ensuring the comprehensiveness of anomaly detection.

6. The chip wafer-level test anomaly detection method based on multidimensional parameter correlation analysis according to claim 1, characterized in that, The specific dynamic threshold settings for the chosen scenario include: calculating the correlation deviation result based on preprocessed historical normal data, and using a specified quantile as the initial threshold value; calculating the average correlation deviation of the batch of normal wafers after each preset number of real-time tests are completed; if the average correlation deviation of the batch fluctuates beyond a preset range compared to the previous batch, the current threshold is fine-tuned; and simultaneously setting threshold range limits to ensure that the threshold is always within a reasonable range, adapting to the testing requirements of different manufacturing processes and different chip models, and avoiding misjudgments and missed detections caused by unreasonable thresholds.

7. The chip wafer-level test anomaly detection method based on multidimensional parameter correlation analysis according to claim 1, characterized in that, The specific steps for tracing the root cause of anomalies include: simultaneously performing feature screening and anomaly determination on high-dimensional test parameters, establishing a mapping relationship between parameter-related anomalies and wafer manufacturing processes and test equipment status; tracing back the specific root cause of the anomaly through the correlation characteristics of the anomaly parameters; the root causes of the anomalies include wafer manufacturing process deviations and test equipment malfunctions, where wafer manufacturing process deviations include lithography process deviations, and test equipment malfunctions include probe contact defects; after tracing is completed, the anomaly root cause information and anomaly determination results are output synchronously to provide a basis for process optimization and equipment maintenance.

8. The chip wafer-level test anomaly detection method based on multidimensional parameter correlation analysis according to claim 1, characterized in that, The acquisition of core wafer testing parameters and related data also includes the acquisition of test equipment operating parameters. Specifically, the core wafer testing parameters are the essential electrical parameters that must be measured in wafer testing, and the test equipment operating parameters include probe contact force, temperature control platform temperature, and test voltage stability. The core wafer testing parameters and test equipment operating parameters are integrated to construct a chip-equipment parameter correlation model. This model is used to analyze the parameter correlation relationship, distinguish between chip defects and anomalies caused by equipment interference, and ensure the accuracy of anomaly determination.

9. The chip wafer-level test anomaly detection method based on multidimensional parameter correlation analysis according to claim 1, characterized in that, In the process of calculating the correlation deviation and constructing the dynamic parameter correlation benchmark model, a lightweight CART correlation analysis algorithm is adopted. Specifically, this includes: retaining key correlation parameters and eliminating irrelevant parameters through an adaptive parameter dimension pruning method; optimizing the decision tree node splitting rules to simplify the algorithm calculation steps; reducing the algorithm's computational complexity and improving its computational efficiency without changing the detection logic and judgment criteria, adapting to the needs of rapid testing of mass-produced wafers, and ensuring the timeliness of real-time detection.

10. The chip wafer-level test anomaly detection method based on multidimensional parameter correlation analysis according to claim 1, characterized in that, In the process of constructing the dynamic parameter correlation benchmark model and calculating the correlation deviation, a dynamic parameter weight allocation mechanism is adopted, which specifically includes: constructing a parameter weight allocation model based on the degree of influence of each test parameter on chip performance and the abnormal contribution rate of each parameter in historical abnormal data; automatically allocating the weight of each test parameter in the correlation analysis through this model, with key parameters that have a greater impact on chip performance and a higher abnormal contribution rate being assigned higher weights; and dynamically adjusting the parameter weights in sync with the update of historical abnormal data to ensure the pertinence and accuracy of correlation analysis and anomaly judgment.

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