Off-chip load capacitor-free low dropout linear regulator circuit with transient enhancement structure

Abstract

The invention belongs to the technical field of semiconductor circuits, and particularly relates to an off-chip load capacitor-free low dropout linear regulator circuit with a transient enhancement structure, which mainly comprises the following seven parts: an enabling circuit, a starting circuit, a current reference circuit, an operational amplifier A, a source follower, a power tube output circuit and an operational amplifier B. The low-dropout linear voltage regulator circuit does not need an additional load capacitor, and compared with a traditional low-dropout linear voltage regulator, the low-dropout linear voltage regulator circuit can remarkably reduce the use cost; the capacitance requirement of an internal circuit does not need to be too large, the chip size can be reduced, and the cost is further reduced.

Description

Technical Field

[0001] This invention belongs to, but is not limited to, the field of semiconductor circuit technology, and particularly relates to a low-dropout linear regulator circuit with transient enhancement structure and no external load capacitor. Background Technology

[0002] A linear drop-out regulator (LDO) is a type of low-dropout voltage regulator circuit used to convert unstable supply voltages into stable output voltages. LDOs are widely used in integrated power management, mobile terminals, RF front-end power supplies, system-on-chips (SoCs), and analog mixed-signal applications due to their advantages such as simple structure, low output noise, low quiescent power consumption, and good power supply rejection ratio. A typical LDO structure includes basic modules such as a stable reference voltage source, an error amplifier, a feedback voltage divider network, and a power transistor.

[0003] In traditional LDO circuits, a reference voltage source provides a stable reference voltage for the error amplifier. The error amplifier compares the feedback voltage from the output voltage feedback network with the reference voltage, generates an error signal, and drives the power transistor to adjust the output voltage, thus achieving closed-loop control. To ensure the stability and sufficient phase margin of the closed-loop control system, traditional LDO designs generally require a large external load capacitor (typically greater than or equal to 1 μF) at the output. This capacitor plays a crucial role in the system's frequency response. On one hand, a larger capacitance value significantly reduces the pole frequency of the output node, effectively separating it from the poles generated by the internal amplifier, thereby avoiding oscillations caused by insufficient phase margin. On the other hand, the external capacitor acts as a charge buffer, rapidly supplying / absorbing charge to the load when the load current changes rapidly, suppressing output voltage overshoot and undershoot, while simultaneously reducing high-frequency output impedance and improving transient response performance.

[0004] However, the reliance of traditional LDOs on external load capacitors presents several key practical problems that significantly limit the design and implementation of integrated, miniaturized, and low-cost power management systems. First, high-quality, large-capacitance capacitors are expensive (especially low equivalent series resistance (ESR) ceramic capacitors), making it difficult to meet cost control requirements in BOM-sensitive applications such as consumer electronics. Second, the physical size and packaging space requirements of the load capacitors hinder system miniaturization and high integration, especially in advanced packaging technologies (such as WLP and 2.5D / 3D packaging). Third, the ESR characteristics of the load capacitors are highly dependent on loop stability; when the actual external capacitor ESR does not meet design expectations, it can easily cause loop oscillations, reducing system reliability.

[0005] To address the aforementioned issues, the Capacitor-Less Linear Regulator (CL-LDO) without external load capacitors was developed. Its design goal is to eliminate dependence on large external output capacitors while maintaining good loop stability and transient response performance. CL-LDOs compensate for the stability contribution of traditional output capacitors through internal design. However, after removing the large load capacitor, the system loses its fast charge buffering capability at the output node. The output node's response to sudden changes in load current is prone to large voltage overshoots or undershoots. This overshoot / undershoot not only affects the regulator's dynamic performance but may also lead to malfunctions or even damage to downstream circuits in certain sensitive power supply scenarios. Therefore, how to achieve stable closed-loop regulation and significantly improve transient response without relying on external output capacitors is a core technical challenge that urgently needs to be overcome in CL-LDO design.

[0006] Existing technology discloses a low-dropout linear regulator without external load capacitors, which improves loop stability through an internal compensation network. However, this structure still exhibits significant voltage overshoot and undershoot during rapid load current switching. Furthermore, its internal bias path risks entering a zero-current steady state during the power-on transient phase, leading to prolonged regulator startup time and the output voltage failing to converge quickly to the target value. This indicates that existing technology cannot achieve an ideal balance between steady-state stability and transient response, failing to completely solve the core pain points in CL-LDO design.

[0007] Therefore, there is an urgent need for a new low-dropout linear regulator circuit without external load capacitors. By improving the bias setup, error amplification, and transient enhancement structure, the load transient performance can be significantly improved while maintaining loop stability, so as to meet the needs of power supply systems with high integration, low cost, and strong dynamic performance. Summary of the Invention

[0008] To address the problems existing in the prior art, the present invention provides a low-dropout linear regulator circuit with transient enhancement structure and no external load capacitor.

[0009] This invention is implemented as follows: a low-dropout linear regulator circuit with transient enhancement structure and no external load capacitor. The circuit mainly includes the following seven parts: enable circuit, startup circuit, current reference circuit, operational amplifier A, source follower, power transistor output circuit, and operational amplifier B.

[0010] Furthermore, the enabling circuit is composed of , , , , , , , , , The circuit is configured such that it starts when the enable signal PD is high and stops when PD is low.

[0011] Furthermore, the startup circuit is composed of ~ , , , , Composition; When the enable signal PD just jumps from low level to high level, at this time =0, Deadline ~ Conductive, they are with This branch will generate current, and through Mirror current to , making , The current in the branch is not zero at that moment, thus preventing the bias circuit from entering a steady state where all currents are zero. After the circuit starts normally, Greater than Threshold voltage This allows it to conduct, at which point the current will no longer flow. The starting circuit will no longer affect subsequent circuits, if set Less than If so, then it needs to make corresponding adjustments; The purpose is to prevent transient oscillations or even jumps when the circuit is first started.

[0012] Furthermore, the current reference circuit is composed of , , , , composition. and If a current mirror is constructed and all components are of identical size, then the current flowing through both branches will be equal. This current serves as the reference current for this invention, and its value is assumed to be I. The gate source voltage is Then the expression for the reference current is:

[0013] (1)

[0014] As long as the appropriate settings are configured of as well as If the value of is determined, a reference current source that is not significantly affected by temperature can be obtained.

[0015] Furthermore, the operational amplifier A is composed of ~ , ~ as well as Composition: The operational amplifier adopts a folded cascode structure and uses PMOS as the input differential pair, which can reduce flicker noise and is suitable for low input common-mode conditions. This folded cascode amplifier also has a wide common-mode input range and a large output voltage swing. At the same time, this structure can also improve the power supply rejection ratio.

[0016] Furthermore, the source follower is composed of , Its low output impedance reduces the load capacitance of operational amplifier A, making it easier to push the poles of the power transistor MPT to higher frequencies. The pole equation is:

[0017] (2)

[0018] in, For the transconductance of MPS, The gate pole of the power transistor MPT This is the gate-source capacitance of the power transistor MPT. Therefore, the compensated dominant pole is located at the output of the error amplifier, and the CL-LDO output stage will serve as the secondary pole.

[0019] Furthermore, the output circuit consists of an MPT, , Composition; because the switching transistor... Since the impedance is approximately 0, the output voltage is... The expression is approximately:

[0020] (3)

[0021] Furthermore, the operational amplifier B is composed of ~ , , Composition: The operational amplifier is a five-transistor operational amplifier with NMOS as the differential pair. It has a large bandwidth and slew rate, and can quickly respond to changes in load current, thereby quickly raising or lowering the gate voltage of the power transistor and enhancing the transient characteristics of the output circuit.

[0022] Based on the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solution to be protected by this invention are as follows:

[0023] The present invention proposes a low-dropout linear regulator circuit with transient enhancement structure and no external load capacitor. Through circuit structure design, it can quickly respond to load changes and reduce the overshoot and undershoot voltages caused by load jumps. In addition, it also has a high power supply rejection ratio and a current reference circuit with a reliable startup circuit.

[0024] Unlike traditional LDOs that rely on external capacitors at the μF level to maintain stability, this invention achieves operation without external capacitors through internal structural optimization. This not only saves the cost of expensive, high-quality, low-ESR capacitors but also avoids the risk of oscillation caused by mismatched capacitor parameters. At the same time, it facilitates system miniaturization and advanced packaging integration, which can significantly reduce the difficulty and cost of use.

[0025] By employing a source follower structure, this invention pushes the output pole to a higher frequency without requiring large internal capacitor compensation, thus enhancing transient recovery capability. This design improves performance while incurring only minimal additional area overhead, which is beneficial for chip miniaturization and cost control.

[0026] To address the issue of voltage overshoot and undershoot that can easily occur in LDOs without external capacitors during load transitions, this invention innovatively introduces a high-bandwidth, high-slew-rate auxiliary operational amplifier B, which can quickly adjust the gate voltage of the power transistor, thereby effectively suppressing voltage fluctuations, improving the dynamic response performance of the system, and providing a simple and efficient compensation structure.

[0027] By using an operational amplifier A with a folded cascode structure, the circuit still has good common-mode range and output swing under low input common-mode conditions, and significantly improves the power supply rejection ratio of the circuit, so that the overall circuit of the low dropout linear regulator without external load capacitor has excellent noise suppression capability.

[0028] (1) The expected benefits and commercial value of the technical solution of this invention after transformation are as follows:

[0029] This invention introduces a composite compensation structure combining a source follower and an auxiliary high-speed operational amplifier, effectively improving system bandwidth and transient recovery speed without requiring external capacitors, while simultaneously achieving a high power supply rejection ratio. This structure simplifies the compensation mechanism while maintaining performance, achieving an optimized balance between performance, area, and cost. This technical solution significantly reduces the system's reliance on high-cost, bulky external capacitors, making it particularly suitable for portable devices, IoT nodes, wearable devices, and highly integrated system-on-a-chip (SoC) applications with stringent requirements for chip area, system cost, and package size. It is expected to significantly reduce overall material costs and enhance product competitiveness. In its commercialization process, this technology is expected to become a core module of the next generation of highly integrated power management chips, possessing broad market prospects and high economic added value.

[0030] (2) The technical solution of the present invention solves a technical problem that people have long wanted to solve but have never been able to solve successfully:

[0031] Traditional LDO designs rely on large external capacitors to isolate poles and provide charge buffering. However, removing these external capacitors can easily lead to oscillations or slow responses due to pole position shifts. It is widely believed in the industry that LDOs require large external capacitors to ensure system stability and good transient performance, especially under heavy load changes. This invention, through an innovative internal pole-boosting and dynamic compensation mechanism, demonstrates that the function of external capacitors can be completely replaced by optimizing the internal circuit structure alone. Without relying on any external capacitors, this solution significantly improves overshoot and undershoot voltages and achieves fast load transient response and high loop stability when the load current changes, successfully solving the long-standing technical challenge of achieving both fast transient response and high stability without external capacitors. Furthermore, this solution breaks away from the common design approach of "adding large internal capacitors or complex compensation networks to improve transient response," achieving a significant performance improvement with a simple and efficient architecture. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of a low-dropout linear regulator circuit with transient enhancement structure and no external load capacitor provided in an embodiment of the present invention.

[0033] Figure 2 This is a schematic diagram of the circuit structure provided in an embodiment of the present invention;

[0034] Figure 3 These are waveforms comparing the output voltage transient response with and without the transient enhancement structure in this embodiment of the invention.

[0035] Figure 4 This is a waveform diagram of the output voltage power supply rejection ratio in an embodiment of the present invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0037] like Figure 1 As shown, the low-dropout linear regulator circuit without external load capacitor in this embodiment includes an input terminal VDD, a reference terminal REF, an enable control terminal SEL, an output terminal VOUT, and a ground terminal GND. Internally, it consists of a steady-state regulation path and a transient enhancement path, and is uniformly scheduled through the control node of the power output module. Figure 2As shown, each functional module is further refined at the transistor level into enable and disable circuits, startup circuits, reference current generation unit, error amplifier module OPA A, source follower drive module, power transistor MPT, transient enhancement amplifier module OPA B, and output feedback network.

[0038] During the circuit startup phase, the enable control terminal SEL triggers the enable circuit to operate. The startup circuit provides a startup bias to the reference current generation unit during the initial VDD power-up phase, preventing the system from entering the zero-current steady-state point. After the reference current generation unit establishes a stable bias current, it provides operating bias for the error amplification module OPA A and the transient enhancement amplification module OPA B.

[0039] Under steady-state operating conditions, the output terminal VOUT is connected to a resistor. , The voltage divider network is fed back to the input of the error amplifier module OPA A, forming a closed-loop comparison with the reference terminal REF. OPA A amplifies the steady-state error signal with high gain, and its output is buffered by the source follower driver module before driving the gate of the power transistor MPT. The source follower structure effectively reduces the equivalent output impedance of the MPT gate node, increases the pole frequency of that node, and keeps the system's dominant pole located at the output of OPA A in a controlled manner, thereby maintaining the system's stability and steady-state output accuracy without external load capacitors.

[0040] When the load current undergoes a rapid step change, a transient voltage disturbance is generated at the output terminal VOUT. This disturbance signal is directly sensed by the transient enhancement amplifier module OPA B. Through a direct coupling path with the control terminal of the power transistor MPT, OPA B bypasses the bandwidth limitation of the steady-state regulation path. With its high bandwidth and high slew rate characteristics, it rapidly modulates the gate drive voltage of the MPT, instantaneously enhancing the current supply or absorption capability of the output stage, thereby suppressing overshoot or undershoot of the output voltage and shortening the recovery time.

[0041] As the output voltage gradually returns to its steady-state value, the amplitude of the transient error signal decreases, and the effect of the transient enhancement path automatically weakens, with the system's regulation control returning to the steady-state regulation path. Thus, the steady-state regulation path and the transient enhancement path work synergistically under different operating sequences, achieving a technical effect that balances stability and transient response performance without external load capacitors.

[0042] The low-dropout linear regulator circuit with transient enhancement structure and no external load capacitor described in this invention is not simply a high-speed amplification unit superimposed on the traditional low-dropout linear regulator. Instead, it focuses on the core technical goal of "simultaneously satisfying stability and transient response under the condition of no external load capacitor" and constructs a dual-path regulation mechanism in which the steady-state regulation path and the transient enhancement path have clear division of labor and coordinated control in the time and frequency domains.

[0043] Under steady-state operating conditions, the load current changes slowly or remains constant, and the output voltage regulation is mainly accomplished by the steady-state regulation path. The error amplifier module amplifies the deviation between the output voltage and the reference voltage with high gain, and its output is applied to the control terminal of the power output module via the source follower driver module. The source follower driver module reduces the equivalent output impedance of this control node, pushing the gate pole of the power output module high, thereby ensuring that the dominant pole of the system stably falls at the output terminal of the error amplifier module, guaranteeing that the system still has sufficient phase margin and steady-state accuracy even without external load capacitors. In this state, the transient enhancement path, due to its extremely small input change amplitude, naturally suppresses its influence on the control node and does not participate in the steady-state regulation process, thus not introducing additional static errors or power consumption burdens.

[0044] When the load current undergoes a step change, the output voltage will shift rapidly within a very short time. At this time, due to the limited bandwidth of the error amplification module, its output change has an inherent delay. Relying solely on the steady-state regulation path will significantly prolong the output voltage recovery time. This invention addresses this by directly coupling a transient enhancement amplification module to the control terminal of the power output module. This allows the module to bypass the low-frequency limitations of the steady-state regulation path and prioritize sensing and responding to rapid changes in the output voltage. The transient enhancement amplification module employs a simplified field-effect transistor differential structure, achieving high bandwidth and high slew rate characteristics with relatively low static power consumption. This allows it to rapidly increase or decrease the drive voltage of the power output module during sudden load current changes, significantly enhancing the transient current supply or absorption capability at the output terminal and suppressing output voltage overshoot or undershoot.

[0045] As the output voltage gradually recovers to the target value, the transient disturbance amplitude decreases, the effect of the transient enhancement path automatically weakens, and the system's regulatory control smoothly returns to the steady-state regulation path. This forms a dual-path collaborative regulation mechanism based on adaptive switching of operating states, ensuring that steady-state accuracy and transient performance are each handled by the most suitable regulation path, with the two complementing each other rather than interfering with each other in terms of time scale and frequency characteristics. This overall mechanism is not an arbitrary combination of functional modules in existing technologies, but rather, under the constraint of no external load capacitor, it achieves a balance between stability and transient performance—a balance that is difficult to achieve in traditional low-dropout linear regulators—through a systematic design of structural coupling relationships and operational timing.

[0046] In one exemplary embodiment, the present invention provides a low-dropout linear regulator circuit with transient enhancement structure and no off-chip load capacitor, which can be integrated into a single semiconductor chip and is suitable for applications requiring fast load response and stable output voltage in on-chip power supply, analog / mixed signal systems or low-power system-on-a-chip.

[0047] Preferably, the enable control module can be implemented using CMOS logic gates or level comparators to selectively connect the power path and bias network based on an external enable signal. In one example, the enable control module uses a transmission gate or a controlled switching transistor to uniformly control the startup bias establishment module and the current reference module, thereby reducing static power consumption in the off state.

[0048] The startup bias establishment module can be implemented using a weakly inverting operating region transistor, a subthreshold current source, or an RC delay trigger structure. In a preferred embodiment, the startup bias establishment module injects a non-zero startup current into the current reference module during the rising edge of the enable signal. The amplitude of this current can be selected from 1 nA to 1 μA, exemplarily including approximately 10 nA, 100 nA, or 500 nA, to prevent the reference branch and error amplification module from falling into a zero-current steady state. After startup, the module can be automatically bypassed or shut down, thus not affecting steady-state power consumption.

[0049] The current reference module can be implemented using a bandgap reference, a current mirror, or a self-biased reference structure, and provides a stable bias to the first error amplification module and the second transient enhancement amplification module. For example, the reference current can be set in the range of 1 μA to 50 μA, and the specific value can be adjusted according to the process node, power supply voltage, and target static power consumption.

[0050] The first error amplification module is preferably a high-gain differential amplifier structure, whose input terminals receive the feedback signal of the output voltage and the reference voltage signal, respectively, to generate a steady-state regulation control signal. In different embodiments, this module can adopt a single-stage folded cascode structure, a two-stage operational amplifier structure, or a multi-stage amplification structure with internal compensation capacitors to adapt to different stability and gain requirements.

[0051] The source follower drive module is positioned between the first error amplifier module and the power output module. It is preferably composed of a source follower transistor or a buffer stage, and its equivalent output impedance is significantly lower than the direct output impedance of the error amplifier module, thereby shifting the gate pole of the power output module to a higher frequency band. For example, this module can employ an NMOS or PMOS source follower structure, and the bias current can be selected in the range of 5 μA to 100 μA.

[0052] The power output module is preferably a large-size PMOS power transistor, but in other embodiments, an NMOS plus charge pump or a composite power transistor structure can also be used, with its drain connected to the input power supply and its source connected to the output terminal, to provide a stable voltage to the load.

[0053] The second transient enhancement amplification module is coupled in parallel to the control terminal of the power output module to provide a high-speed regulation path when the load current changes rapidly. For example, this module can be connected to the gate of the power transistor via capacitive coupling, transconductance amplification, or a transient detection network to quickly adjust the gate voltage during sudden increases or decreases in load, thereby significantly improving the undershoot and overshoot characteristics of the output voltage. Its operation may only be effective during transient periods, with minimal impact on system gain and stability in steady state.

[0054] Through the above multi-module collaborative configuration, the present invention achieves an effective balance between steady-state stability and transient response speed in a low-dropout regulator without the need for an external load capacitor, and has good engineering adaptability and scalability.

[0055] This invention provides a low-dropout linear regulator circuit with transient enhancement structure and no external load capacitor. The circuit mainly includes the following seven parts: enable circuit, startup circuit, current reference circuit, operational amplifier A, source follower, power transistor output circuit, and operational amplifier B.

[0056] The enabling circuit is composed of , , , , , , , , , The circuit is configured such that it starts when the enable signal PD is high and stops when PD is low.

[0057] The startup circuit is composed of ~ , , , , Composition; When the enable signal PD just jumps from low level to high level, at this time =0, Deadline ~ Conductive, they are with This branch will generate current, and through Mirror current to , making , The current in the branch is not zero at that moment, thus preventing the bias circuit from entering a steady state where all currents are zero. After the circuit starts normally, Greater than Threshold voltage This allows it to conduct, at which point the current will no longer flow. The starting circuit will no longer affect subsequent circuits, if set Less than If so, then it needs to make corresponding adjustments; The purpose is to prevent transient oscillations or even jumps when the circuit is first started.

[0058] The current reference circuit is composed of , , , , composition. and If a current mirror is constructed and all components are of identical size, then the current flowing through both branches will be equal. This current serves as the reference current for this invention, and its value is assumed to be I. The gate source voltage is Then the expression for the reference current is:

[0059] (1)

[0060] As long as the appropriate settings are configured of as well as If the value of is determined, a reference current source that is not significantly affected by temperature can be obtained.

[0061] The operational amplifier A is composed of ~ , ~ as well as Composition: The op-amp adopts a folded cascode structure and uses PMOS as the input differential pair, which can reduce flicker noise and is suitable for low input common-mode conditions. This folded cascode amplifier also has a wide common-mode input range and a large output voltage swing. At the same time, this structure can also improve the power supply rejection ratio.

[0062] The source follower is composed of , Its low output impedance reduces the load capacitance of operational amplifier A, making it easier to push the poles of the power transistor MPT to higher frequencies. The pole equation is:

[0063] (2)

[0064] in, For the transconductance of MPS, The gate pole of the power transistor MPT This is the gate-source capacitance of the power transistor MPT. Therefore, the compensated dominant pole is located at the output of the error amplifier, and the CL-LDO output stage will serve as the secondary pole.

[0065] The output circuit consists of MPT, , Composition; because the switching transistor... Since the impedance is approximately 0, the output voltage is... The expression is approximately:

[0066] (3)

[0067] The operational amplifier B is composed of ~ , , Composition: The operational amplifier is a five-transistor operational amplifier with NMOS as the differential pair. It has a large bandwidth and slew rate, and can quickly respond to changes in load current, thereby quickly raising or lowering the gate voltage of the power transistor and enhancing the transient characteristics of the output circuit.

[0068] The low-dropout linear regulator circuit with transient enhancement structure and no external load capacitor provided by this invention can be widely used in portable electronic products such as smartphones, wearable devices, and IoT terminals, as well as in fields with stringent requirements for power supply size, cost, noise suppression, and dynamic response, such as highly integrated system-on-chips, system-in-package, RF front-ends, and high-precision data converters. It can be used as an independent power management chip or integrated into various chips as an IP core, effectively achieving system miniaturization, low cost, and high-performance power supply.

[0069] To verify the actual performance of the present invention, the circuit was simulated and verified under typical operating conditions using the SMIC 180nm process and the Cadence Virtuoso platform.

[0070] Key performance data are as follows: When the load current jumps from 0mA to 50mA and then back to 0mA within 1μs, without the transient enhancement structure (operational amplifier B), the output voltage overshoot is 268.5mV and the undershoot is 239.9mV. With the transient enhancement structure, the output voltage overshoot is only 165.5mV and the undershoot is only 136.7mV. See the comparison results below. Figure 3 As shown, the output voltage overshoot peak was reduced by 38.4%, and the undershoot peak was reduced by 42.9%. The fluctuation range was strictly limited to within ±10% of the stable output voltage value. This fully demonstrates that the present invention still has excellent fast transient response and voltage recovery capability without any external capacitor support.

[0071] Furthermore, the power supply rejection ratio (PSRR) of the simulated circuit under no-load (0mA) and full-load (50mA) conditions showed that even at its worst, the PSRR reached -70dB at a frequency of 1kHz, demonstrating excellent power supply noise suppression performance. The output results are shown in [link to output]. Figure 4 As shown above, the data effectively confirms that this invention, through internal structural innovation, successfully achieves multiple technical advantages, including no external capacitors, high stability, and high power supply rejection ratio.

[0072] Example 1: Transient Enhancement Voltage Regulator Structure with Virtually No External Load Capacitor

[0073] This embodiment provides a low-dropout linear regulator circuit that operates without any external load capacitor. By employing a parallel structure of steady-state regulation and transient enhancement paths, the output voltage remains stable even during sudden changes in load current. The steady-state regulation path maintains output voltage accuracy, while the transient enhancement path directly applies to the power transistor control terminal during load changes, thus avoiding the traditional design approach that relies on external capacitor energy storage and significantly shortening the voltage recovery time.

[0074] Example 2: Voltage regulator circuit with startup bias protection

[0075] Building upon Example 1, this example further incorporates a startup bias establishment structure. When the enable signal switches from the off state to the on state, this structure injects startup current into the internal reference node, preventing the bias network from entering a zero-current steady state. Once the system enters the normal operating region, the startup branch automatically exits, no longer affecting steady-state performance. This design ensures reliable startup under low-voltage and low-power conditions, improving overall system stability.

[0076] Example 3: Implementation method for suppressing startup transient oscillations

[0077] Based on Embodiment 2, a capacitor buffer mechanism is introduced at the startup bias node to ensure that the node voltage rises slowly during startup, preventing oscillations or false triggering of the error amplification stage due to excessively rapid voltage transitions. This structure allows the regulator to enter a controlled state immediately upon power-up, improving system robustness and making it particularly suitable for on-chip system environments with high power supply stability requirements.

[0078] Example 4: Pole control structure based on source follower drive

[0079] This embodiment introduces a source follower drive structure between the error amplification module and the power output module to reduce the equivalent output impedance of the drive node. This structure effectively shifts the poles of the power transistor control terminal to a higher frequency, ensuring that the system's dominant poles are stably distributed at the error amplifier output, thus maintaining good phase margin even without a load capacitor. This approach differs from traditional compensation capacitor methods and exhibits significant structural innovation.

[0080] Example 5: High-bandwidth transient enhancement and amplification structure

[0081] Building upon the aforementioned embodiments, this embodiment establishes an independent transient enhancement amplification path. This path employs a simplified amplification structure to achieve higher bandwidth and a larger voltage change rate. When the load current changes rapidly, this amplification structure can adjust the power transistor control voltage before the steady-state regulation path has fully responded, thereby significantly reducing the output voltage drop or overshoot, demonstrating a clear improvement in transient performance.

[0082] Example 6: Integrated Application of On-Chip Power Management System

[0083] This embodiment integrates the aforementioned voltage regulator structure into an on-chip power management system, which works in conjunction with the reference voltage unit and the enable control unit to provide stable power to the digital logic module or analog module. It achieves a balance between high integration, low power consumption, and fast transient response without requiring external load capacitors. This makes it particularly suitable for system-on-a-chip applications where area is limited and the number of peripheral devices is strictly controlled, demonstrating significant engineering practical value and innovative advantages.

[0084] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A low-dropout linear regulator circuit with transient enhancement structure and no external load capacitor, characterized in that, The circuit includes an enable control module, a startup bias establishment module, a current reference module, a first error amplification module, a source follower drive module, a power output module, and a second transient enhancement amplification module. in: The enable control module is used to selectively turn the low dropout linear regulator circuit on or off under the action of an external enable signal; The bias establishment module provides a non-zero bias current to the current reference module when the enable signal changes from the off state to the on state, so as to prevent the subsequent analog circuit from entering the zero current steady state. After startup, the current reference module generates a stable reference current and provides bias to the first error amplification module and the second transient enhancement amplification module. The first error amplification module is used to amplify the error signal between the output voltage and the reference voltage to form a steady-state regulation control signal; The source follower drive module is located between the first error amplification module and the power output module to reduce the equivalent output impedance of the drive node, thereby pushing the gate pole of the power output module to a higher frequency. The second transient enhancement amplification module is coupled in parallel to the control terminal of the power output module to provide a high-speed voltage regulation path when the load current changes abruptly.

2. The low-dropout linear regulator circuit according to claim 1, characterized in that, The startup bias establishment module includes a current injection branch and a delay stabilization branch controlled by the enable signal. It injects startup current into the current reference module during the initial stage when the enable signal transitions from low to high level, and automatically exits the working state after the current reference module establishes a stable operating point.

3. The low-dropout linear regulator circuit according to claim 2, characterized in that, The startup bias establishment module includes a capacitor element for suppressing startup transient oscillations. This capacitor element performs gradual voltage control on key bias nodes during the initial power-on phase of the circuit to avoid oscillations or jumps at the output nodes.

4. A low-dropout linear regulator circuit with transient enhancement structure and no external load capacitor, characterized in that, The circuit includes a steady-state regulation path and a transient enhancement path, wherein: The steady-state regulation path includes an error amplification module, a source follower drive module, and a power output module, which are used to maintain the steady-state accuracy of the output voltage under stable load current conditions. The transient enhancement path includes a transient enhancement amplification module directly coupled to the control terminal of the power output module, which has high bandwidth and high slew rate characteristics; When the load current undergoes a step change, the transient enhancement path preferentially acts on the control terminal of the power output module to quickly increase or decrease its drive voltage, thereby shortening the recovery time of the output voltage. Under steady-state conditions, the steady-state regulation path dominates the output voltage regulation, ensuring that the transient enhancement path does not introduce additional steady-state errors. Thus, a dual-path collaborative mechanism is used to achieve both high stability and high transient performance under conditions without external load capacitors.

5. The low-dropout linear regulator circuit according to claim 4, characterized in that, The transient enhancement amplification module adopts a simplified amplification structure composed of differential pairs of field-effect transistors, which enables it to obtain a large signal bandwidth and voltage change rate under relatively low static power consumption conditions.

6. The low-dropout linear regulator circuit according to claim 4, characterized in that, The source follower drive module reduces the equivalent output impedance of the power output module control node, thereby increasing the gate pole frequency of the power output module and stabilizing the main pole at the output node of the error amplification module.

7. A low-power integrated power management system, characterized in that, The system includes an input power interface, an enable control interface, a reference voltage generation unit, and a low-dropout linear regulator circuit. The low-dropout linear regulator circuit described herein is the low-dropout linear regulator circuit according to any one of claims 1 to 6. The system provides a stable output voltage to the load without an external load capacitor and maintains the ability to quickly recover the output voltage when the load current changes abruptly.

8. The low-power integrated power management system according to claim 7, characterized in that, The system is applied to on-chip power supply scenarios where chip area and the number of peripheral devices are limited.

9. The low-power integrated power management system according to claim 7, characterized in that, The output of the low-dropout linear regulator circuit provides a feedback signal to the error amplification module through a resistor divider to determine the magnitude of the system output voltage.

10. The low-power integrated power management system according to claim 7, characterized in that, The enable control interface starts the low-dropout linear regulator circuit when it receives a high-level control signal and shuts down the low-dropout linear regulator circuit when it receives a low-level control signal, thereby reducing the system's standby power consumption.

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