Linear voltage regulator adopting ripple suppression and impedance enhancement

Abstract

The invention discloses a high-PSRR (power supply rejection ratio) linear voltage regulator adopting ripple suppression and impedance enhancement, belongs to the technical field of power management chips, and solves the problems of how to improve the power supply rejection ratio of an LDO (low dropout regulator) and how to reduce the chip area. The band-gap reference source is connected through the low-frequency enhancement module to form a negative feedback loop, and the power supply rejection ratio at the low-frequency position is improved by improving the impedance from the source to the ground; a ripple sampling unit in the medium-high frequency enhancement module adopts a pseudo resistor structure, sampling current can be accurately controlled by adjusting the width-to-length ratio of a transistor, an equivalent resistor with a great resistance value is provided, the equivalent resistor and a capacitor C0 form a sampling filter, power supply feedforward ripples are collected, and the ripples are injected into a grid electrode of a power tube PM after being amplified. The linear voltage regulator has the advantages that the power supply rejection ratio of the linear voltage regulator at medium-high frequency is improved, and the area consumption of a chip is reduced.

Description

Technical Field

[0001] This invention belongs to the field of power management chip technology and relates to a high PSRR linear regulator that employs ripple suppression and impedance enhancement. Background Technology

[0002] Low dropout regulators (LDOs) are core components in power management. They achieve stable output voltage based on linear regulation and resistive feedback principles, offering advantages such as low voltage drop, low noise, and simple structure, playing a crucial role in electronic device power supply systems. As industries such as consumer electronics, automotive electronics, and the Internet of Things (IoT) upgrade towards miniaturization, low power consumption, and high precision, LDOs are gradually replacing traditional voltage regulators, and their application scenarios continue to expand. The global LDO market is steadily growing, with consumer electronics being the primary demand driver, and significant growth in automotive electronics and industrial control. Portable devices also have an urgent need for low-power, small-sized LDOs. The automotive electronics sector requires high reliability for voltage regulators, while industrial applications prioritize high-precision voltage regulation capabilities.

[0003] Power supply rejection ratio (PSRR) is a core performance indicator of low-dropout linear regulators (LDOs), primarily affected by four paths: the bandgap reference path, the error amplifier path, the drain-source transconductance of the power transistor, and the gate-source transconductance of the power transistor. The bandgap reference path mainly affects the LDO's PSRR at low frequencies due to insufficient power supply-to-ground impedance, while the drain-source and gate-source transconductances of the power transistor mainly affect the PSRR at mid-to-high frequencies.

[0004] For mid-to-high frequency power supply rejection ratio (PSR) processing, existing technologies typically employ feedforward ripple suppression (FFRC) technology with low-dropout voltage regulators (LDVs). For example, patent application CN117850523A discloses a low-dropout linear regulator for ripple suppression. This regulator introduces the input ripple into the input of an error amplifier via a ripple-introducing capacitor, generating ripple at the output of the error amplifier. This ripple is in the same direction as the ripple at the input of the power transistor. Therefore, common-mode cancellation by the power transistor can suppress the output ripple and improve the PSR. The ripple suppression structure only requires adding capacitors and resistors. However, since the sampling structure required by FFRC technology mainly consists of capacitors and resistors, large resistors and capacitors are needed to obtain a lower roll-off start frequency, occupying a significant amount of chip area. This results in an excessively large area occupied by the sampling structure required in FFRC. Summary of the Invention

[0005] The technical problem to be solved by this invention is how to improve the power supply rejection ratio of LDO and reduce the chip area.

[0006] The present invention solves the above-mentioned technical problems through the following technical solutions:

[0007] A linear regulator employing ripple suppression and impedance enhancement includes a bandgap reference source, a low-frequency enhancement module, an error amplifier EA, a power transistor MP, a mid-to-high frequency enhancement module, and a resistive feedback module. The input terminal of the bandgap reference source is connected to an external voltage source Vin, the output terminal Vref of the bandgap reference source is connected to the non-inverting input terminal of the error amplifier EA, the inverting input terminal of the error amplifier EA is connected to the output terminal of the resistive feedback module, the output terminal of the error amplifier EA is connected to the mid-to-high frequency enhancement module, and the two ends of the low-frequency enhancement module are connected to the feedback loop of the bandgap reference source. The mid-to-high frequency enhancement module includes a current mirror unit, a ripple sampling unit, and a ripple amplification unit connected in sequence; the input terminal of the current mirror unit is connected to an external voltage source Vin, the output terminal of the injected ripple amplification unit is connected to the gate of the power transistor MP, the source of the power transistor MP is connected to the external voltage source Vin, and the drain of the power transistor MP is connected to the input terminal of the resistor feedback module. The current mirror unit provides sampling current to the ripple sampling unit. The ripple sampling unit samples the power supply ripple signal and injects it into the ripple amplification unit. The extracted ripple is amplified and injected into the power transistor MP to reduce the mid-to-high frequency power supply ripple. Specifically, the ripple sampling unit is a pseudoresistor sampling structure.

[0008] Furthermore, the bandgap reference source includes transistor MP9, transistor MP10, operational amplifier amp1, transistor PNP1, transistor PNP2, and resistors R5~R11; the sources of transistors MP9 and MP10 are both connected to an external voltage source Vin, and the gates of transistors MP9 and MP10 are connected together, with the connection point denoted as node Vg1. The drain of transistor MP9 is connected to one end of resistor R5, and the other end of resistor R5 is connected to the emitter of transistor PNP1. The connection point is denoted as node Vg2. The base and collector of transistor PNP1 are both grounded. Resistors R10 and R11 are connected in series. The non-series end of resistor R10 is connected to the drain of transistor MP9, and the non-series end of resistor R11 is grounded. The drain of transistor MP10 is connected to one end of resistor R6, and the other end of resistor R6 is connected to one end of resistor R7. The connection point is denoted as node Vg3. The other end of resistor R7 is connected to the emitter of transistor PNP2. The base and collector of transistor PNP2 are both grounded. Resistors R8 and R9 are connected in series. The non-series end of resistor R8 is connected to the drain of transistor MP10, and the non-series end of resistor R9 is grounded. The non-inverting input of the operational amplifier amp1 is connected to node Vg2, and the inverting input is connected to node Vg3.

[0009] Furthermore, the low-frequency enhancement module includes transistor MP1 and transistor MN1; the drain and gate of transistor MP1 are connected, the gate of transistor MP1 is connected to node Vg1 of the bandgap reference source, and the source of transistor MP1 is connected to an external voltage source Vin; the source of transistor MN1 is connected to the drain of transistor MP1, the gate of transistor MN1 is connected to the output terminal of operational amplifier amp1, and the drain of transistor MN1 is grounded.

[0010] Further, the current mirror unit includes a current source, transistor MP2, transistor MP3, transistor MN2, transistor MN3, and transistor MP4; the drain of transistor MP2 is connected to the current source, the source of transistor MP2 is connected to an external voltage source Vin, and the gate of transistor MP2 is connected to the drain; the drain of transistor MP3 is connected to the drain of transistor MN2, the source of transistor MP3 is connected to the external voltage source Vin, and the gate of transistor MP3 is connected to the gate of transistor MP2; the drain of transistor MN2 is connected to the drain of transistor MP3, the source of transistor MN2 is grounded, and the gate of transistor MN2 is connected to the drain of transistor MN2; the drain of transistor MN3 is connected to the drain of transistor MP4, the source of transistor MN3 is grounded, and the gate of transistor MN3 is connected to the gate of transistor MN2; the source of transistor MP4 is connected to the external voltage source Vin, and the gate of transistor MP4 is connected to the drain of transistor MP4.

[0011] Further, the ripple sampling unit includes transistor MN4, transistor MP5, transistor MP6, resistor R4, and capacitor C0; the drain of transistor MN4 is connected to one end of resistor R4, the other end of resistor R4 is connected to the drain of transistor MP5, the source of transistor MN4 is grounded, and the gate of transistor MN4 is connected to the gate of transistor MN3; the gate of transistor MP5 is connected to the drain of transistor MN4, and the connection point is denoted as node V3; the drain of transistor MP5 is connected to the gate of transistor MP6, and the connection point is denoted as node V4; the source of transistor MP5 is connected to the gate of transistor MP4; the source of transistor MP6 is connected to the gate of transistor MP4, and the drain of transistor MP6 is connected to one end of capacitor C0, the other end of capacitor C0 is grounded.

[0012] Furthermore, the sampling frequency of the ripple sampling unit Using the following logical representation:

[0013] in, Let R4 be the resistance value. Let C0 be the capacitance value.

[0014] Furthermore, the ripple amplification unit includes transistor MP7 and transistor MP8; the gate of transistor MP7 is connected to the drain of transistor MP6, the source of transistor MP7 is connected to an external voltage source Vin, and the drain of transistor MP7 is connected to the source of transistor MP8. The connection point is denoted as node V2. Node V2 serves as the output terminal of the mid-to-high frequency enhancement module and is connected to the gate of power transistor MP; the gate of transistor MP8 is connected to the output terminal of error amplifier EA, and the drain of transistor MP8 is grounded.

[0015] Furthermore, in the current mirror unit, the width-to-length ratio W / L of transistor MP2 is proportional to the width-to-length ratio W / L of transistor MP3, and the width-to-length ratio W / L of transistor MN2 is proportional to the width-to-length ratio W / L of transistor MN3. In the ripple amplification unit, transistors MP7 and MP8 have the same width-to-length ratio (W / L).

[0016] Furthermore, the resistive feedback module includes resistors R1 and R2 connected in series. The non-series terminal of resistor R2 is connected to the drain of the power transistor MP, and the non-series terminal of resistor R1 is grounded. The connection point of resistors R1 and R2 is denoted as node V1, and the inverting input terminal of error amplifier EA is connected to node V1.

[0017] Furthermore, the linear regulator also includes a resistor R3 and a capacitor C1; the drain of the power transistor MP serves as the output terminal of the linear regulator, the drain of the power transistor MP is connected to one end of the capacitor C1, the other end of the capacitor C1 is grounded, one end of the resistor R3 is connected to the drain of the power transistor MP, and the other end of the resistor R3 is grounded.

[0018] The advantages of this invention are: (1) This invention provides a high PSRR linear regulator with ripple suppression and impedance enhancement. The low-frequency enhancement module is connected to a bandgap reference source to form a negative feedback loop. The power supply rejection ratio at low frequencies is improved by increasing the impedance from the source to ground. The ripple sampling unit in the mid-to-high frequency enhancement module adopts a pseudoresistor structure. The sampling current can be precisely controlled by adjusting the width-to-length ratio of the transistor and an equivalent resistance with a very large resistance value can be provided. It forms a sampling filter with capacitor C0 to collect the power supply feedforward ripple. After ripple amplification, it is injected into the gate of the power transistor PM to improve the power supply rejection ratio (PSRR) of the linear regulator at mid-to-high frequencies. It has the advantage of reducing chip area consumption.

[0019] (2) The present invention introduces a negative feedback loop composed of transistors between the internal node of the bandgap reference source and ground through a low-frequency enhancement module, thereby increasing the equivalent impedance from the power supply to ground, thereby weakening the coupling effect of the power supply voltage ripple on the reference voltage and improving the PSRR of the LDO in the low-frequency band. This invention uses a cascaded PMOS and NMOS mirror structure to form a current mirror unit. The reference current is mirrored multiple times and then used as the sampling current of the ripple sampling unit. By adjusting the width-to-length ratio of the transistors in the current mirror unit, the sampling current can be precisely controlled, ensuring that the internal MOS transistors operate in the micro-current state required to generate high equivalent impedance, thus ensuring the stability of the ripple sampling characteristics and avoiding the direct impact of wide-range changes in power supply voltage. This invention replaces the traditional large-value physical resistor as the sampling unit with a pseudoresistor structure composed of multiple MOS transistors. By controlling the pseudoresistor structure to operate in a high-impedance state under sampling current bias, and in conjunction with capacitor C0, an extremely low sampling filter cutoff frequency can be achieved. Compared with on-chip integrated resistors that achieve the same resistance value, the pseudoresistor structure consumes only a very small chip area and has the flexibility to adjust the resistance value by sampling current, achieving an extremely high equivalent resistance value. This invention uses a ripple amplification unit to amplify the extracted ripple and inject it into the gate of the power transistor, making it in phase with the ripple directly connected to the power supply. At the same time, it receives the DC voltage regulation control signal output by the error amplifier EA. The two signals cancel each other out in the output current of the power transistor, thereby significantly attenuating the power supply ripple appearing on the output voltage and improving the power supply rejection ratio of the entire LDO in the mid-to-high frequency range. Attached Figure Description

[0020] Figure 1 This is a structural block diagram of a linear voltage regulator employing ripple suppression and impedance enhancement according to Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the structure of the high-frequency enhancement module in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the pseudoresistor structure according to Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the bandgap reference source and low-frequency enhancement module according to Embodiment 1 of the present invention; Figure 5 This is a diagram showing the power rejection ratio of a traditional LDO. Figure 6 This is a power supply rejection ratio (PSRR) effect diagram of LDO in Embodiment 1 of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments: Example 1 like Figure 1 Specifically, a linear regulator employing ripple suppression and impedance enhancement is disclosed, comprising a bandgap reference source, a low-frequency enhancement module, an error amplifier EA, a power transistor MP, a mid-to-high frequency enhancement module, and a resistive feedback module. The input terminal of the bandgap reference source is connected to an external voltage source Vin, the output terminal Vref of the bandgap reference source is connected to the non-inverting input terminal of the error amplifier EA, the inverting input terminal of the error amplifier EA is connected to the output terminal of the resistive feedback module, the output terminal of the error amplifier EA is connected to the mid-to-high frequency enhancement module, and the two ends of the low-frequency enhancement module are connected to the feedback loop of the bandgap reference source. The mid-to-high frequency enhancement module includes a current mirror unit, a ripple sampling unit, and a ripple amplification unit connected in sequence; the input terminal of the current mirror unit is connected to an external voltage source Vin, the output terminal of the injected ripple amplification unit is connected to the gate of the power transistor MP, the source of the power transistor MP is connected to the external voltage source Vin, and the drain of the power transistor MP is connected to the input terminal of the resistor feedback module. The current mirror unit provides sampling current to the ripple sampling unit. The ripple sampling unit samples the power supply ripple signal and injects it into the ripple amplification unit. The extracted ripple is amplified and injected into the power transistor MP to reduce the mid-to-high frequency power supply ripple. Specifically, the ripple sampling unit is a pseudoresistor sampling structure.

[0023] In this embodiment, the bandgap reference is used to provide a reference voltage. The error amplifier EA compares the input reference voltage with the output voltage of the resistor feedback module and injects it into the ripple amplification unit. The current mirror unit provides a sampling current to the ripple sampling unit. The ripple sampling unit samples the power supply ripple signal and injects it into the ripple amplification unit. The output terminal of the ripple amplification unit controls the gate terminal of the power transistor to reduce the mid-to-high frequency power supply ripple, thereby controlling the output voltage.

[0024] Furthermore, the components of the linear regulator are further described: like Figure 4 As shown, the bandgap reference source includes an operational amplifier amp1, a current mirror, a pair of bipolar transistors, and voltage divider resistors. Transistors MP9 and MP10, operational amplifier amp1, transistor PNP1, transistor PNP2, and resistors R5-R11 are also included. The sources of transistors MP9 and MP10 are both connected to an external voltage source Vin, and the gates of transistors MP9 and MP10 are connected together at the connection point, denoted as node Vg1. Figure 4 As shown, transistors MP9 and MP10 constitute the internal current mirror structure of the bandgap reference source.

[0025] The drain of transistor MP9 is connected to one end of resistor R5, and the other end of resistor R5 is connected to the emitter of transistor PNP1. The connection point is denoted as node Vg2. The base and collector of transistor PNP1 are both grounded. Resistors R10 and R11 are connected in series. The non-series end of resistor R10 is connected to the drain of transistor MP9, and the non-series end of resistor R11 is grounded. The drain of transistor MP10 is connected to one end of resistor R6, and the other end of resistor R6 is connected to one end of resistor R7. The connection point is denoted as node Vg3. The other end of resistor R7 is connected to the emitter of transistor PNP2. The base and collector of transistor PNP2 are both grounded. Resistors R8 and R9 are connected in series. The non-series end of resistor R8 is connected to the drain of transistor MP10, and the non-series end of resistor R9 is grounded. The non-inverting input of the operational amplifier amp1 is connected to node Vg2, and the inverting input is connected to node Vg3.

[0026] In this embodiment, transistors PNP1 and PNP2 are bipolar transistors. Figure 4 As shown, transistors PNP1 and PNP2 form a bipolar transistor pair structure, and resistors R5~R11 act as voltage divider resistors.

[0027] like Figure 4 As shown, the low-frequency enhancement module includes transistor MP1 and transistor MN1; the drain and gate of transistor MP1 are connected, the gate of transistor MP1 is connected to node Vg1 of the bandgap reference source, and the source of transistor MP1 is connected to an external voltage source Vin. The source of transistor MN1 is connected to the drain of transistor MP1, the gate of transistor MN1 is connected to the output of operational amplifier amp1, and the drain of transistor MN1 is grounded.

[0028] In this embodiment, transistor MP1 is specifically a PMOS transistor, and transistor MN1 is specifically an NMOS transistor. The power supply rejection ratio of the LDO at low frequencies is improved by increasing the impedance from the power supply to ground.

[0029] Specifically, in the bandgap reference source, there is a parasitic path from the external voltage source Vin to the internal node Vg1. The path from node Vg1 to ground is mainly through the internal transistor and other paths. The internal impedance is limited, and ripple is easily coupled in. The ripple of Vin will generate ripple disturbance on node Vg1 through the limited internal impedance, thus affecting the output reference voltage Vref.

[0030] Therefore, this embodiment introduces a low-frequency enhancement structure, introducing a negative feedback loop composed of transistors MP1 and MN1 between the internal node Vg1 of the bandgap reference source and ground. When Vg1 attempts to change due to Vin ripple, the low-frequency enhancement module generates a canceling current, thereby significantly increasing the AC impedance to ground from Vg1 to transistor MN1, making it more difficult for Vin ripple to disturb node Vg1, thus making the generated reference voltage Vref purer. This significantly improves the AC small-signal impedance of node Vg1 to ground, thereby weakening the coupling effect of low-frequency power supply voltage ripple on the reference voltage, and ultimately improving the PSRR of the entire LDO in the low-frequency range.

[0031] When ripple occurs in Vin, causing the potential of node Vg1 to rise, the source voltage of MN1 will experience a voltage increase trend. Since the gate voltage of MN1 is provided by the output of operational amplifier amp1, this will lead to a decrease in the gate-source voltage of MN1. This means that the channel current of MN1 decreases, indicating a weakened ability to draw current from node Vg1. This counteracts the voltage rise caused by coupling ripple at node Vg1. Therefore, the negative feedback provided by the low-frequency enhancement module significantly increases the equivalent output impedance from power supply to ground.

[0032] like Figure 1 , Figure 4 As shown, the low-frequency enhancement structure consists of transistors MP1 and MN1, which are inserted into the feedback loop to increase impedance and improve the power supply rejection ratio (PSRR) of the bandgap reference at low frequencies, thereby enhancing the gain performance of the circuit in the low-frequency signal band. Specifically, the drain and gate of transistor MP1 are connected, the gate of transistor MP1 is connected to node Vg1 of the bandgap reference source, and the source is connected to an external voltage source Vin. The PSRR of node Vg1 is... Using the following logical representation:

[0033] in, For the transconductance of transistor MN1, This is the drain-source resistance of transistor MP1.

[0034] Furthermore, such as Figure 2 , Figure 3As shown, the mid-to-high frequency enhancement module includes a current mirror unit, a ripple sampling unit, and a ripple amplification unit connected in sequence. The current mirror unit includes a current source, transistor MP2, transistor MP3, transistor MN2, transistor MN3, and transistor MP4. The drain of transistor MP2 is connected to the current source, the source of transistor MP2 is connected to an external voltage source Vin, and the gate of transistor MP2 is connected to its drain. The drain of transistor MP3 is connected to the drain of transistor MN2, the source of transistor MP3 is connected to an external voltage source Vin, and the gate of transistor MP3 is connected to the gate of transistor MP2. The drain of transistor MN2 is connected to the drain of transistor MP3, the source of transistor MN2 is grounded, and the gate of transistor MN2 is connected to its drain. The drain of transistor MN3 is connected to the drain of transistor MP4, the source of transistor MN3 is grounded, and the gate of transistor MN3 is connected to the gate of transistor MN2. The source of transistor MP4 is connected to an external voltage source Vin, and the gate of transistor MP4 is connected to its drain.

[0035] In this embodiment, transistors MP2 and MP3 are specifically PMOS transistors, and transistors MN2 and MN3 are specifically NMOS transistors. Since the size ratio of transistors in the current mirror directly affects the current replication accuracy, in a preferred embodiment, the width-to-length ratio W / L of transistor MP2 is four times that of transistor MP3, and the width-to-length ratio W / L of transistor MN2 is four times that of transistor MN3.

[0036] Specifically, firstly, since the gate and drain of transistor MP2 are shorted, the current source inside the current mirror unit flows through transistor MP2 to determine the gate-source voltage of transistor MP2. Since transistor MP3 is connected to the gate of transistor MP2 and the source of both are connected to the external voltage source Vin, based on the transistor characteristics, transistor MP3 mirrors the current of transistor MP2, generating a current proportional to that of transistor MP2. Next, based on the same principle, transistor MN3 mirrors the current of transistor MN2. By setting the width-to-length ratio W / L of the transistor, the bias current flowing through transistor MN3 can be precisely set, and this bias current will serve as the sampling current of the ripple sampling unit. This sampling current can force the transistor of the ripple sampling unit to operate in the deep linear / subthreshold region, forming a high-impedance characteristic.

[0037] The ripple sampling unit includes transistors MN4, MP5, and MP6, resistor R4, and capacitor C0. The drain of transistor MN4 is connected to one end of resistor R4, and the other end of resistor R4 is connected to the drain of transistor MP5. The source of transistor MN4 is grounded, and the gate of transistor MN4 is connected to the gate of transistor MN3. The gate of transistor MP5 is connected to the drain of transistor MN4, and the connection point is denoted as node V3. The drain of transistor MP5 is connected to the gate of transistor MP6, and the connection point is denoted as node V4. The source of transistor MP5 is connected to the gate of transistor MP4. The source of transistor MP6 is connected to the gate of transistor MP4, and the drain of transistor MP6 is connected to one end of capacitor C0, with the other end of capacitor C0 grounded.

[0038] In this embodiment, the ripple sampling unit is composed of a pseudoresistor structure and a capacitor C0. The sampling current is provided by a current mirror unit. The pseudoresistor structure, as the core functional unit of the ripple sampling unit, is not a single component, but a composite pseudoresistor structure composed of transistors MN4, MP5, MP6, and resistor R4. Specifically, transistor MN4 plays a switching and conduction control role in the pseudoresistor structure: the drain pin of transistor MN4 is electrically connected to one end of resistor R4 to realize current and signal transmission between them; the source pin of transistor MN4 is directly connected to the ground potential of the circuit system, providing a stable potential reference point for the branch and ensuring the stability of the circuit operation; the gate pin of transistor MN4 is interconnected with the gate pin of another transistor MN3 to form a common gate connection structure; by coupling the gates of the two transistors, transistor MN4 can synchronously control its operating state according to the gate control signal of transistor MN3, thereby achieving precise control of the entire pseudoresistor structure's operating mode.

[0039] In this embodiment, resistor R4 serves as a key passive component in the pseudoresistor structure. The two ends of resistor R4 correspond to different circuit connection nodes V3 and V4, forming a complete current path. Resistor R4 receives the current signal from the MN4 branch and establishes an electrical connection with the drain pin of transistor MP5, transmitting the current signal passing through R4 to the branch containing transistor MP5 and subsequent branches. The gate pin of transistor MP5 is directly coupled to node V3, and its drain pin is directly coupled to node V4. The gate pin of transistor MP6 is also directly coupled to node V4. Capacitor C0 forms an energy storage structure with one end electrically connected to the gate pin of transistor MP7 and the other end connected to circuit ground (GND). The sampling frequency of the ripple sampling unit composed of the pseudoresistor structure and capacitor C0 is... Using the following logical representation:

[0040] in, Let R4 be the resistance value. Let C0 be the capacitance value.

[0041] In this embodiment, transistors MP5 and MP6 are specifically PMOS transistors, and transistor MN4 is specifically an NMOS transistor; in a preferred embodiment, the width-to-length ratio (W / L) of transistor MP6 is 1:400, and the width-to-length ratio (W / L) of transistor MP5 is 1:180.

[0042] Specifically, in traditional feedforward ripple cancellation (FFRC) technology, sampling power supply ripple typically uses a large resistor and a capacitor to form an RC low-pass filter. Accurate sampling of low-frequency ripple requires an extremely large RC time constant. In integrated circuits, realizing a precision resistor of tens or even hundreds of megohms requires a huge chip area.

[0043] In this embodiment, by utilizing the high channel resistance characteristic of transistors under a specific bias current, the same high equivalent resistance and extremely low cutoff frequency can be achieved by using only a few small-sized MOS transistors operating in the subthreshold region. Specifically, firstly, a small bias current is provided to transistor MN4 through the current mirror unit. Under this current, transistor MN4 is in the subthreshold region, where the channel resistance between the drain and source of transistor MN4 is extremely high. Secondly, the gates of transistors MP5 and MP6, connected to nodes V3 and V4 respectively, form an internal feedback branch, maintaining a stable and extremely high equivalent dynamic resistance as a "pseudoresistance" over a wide voltage range. The pseudoresistance structure is located between transistors MP4 and MP7, and the gate voltage difference between them is extremely small, ensuring that the pseudoresistance remains in the linear range. Next, the equivalent dynamic resistance and capacitor C0 form a low-pass filter with an extremely low cutoff frequency. After the ripple of the external voltage source Vin passes through the low-pass filter, the low-frequency components are extracted and sent to the ripple amplification unit. Finally, the extracted ripple is amplified and injected into the gate of the power transistor, in phase with the ripple of the power transistor directly connected to the power supply, thereby reducing the influence of power supply ripple and improving the power supply rejection ratio of the entire LDO in the mid-to-high frequency range.

[0044] Furthermore, the current flowing through the pseudoresistive structure generates a voltage drop through resistor R4, which can be represented by the following logic:

[0045] in, Drain current, The current constant in the subthreshold region. Gate-source voltage, Threshold voltage, The non-ideal factor is set to 1.5. Thermoelectric voltage, This is the drain-source voltage.

[0046] The equivalent impedance of a pseudoresistor is represented using the following logic:

[0047] in, It is a small-signal impedance.

[0048] The ripple amplification unit includes transistor MP7 and transistor MP8; the gate of transistor MP7 is connected to the drain of transistor MP6, the source of transistor MP7 is connected to an external voltage source Vin, and the drain of transistor MP7 is connected to the source of transistor MP8. The connection point is denoted as node V2. Node V2 serves as the output terminal of the mid-to-high frequency enhancement module and is connected to the gate of power transistor MP; the gate of transistor MP8 is connected to the output terminal of error amplifier EA, and the drain of transistor MP8 is grounded.

[0049] In this embodiment, the ripple amplification unit is an important component of the mid-to-high frequency enhancement module, consisting of core components transistors MP7 and MP8, and their key node V2.

[0050] In this embodiment, both transistors MP7 and MP8 are PMOS transistors, and the width-to-length ratio (W / L) of transistors MP7 and MP8 is the same to ensure that the two transistors have consistent current drive characteristics.

[0051] like Figure 2 As shown, the non-inverting input of the error amplifier EA is connected to the output Vref of the bandgap reference source to receive the reference voltage output by the bandgap reference source. The inverting input is connected to node V1 in the resistor feedback module to receive the voltage feedback value from the regulator output. The output of the error amplifier EA is connected to the gate of MP8, and the comparison result of the above two is transmitted to the ripple amplification unit.

[0052] Specifically, the ripple signal sampled by the ripple sampling unit is output from the drain of transistor MP6 and input to the gate of transistor MP7. The gate of transistor MP8 is controlled by the output of error amplifier EA. Transistors MP7 and MP8 form a gain stage, and node V2 is directly connected to the gate of power transistor MP. Therefore, the potential of node V2 simultaneously includes the DC voltage regulation control signal output from error amplifier EA in the main loop and the AC ripple cancellation signal from the feedforward path. This causes the two signals to cancel each other out in the output current of the power transistor, thereby significantly attenuating the power supply ripple appearing on the output voltage Vout and improving the PSRR in the mid-to-high frequency range.

[0053] Furthermore, such as Figures 2-3As shown, the resistor feedback module includes resistors R1 and R2 connected in series. The non-series terminal of resistor R2 is connected to the drain of power transistor MP, and the non-series terminal of resistor R1 is grounded. The connection point of resistors R1 and R2 is denoted as node V1. The inverting input terminal of error amplifier EA is connected to node V1.

[0054] Furthermore, the linear regulator also includes a resistor R3 and a capacitor C1; the drain of the power transistor MP serves as the output terminal of the linear regulator, the drain of the power transistor MP is connected to one end of the capacitor C1, the other end of the capacitor C1 is grounded, one end of the resistor R3 is connected to the drain of the power transistor MP, and the other end of the resistor R3 is grounded.

[0055] like Figure 5 , Figure 6 As shown, based on the high PSRR linear regulator structure proposed in this invention, which employs ripple suppression and impedance enhancement, a bandgap reference source is used to generate a voltage signal, which is then connected to a low-frequency enhancement module via a voltage divider structure. This enhances the overall source-to-ground impedance, thereby improving the power supply rejection ratio (PSRR) at low frequencies. A mid-to-high frequency enhancement module, including a current mirror, a pseudoresistor, and a fixed feedforward ripple elimination structure (fixed FFRC structure), is used. The pseudoresistor structure adjusts the voltage within the circuit, and together with capacitor C0, forms a sampling filter structure to collect power supply ripple. After amplification by the fixed FFRC structure, the ripple is injected into the gate of the power transistor PM, where it is eliminated along with the power supply ripple from the third path. Compared to the power supply rejection ratio of a traditional LDO, this invention improves the power supply rejection ratio from 67dB to 88dB at 100Hz; from 65dB to 73dB at 1kHz; and from 50dB to 53dB at 10kHz.

[0056] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A linear voltage regulator employing ripple suppression and impedance enhancement, characterized in that, It includes a bandgap reference source, a low-frequency enhancement module, an error amplifier EA, a power transistor MP, a mid-to-high frequency enhancement module, and a resistive feedback module; the input terminal of the bandgap reference source is connected to an external voltage source Vin, the output terminal Vref of the bandgap reference source is connected to the non-inverting input terminal of the error amplifier EA, the inverting input terminal of the error amplifier EA is connected to the output terminal of the resistive feedback module, the output terminal of the error amplifier EA is connected to the mid-to-high frequency enhancement module, and the two ends of the low-frequency enhancement module are connected to the feedback loop of the bandgap reference source; The mid-to-high frequency enhancement module includes a current mirror unit, a ripple sampling unit, and a ripple amplification unit connected in sequence; the input terminal of the current mirror unit is connected to an external voltage source Vin, the output terminal of the injected ripple amplification unit is connected to the gate of the power transistor MP, the source of the power transistor MP is connected to the external voltage source Vin, and the drain of the power transistor MP is connected to the input terminal of the resistor feedback module. The current mirror unit provides sampling current to the ripple sampling unit. The ripple sampling unit samples the power supply ripple signal and injects it into the ripple amplification unit. The extracted ripple is amplified and injected into the power transistor MP to reduce the mid-to-high frequency power supply ripple. Specifically, the ripple sampling unit is a pseudoresistor sampling structure.

2. A linear voltage regulator employing ripple suppression and impedance enhancement according to claim 1, characterized in that, The bandgap reference source includes transistor MP9, transistor MP10, operational amplifier amp1, transistor PNP1, transistor PNP2, and resistors R5~R11; the sources of transistors MP9 and MP10 are both connected to an external voltage source Vin, and the gates of transistors MP9 and MP10 are connected together, with the connection point denoted as node Vg1. The drain of transistor MP9 is connected to one end of resistor R5, and the other end of resistor R5 is connected to the emitter of transistor PNP1. The connection point is denoted as node Vg2. The base and collector of transistor PNP1 are both grounded. Resistors R10 and R11 are connected in series. The non-series end of resistor R10 is connected to the drain of transistor MP9, and the non-series end of resistor R11 is grounded. The drain of transistor MP10 is connected to one end of resistor R6, and the other end of resistor R6 is connected to one end of resistor R7. The connection point is denoted as node Vg3. The other end of resistor R7 is connected to the emitter of transistor PNP2. The base and collector of transistor PNP2 are both grounded. Resistors R8 and R9 are connected in series. The non-series end of resistor R8 is connected to the drain of transistor MP10, and the non-series end of resistor R9 is grounded. The non-inverting input of the operational amplifier amp1 is connected to node Vg2, and the inverting input is connected to node Vg3.

3. A linear voltage regulator employing ripple suppression and impedance enhancement according to claim 2, characterized in that, The low-frequency enhancement module includes transistor MP1 and transistor MN1; the drain and gate of transistor MP1 are connected, the gate of transistor MP1 is connected to node Vg1 of the bandgap reference source, and the source of transistor MP1 is connected to an external voltage source Vin; the source of transistor MN1 is connected to the drain of transistor MP1, the gate of transistor MN1 is connected to the output terminal of operational amplifier amp1, and the drain of transistor MN1 is grounded.

4. A linear voltage regulator employing ripple suppression and impedance enhancement according to claim 1, characterized in that, The current mirror unit includes a current source, transistor MP2, transistor MP3, transistor MN2, transistor MN3, and transistor MP4; the drain of transistor MP2 is connected to the current source, the source of transistor MP2 is connected to an external voltage source Vin, and the gate of transistor MP2 is connected to the drain. The drain of transistor MP3 is connected to the drain of transistor MN2, the source of transistor MP3 is connected to the external voltage source Vin, and the gate of transistor MP3 is connected to the gate of transistor MP2; the drain of transistor MN2 is connected to the drain of transistor MP3, the source of transistor MN2 is grounded, and the gate of transistor MN2 is connected to the drain of transistor MN2; the drain of transistor MN3 is connected to the drain of transistor MP4, the source of transistor MN3 is grounded, and the gate of transistor MN3 is connected to the gate of transistor MN2. The source of transistor MP4 is connected to an external voltage source Vin, and the gate of transistor MP4 is connected to the drain of transistor MP4.

5. A linear voltage regulator employing ripple suppression and impedance enhancement according to claim 4, characterized in that, The ripple sampling unit includes transistors MN4, MP5, MP6, resistor R4, and capacitor C0. The drain of transistor MN4 is connected to one end of resistor R4, the other end of resistor R4 is connected to the drain of transistor MP5, the source of transistor MN4 is grounded, and the gate of transistor MN4 is connected to the gate of transistor MN3. The gate of transistor MP5 is connected to the drain of transistor MN4, and the connection point is denoted as node V3. The drain of transistor MP5 is connected to the gate of transistor MP6, and the connection point is denoted as node V4. The source of transistor MP5 is connected to the gate of transistor MP4. The source of transistor MP6 is connected to the gate of transistor MP4, the drain of transistor MP6 is connected to one end of capacitor C0, and the other end of capacitor C0 is grounded.

6. A linear voltage regulator employing ripple suppression and impedance enhancement according to claim 5, characterized in that, The sampling frequency of the ripple sampling unit Using the following logical representation: in, Let R4 be the resistance value. Let C0 be the capacitance value.

7. A linear voltage regulator employing ripple suppression and impedance enhancement according to claim 5, characterized in that, The ripple amplification unit includes transistor MP7 and transistor MP8; the gate of transistor MP7 is connected to the drain of transistor MP6, the source of transistor MP7 is connected to an external voltage source Vin, and the drain of transistor MP7 is connected to the source of transistor MP8. The connection point is denoted as node V2. Node V2 serves as the output terminal of the mid-to-high frequency enhancement module and is connected to the gate of power transistor MP; the gate of transistor MP8 is connected to the output terminal of error amplifier EA, and the drain of transistor MP8 is grounded.

8. A linear voltage regulator employing ripple suppression and impedance enhancement according to claim 7, characterized in that, In the current mirror unit, the width-to-length ratio W / L of transistor MP2 is proportional to the width-to-length ratio W / L of transistor MP3, and the width-to-length ratio W / L of transistor MN2 is proportional to the width-to-length ratio W / L of transistor MN3. In the ripple amplification unit, transistors MP7 and MP8 have the same width-to-length ratio (W / L).

9. A linear voltage regulator employing ripple suppression and impedance enhancement according to claim 1, characterized in that, The resistance feedback module includes resistors R1 and R2 connected in series. The non-series terminal of resistor R2 is connected to the drain of power transistor MP, and the non-series terminal of resistor R1 is grounded. The connection point of resistors R1 and R2 is denoted as node V1. The inverting input terminal of error amplifier EA is connected to node V1.

10. A linear voltage regulator employing ripple suppression and impedance enhancement according to claim 1, characterized in that, The linear regulator also includes a resistor R3 and a capacitor C1; the drain of the power transistor MP serves as the output terminal of the linear regulator, the drain of the power transistor MP is connected to one end of the capacitor C1, the other end of the capacitor C1 is grounded, one end of the resistor R3 is connected to the drain of the power transistor MP, and the other end of the resistor R3 is grounded.

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