GPU multi-thread parallel Hawk algorithm acceleration method

Abstract

The invention provides a Hawk algorithm acceleration method based on GPU (Graphics Processing Unit) multi-thread parallel. The GPU multi-thread parallel-based Hawk algorithm acceleration method comprises the following steps of (1) thread resource division and task mapping; (2) kernel fusion and throughput peak detection; (3) NTT / iNTT parallel reconstruction and memory access optimization are carried out; and (4) carrying out FFT / iFFT structured parallel optimization and butterfly operator fusion. According to the method, a coarse-grained parallel butterfly operator execution mode which does not need complex address calculation, does not need shared memory synchronization and does not compete among threads is realized, and the throughput efficiency on the GPU is greatly improved; meanwhile, a parallel execution framework is unified in forward and reverse transformation of the FFT / NTT, and overall recovery can be completed only by using a corresponding reverse twiddle factor and performing simple normalization processing at the tail end in the reverse transformation.

Description

Technical Field

[0001] This invention relates to the field of high-performance computing technology, specifically to a method for accelerating the Hawk algorithm based on GPU multi-threaded parallelism. Background Technology

[0002] With the accelerated evolution of quantum computing technology, the mathematical problems upon which traditional public key infrastructure (PKI) relies are facing unprecedented security threats. In the foreseeable future, if large-scale quantum computers become a reality, classical cryptographic algorithms based on problems such as integer factorization and elliptic curve discrete logarithms, such as RSA, ECDSA, and ECDH, will lose their security in the face of quantum algorithms. This will not only impact internet communication security systems but also threaten data integrity and trusted execution in critical application scenarios such as government affairs, finance, and blockchain. Therefore, developing post-quantum digital signature algorithms that can withstand quantum attacks has become an important direction for international cryptographic research.

[0003] In recent years, lattice-based digital signature schemes (such as SIS and LWE) have attracted widespread attention due to their clear theoretical foundation for quantum security, as well as their good parallelism, scalability, and implementation efficiency. Among them, the post-quantum cryptography (PQC) standardization process led by the National Institute of Standards and Technology (NIST) has promoted in-depth evaluation and standardization of representative lattice signature schemes such as Dilithium and Falcon, making lattice-based digital signatures a core component of post-quantum systems. However, in various practical deployment scenarios such as low-power devices, cloud service platforms, and high-density authentication systems, lattice signatures still face key challenges such as high computational complexity, complex key structures, and insufficient concurrency capabilities.

[0004] Hawk's signature algorithm, a high-efficiency lattice digital signature scheme proposed in recent years, is based on Learning-by-Error (LWE) and lattice function structures. By introducing specific sampling mechanisms, vector transformation structures, decoding strategies, and frequency domain acceleration techniques, it achieves a good balance between signature size, signing speed, and security. Compared to traditional lattice signature schemes, Hawk introduces high-frequency calls to Fast Number Theory Transform (NTT / iNTT) and Fast Fourier Transform (FFT / iFFT) structures in the signature generation and key generation stages, giving the algorithm inherent parallelization potential. However, due to its large number of multi-dimensional, multi-round convolutional calculations, vector multiplication and accumulation operations, modulus-to-digital transformation steps, and costly sampling components, Hawk's performance is still limited by the processor's serial computing architecture when facing large-scale signature tasks or high-concurrency verification requests, thus affecting the overall system throughput and response latency.

[0005] With the maturity of GPU computing architecture and the widespread application of general-purpose programming frameworks such as CUDA, GPUs have become an important platform for accelerating cryptographic algorithms. Modern GPUs integrate a large number of stream processors and parallel execution units, providing orders of magnitude higher parallel computing power than CPUs at lower power consumption. Their excellent thread scheduling model and multi-level memory structure can fully adapt to the characteristics of Hawk algorithms, such as multi-vector, multi-stage pipelined computation, and intensive transformation operations. At the same time, operations such as NTT / iNTT, FFT / iFFT, lattice sampling, and polynomial computation in Hawk algorithms inherently possess SIMD and parallelism, making GPU acceleration significantly feasible and advantageous.

[0006] However, directly porting the Hawk signature algorithm to a GPU environment often fails to achieve the expected speedup. The algorithm's internal computational modules contain complex data dependencies, and some transformations trigger cross-level synchronization interactions. Furthermore, the dependencies of various sub-operations on thread scheduling, memory access mechanisms, shared memory layout, and local caching vary significantly. Especially in frequently invoked critical computational chains, without tailored thread orchestration, memory access mode restructuring, and pipeline modifications for the GPU's underlying hardware, thread divergence and memory conflicts can easily arise, leading to a decrease in execution efficiency instead of an increase. Additionally, Hawk's original NTT / FFT architecture requires a complete overhaul to accommodate GPU thread block partitioning, warp scheduling, and vectorized data access characteristics. In summary, there is still considerable room for improvement in adapting the Hawk algorithm for GPU parallelization.

[0007] The patent document with authorization announcement number "CN117473212B" proposes an NTT algorithm GPU acceleration scheme covering devices, equipment, and storage media. This scheme introduces a hybrid execution mechanism based on threshold judgment: when the modulus does not exceed a set threshold, the rotation factor matrix is ​​decomposed and matrix multiplication is performed; only when the modulus exceeds the limit or the video memory is tight does it switch to multi-threaded butterfly operation. This conditional restriction narrows its practical scope; moreover, this technical solution does not provide a specific logic reuse strategy for the inverse transformation stage.

[0008] The patent application with publication number "CN117633418A" relates to a technique for accelerating multidimensional fast Fourier transforms (FFTs) by relying on matrix computation. Its core lies in mapping multidimensional FFTs to matrix multiplication tasks, leveraging the matrix cores of GPUs to improve efficiency. However, this requires constructing DFT matrices and forces data to undergo complex explicit migrations and format conversions between global video memory, registers, and shared memory. Simultaneously, the host machine needs continuous intervention to manage data copying and resource reclamation, making the overall process extremely complex. Furthermore, this method focuses on using multithreading to execute matrix element-wise multiplication and matrix multiplication step-by-step, resulting in overly fine parallel granularity, which is essentially more suited to single, ultra-large-scale FFT tasks.

[0009] Patent application publication number "CN119939618A" explores a homomorphic encryption speed-up method that integrates polynomial multiplication improvement and GPU multithreaded mapping. This technology mainly serves fully homomorphic encryption scenarios, and its modification focuses on reorganizing the nested loop hierarchy and pre-computing and caching unit primitive roots. In essence, this scheme emphasizes improving homomorphic multiplication performance through primitive root preprocessing under the BFV mechanism.

[0010] Therefore, how to combine the structural characteristics of the Hawk algorithm and fully utilize the massive parallel capabilities of GPUs to achieve efficient acceleration of the Hawk signature algorithm through thread-level parallelization, memory access optimization, and NTT / iNTT and FFT / iFFT kernel reconstruction has become a key issue in promoting the deployment of digital signatures in cloud services, blockchain networks, and edge device trust scenarios. Meanwhile, how to solve problems such as thread resource allocation, kernel fusion, and peak throughput under coarse-grained parallel strategies; the large computational load and complex access patterns of the NTT / iNTT transformation in the Hawk algorithm, which easily leads to inefficiency in a GPU parallel environment; and the performance bottleneck caused by the complex FFT / iFFT transformation calculation method in the signature process under a GPU parallel environment are problems that this invention urgently needs to solve. Summary of the Invention

[0011] The purpose of this invention is to propose a GPU-based multi-threaded parallel Hawk algorithm acceleration method to significantly improve the throughput and operating efficiency of its signature generation and key generation stages, providing a solid cryptographic foundation for large-scale trusted computing systems in the quantum era.

[0012] To achieve the above objectives, the technical solution adopted by this invention is as follows: This invention provides a method for accelerating the Hawk algorithm based on GPU multi-threaded parallelism, comprising the following steps:

[0013] (1) Thread resource allocation and task mapping;

[0014] (2) Kernel fusion and peak throughput detection;

[0015] (3) Parallelization and memory access optimization of NTT / iNTT;

[0016] (4) FFT / iFFT structured parallelization optimization and butterfly operator fusion.

[0017] As a further improvement, the thread resource allocation and task mapping in step (1) are implemented in a coarse-grained manner. The present invention adopts a coarse-grained parallel scheme, allocating independent video memory space for each thread according to the number of each thread, and then mapping the complete computing process of Hawk onto the GPU, with each thread independently executing a complete task.

[0018] As a further improvement, the peak throughput detection in step (2) determines the peak throughput by setting a reasonable number of threads in the GPU's stream processor specifications. Furthermore, as... Figure 3 As shown, this process further integrates a kernel fusion strategy: through the synergy of kernel fusion and throughput peak detection, the number of global functions is compressed to the maximum extent, and core logic such as key generation (HAWK_KeyGen), signing (HAWK_Sign), and verification (HAWK_Verify) is reconstructed into device functions called by global functions; it also includes kernel fusion, which, through kernel fusion and throughput peak detection, minimizes the number of global functions and rewrites most functions into device functions, writes intermediate computation results into thread registers to minimize data exchange between the host and device, and allocates appropriate thread parameters and obtains the parameter values ​​of throughput peaks according to the GPU's stream processor architecture.

[0019] As a further improvement, the NTT / iNTT parallelization reconstruction and memory access optimization in step (3) are implemented through butterfly operations of forward and inverse number theory transformations. The NTT / iNTT parallelization reconstruction and memory access optimization strategy is to transform the original global traversal form based on triple nested loops into a hierarchical butterfly structure, thus reconstructing the computation process from a breadth-based scanning to a depth-based exploration mode that advances along the hierarchy. Through this structured rearrangement, each thread can independently execute the entire process in a coarse-grained manner, reducing the overall complexity from Reduced to This makes the global memory access pattern more continuous and regular. The inverse transform only requires switching the direction of the rotation factor and finally multiplying by... This allows the same computing framework to be reused to achieve a unified, low-overhead, and easily parallelizable GPU number theory transformation process.

[0020] As a further improvement, the fusion of FFT / iFFT structured parallelization optimization and butterfly operator in step (4) is achieved through forward and inverse fast Fourier transform optimization. The fusion strategy of FFT / iFFT structured parallelization optimization and butterfly operator achieves a consistent data flow on global memory by executing the entire butterfly stage through coarse-grained thread blocks. Moreover, each layer is independently scheduled and threads process continuous butterfly units in batches, avoiding frequent cross-layer synchronization and complex data rearrangement. Furthermore, the butterfly operators in the same layer are fused to reduce the number of global memory accesses and maintain the overall parallelism of the algorithm.

[0021] As a further improvement, the coarse-grained approach is based on multi-threaded parallelism, and is determined according to the thread number. The calculations performed are as follows:

[0022] ;

[0023] in, This indicates the number of the thread block in which the current thread resides. This indicates the number of threads in each thread block. This indicates the local number of the thread within the thread block.

[0024] As a further improvement, specific methods for implementing butterfly operations of positive and inverse number theory transformations include:

[0025] Employing a layered butterfly structure, in each layer of butterfly operations, the algorithm groups the input sequence into even-numbered and odd-numbered items, performs weighted combinations using pre-calculated twiddle factors, and replaces the original complex exponentiation operations with addition, subtraction, and multiplication operations, thus reducing the computational complexity from... Reduce to This reduces the overhead of redundant calculations;

[0026] make This is the current butterfly layer number. This represents the current length of the butterfly-shaped layer. It has a butterfly-shaped span. This is the current layer span, used to control the butterfly index stepping.

[0027] As a further improvement, the layered butterfly structure includes the original butterfly pair. The calculation is as follows:

[0028]

[0029] in, Represents the corresponding number in the array One element, This represents a temporary variable representing the butterfly effect on the original coefficients. Indicates when The frequency domain result obtained at time i.e., the input sequence at the t-th time... Transformation values ​​on discrete frequency components; current rotation factor Represented as:

[0030] ;

[0031] in, The rotation factor table stores the root power of unit required for NTT / iNTT. Indicates the index of the current sub-block. The current layer offset is used to calculate the rotation factor in... Indexes in the table;

[0032] This linear index design enables butterfly pairs Arranged contiguously in memory, each butterfly block is represented as follows:

[0033]

[0034] After index reconstruction is complete, all NTT calculations can be transformed into:

[0035]

[0036] The Butterfly operation's accumulation model consists of fixed-length odd-even pairs, where a[j] represents the j-th element in the input array. In the Hawk algorithm, it usually represents the j-th coefficient of the polynomial (in NTT, it is a modulo-domain integer, and in FFT, it is a complex sample value).

[0037] As a further improvement, the specific method for optimizing the implementation of forward and inverse fast Fourier transforms is as follows:

[0038] In the Hawk algorithm, polynomial multiplication involves Fast Fourier Transform and Inverse Fourier Transform modules, for a length of... sequence :

[0039] ;

[0040] in, Indicates the input sequence number 1 One sampling point, Represents the output frequency domain coefficients. Represents the rotation factor; for a sequence of length n The inverse transform is shown below:

[0041] ;

[0042] in, This represents the recovered time-domain sequence. Represents the input frequency domain coefficients. is the rotation factor, a positive exponent; j represents the subscript index of the input sequence or polynomial, used to traverse the original data; k represents the index of the frequency domain result after transformation, i.e., the kth frequency component; and n represents the sequence length or the order of the polynomial.

[0043] Compared to the patent with announcement number "CN117473212B", this invention, targeting the characteristics of the Hawk algorithm, uniformly adopts a layered butterfly structure parallel reconstruction scheme, converting the triple loop into a single-index driven recursive model. This eliminates the need for complex matrix splitting and judgment, directly ensuring continuous memory arrangement through linear index design, avoiding the branch prediction overhead and memory fragmentation caused by hybrid strategies. Simultaneously, this invention proposes a system-level optimization combining "coarse-grained parallelism" and "kernel fusion," mapping the complete Hawk algorithm process (including sampling, NTT, convolution, etc.) to independent threads and rewriting most functions as device functions to retain intermediate results in registers. This further eliminates the bottleneck of frequent data exchange between the host and device on top of operator acceleration. Furthermore, the architecture designed in this invention achieves unified forward and inverse transformations; the inverse transformation only requires switching the rotation factor direction and multiplying at the end. This allows for complete reuse of the same computing framework. This structured rearrangement significantly reduces the complexity of GPU kernel code and improves the hit rate of the instruction cache.

[0044] Compared to the patent with publication number "CN117633418A", this invention addresses the characteristics of FFT / iFFT in the Hawk algorithm by employing a layer-anchored butterfly operator fusion strategy. This strategy directly executes consistent data flow operations on global GPU memory, avoiding the additional GPU memory overhead and complex matrix multiplication preprocessing required to construct large DFT matrices. Furthermore, this invention uses a "coarse-grained" parallel strategy, where each thread independently executes a complete Hawk signature or verification task. This eliminates synchronization waits between threads, making it more suitable for improving the throughput of massive small-scale FFT tasks in high-concurrency scenarios. Additionally, this invention utilizes a "throughput peak detection" mechanism to automatically allocate appropriate thread parameters based on the GPU stream processor architecture, enabling highly autonomous computational tasks within the GPU and maximizing the utilization of the stream processor's computing power, achieving an order-of-magnitude performance improvement.

[0045] Compared to the patent with publication number "CN119939618A", this invention targets the Hawk signature algorithm in post-quantum cryptography. Its core challenge lies in the high-frequency sampling and transformation calls. Therefore, this application designs a specific single-index driven linear access model, solving the memory access discontinuity problem caused by cross-layer step size jumps in traditional implementations. This addresses the GPU memory access latency problem more deeply than simple loop optimization. Furthermore, this invention not only optimizes polynomial multiplication but also performs full-process GPU mapping for Hawk algorithm-specific components such as Gaussian sampling and rejection sampling, ensuring overall acceleration of the three stages of key generation, signing, and verification, rather than just accelerating a single multiplication operator. This invention also introduces structured decomposition and real / imaginary part boundary index optimization for complex domain FFT, specifically addressing the bottleneck of complex FFT transformations involved in the Hawk algorithm during signature verification. Finally, it reduces the number of global memory accesses through butterfly operator fusion. Figure 4 As shown, a performance improvement of up to 155%-730% was achieved in the signature verification stage.

[0046] Compared with the prior art, the beneficial effects of the present invention are:

[0047] (1) This invention uses a coarse-grained approach to allocate resources to each thread, enabling it to run the entire process independently. This avoids the frequent thread synchronization and shared memory contention issues caused by traditional fine-grained parallelism. By expanding the workload of a single task and reducing inter-core communication, it effectively improves the computation-to-memory ratio. Under the same hardware conditions, it can fully utilize the GPU's computing resources and global video memory bandwidth, making the overall throughput close to the hardware peak and achieving an order-of-magnitude performance improvement.

[0048] (2) The NTT / iNTT and FFT / iFFT operators in polynomial multiplication were reconstructed at the algorithm level. The original triple loop calculation was rewritten into a hierarchical butterfly structure. After optimization, the butterfly operations in each stage can be executed in parallel and memory access jumps are reduced, significantly reducing latency and improving the overall polynomial transformation throughput. This provides quantifiable performance gains for Hawk key generation and signature verification. The method provided by this invention can effectively improve the calculation speed of key steps in the Hawk algorithm and improve computational performance and throughput. Attached Figure Description

[0049] Figure 1 This is a flowchart of the Hawk algorithm acceleration method based on GPU multi-threaded parallelism in this embodiment;

[0050] Figure 2 This is a schematic diagram of the butterfly operation in this embodiment;

[0051] Figure 3 This is a flowchart of kernel fusion in this embodiment;

[0052] Figure 4This is a performance optimization comparison chart of the Hawk series algorithms based on Nvidia RTX 4090 under different thread scales (throughput unit: times / second). Detailed Implementation

[0053] The following is in conjunction with the appendix Figure 1 The present invention will be further described in detail with reference to specific embodiments:

[0054] (1) Coarse-grained implementation scheme, kernel fusion and peak throughput detection: The Hawk algorithm GPU acceleration scheme provided by this invention takes multi-threaded parallelism as its core, and calculates the peak throughput based on the number of each thread. The calculation method is as follows:

[0055] ;

[0056] in, This indicates the number of the thread block in which the current thread resides. This indicates the number of threads in each thread block. This indicates the local number of the thread within the thread block; each thread is allocated independent GPU memory space, and the complete Hawk computation process is mapped to the GPU. Each thread independently executes a complete task, including polynomial initialization, NTT / FFT forward and inverse transformations, discrete Gaussian sampling, rejection sampling, modular arithmetic, and polynomial convolution. Under this architecture, each thread has an independent data space in the GPU's global memory to store all its intermediate variables and polynomial data, fundamentally eliminating resource contention and data conflicts between threads. In a large-scale concurrent computing environment, each thread independently processes the complete task, without relying on shared memory or requiring synchronization operations, enabling highly parallel computing tasks and fully utilizing the computing power of the GPU core. To improve global memory access efficiency, this invention optimizes the data layout of the multi-threaded system, ensuring that the data accessed by each thread is stored continuously in global memory, reducing memory access latency and bandwidth conflicts, thereby maintaining high concurrency while ensuring the stability of thread execution and overall throughput performance. Finally, a reasonable number of threads is set according to the GPU's stream processor specifications to determine the peak throughput.

[0057] (2) The butterfly operation implementation of forward and inverse number theory transformations is as follows: Figure 2 As shown: In the Hawk algorithm, number-theoretic transformations and inverse transformations are the core computational blocks of polynomial multiplication. Given a modulus... Transform Length ,as well as order original root (satisfy The transformation is defined as follows:

[0058] ;

[0059] in Indicates the transformed number of... A number, and Represents the first polynomial of the primitive polynomial. One coefficient,

[0060] Similarly, the inverse transform is defined as follows:

[0061] ;

[0062] in Indicates the inverse root of the unit. yes In the model The inverse of multiplication, i.e. .

[0063] However, its original implementation typically uses a triple nested loop to directly calculate the exponent and weighted sum of each output point according to the formula. This implementation method is not only computationally complex, but also... Furthermore, it cannot fully utilize the massive parallel capabilities of GPUs, resulting in low thread utilization and inefficient memory access, thus limiting overall throughput performance. This invention proposes an optimization scheme for the NTT / iNTT module of the Hawk algorithm, transforming the original triple loop form into a layered butterfly structure. In each butterfly operation, the algorithm groups the input sequence by even and odd terms, performing weighted combinations using a pre-calculated twiddle factor. The originally complex exponentiation operations are replaced by addition, subtraction, and multiplication operations, reducing the computational complexity from... Reduce to This reduces the overhead of redundant calculations.

[0064] make This is the current butterfly layer number. This represents the current length of the butterfly-shaped layer. It has a butterfly-shaped span. This is the current layer span, used to control the butterfly index step size.

[0065] polynomial model Field transformations typically employ layered butterfly iterations based on while and for loops, with a time complexity of O(n log n). Furthermore, on GPUs, throughput is limited by discontinuous memory access and increasing step size across layers. To address this, the traditional two-dimensional butterfly unfolding structure of NTT is structurally rearranged into a single-index-driven recursive unfolding model. Specifically, the original butterfly... Calculation:

[0066] ;

[0067] in Represents the corresponding number in the array One element, This represents a temporary variable representing the butterfly effect on the original coefficients. Indicates when The frequency domain result obtained at time i.e., the input sequence at the t-th time... Transformation value on each discrete frequency component, current rotation factor It can be represented as:

[0068] ;

[0069] In the above expression, The rotation factor table stores the root power of unit required for NTT / iNTT. Indicates the index of the current sub-block. The current layer offset is used to calculate the rotation factor in... The index in the table. This linear index design enables butterfly pairs. They are arranged contiguously in memory, enabling efficient contiguous memory access on the GPU. Each butterfly block can be uniformly represented as:

[0070] ;

[0071] Implementing hierarchical anchoring of the rotation factor index enables butterfly sub-blocks to be accessed on the GPU with strictly consecutive linear memory access. and After this index reconstruction is completed, all NTT calculations can be transformed into:

[0072]

[0073] The Butterfly operation's accumulation model consists of fixed-length odd-even pairs, avoiding memory fragmentation caused by multi-level step size jumps in the original implementation. Since both the twiddle factor and the butterfly index are derived from... Unified driving eliminates the address calculation overhead inside the multiple loop structure, regularizes the memory access mode, and strictly anchors the operator calculation and memory access length. The GPU can complete all butterfly fusion operations without additional synchronization and reloading of constant tables, and maximizes the parallel superposition and throughput of each level of transformation. a[j] represents the j-th element in the input array.

[0074] (3) Optimized Implementation of Forward and Inverse Fast Fourier Transforms: In the Hawk algorithm, polynomial multiplication also involves Fast Fourier Transform (FFT) and Inverse Fourier Transform (iFFT) modules. For a length of... sequence :

[0075] ;

[0076] in, Indicates the input sequence number 1 One sampling point, Represents the output frequency domain coefficients. This represents the twiddle factor. Similarly, for a sequence of length n... The inverse transform is shown below:

[0077] ;

[0078] in, This represents the recovered time-domain sequence. Represents the input frequency domain coefficients. It is a rotation factor; since it is a positive exponent, it is multiplied by at the end. j represents the index of the input sequence or polynomial, used to traverse the original data; k represents the index of the transformed frequency domain result, i.e. the kth frequency component; and n represents the sequence length or the order of the polynomial.

[0079] The original implementation typically uses a triple nested loop form that directly calculates according to the formula, that is, for each output frequency domain point... Calculate all input sequences sequentially The method of summing powers of exponents has a computational complexity of O(n log n). When the polynomial length is large, the computational load increases dramatically. Furthermore, direct loop computation cannot fully utilize the massively parallel thread resources of the GPU, resulting in low thread utilization and poor memory access efficiency, thus limiting the overall throughput and response speed of the algorithm.

[0080] This invention proposes rewriting the triple-loop structure of the FFT / iFFT module into a hierarchical butterfly operation. Specifically, the input sequence is split into even-numbered and odd-numbered terms at each level, and then weighted and combined using a pre-calculated twiddle factor. The exponentiation operations that would normally require computation are replaced by addition, subtraction, and multiplication in the butterfly operation, significantly reducing computational complexity and avoiding redundant calculations. Within each butterfly level, multiple butterfly operations can be executed independently and in parallel. Each GPU thread is assigned several butterfly tasks, achieving highly parallel computation through cross-level thread mapping.

[0081] make This is the current butterfly layer number. This represents the current length of the butterfly-shaped layer. It has a butterfly-shaped span. This is a real / imaginary part boundary index used to split a complex number array into its real and imaginary parts.

[0082] polynomial The complex domain Fast Fourier Transform (FFT) typically employs a layered butterfly iteration based on while and for loops, with a time complexity of O(n log n). On GPUs, the throughput bottleneck is caused by discontinuous memory access and increasing step size across layers. To address this, the traditional two-dimensional butterfly unfolding structure of FFT is restructured into a single-index driven recursive unfolding model.

[0083] Specifically, the original butterfly pair The calculation is as follows:

[0084] ;

[0085] in, Represents the corresponding number in the array One element, For the butterfly effect, a temporary variable for the original coefficients. For another element in the sub-block, The twiddle factor. The current butterfly's twiddle factor. It can be represented as:

[0086] ;

[0087] in, For storage Table of twitch factors for the required root power of unity. This represents the local index of the butterfly pair within the current sub-block. This is for layer offset. This linear index design ensures butterfly pairs... They are arranged contiguously in memory, enabling efficient contiguous memory access on the GPU. Each butterfly block can be uniformly represented as:

[0088] ;

[0089] After this index reconstruction is completed, all FFT calculations can be transformed into:

[0090] ;

[0091] The Butterfly operation's accumulation model consists of fixed-length complex odd-even pairs, avoiding memory fragmentation caused by multi-level step size jumps in the original implementation.

[0092] In the GPU parallel implementation, this invention fully considers the access patterns and layout optimization of global memory. By storing data contiguously and rationally planning the access order, each thread can maintain the merging of memory accesses when accessing the input sequence, reducing memory access latency and improving bandwidth utilization. Furthermore, to avoid data conflicts between threads, the results of the butterfly operation are directly written back to global memory and synchronized by thread grouping to ensure data consistency. For iFFT, the operation process is similar to FFT, but the twiddle factor is taken as the conjugate, and each coefficient is multiplied by a factor in the final output stage. This is done to restore the original polynomial coefficient values.

[0093] The key technical points and protected aspects of this invention are as follows: A multi-level butterfly rearrangement method based on a single index is proposed. This method restructures the traditional NTT / iNTT and FFT / iFFT computations, which rely on multiple nested loops, into a linear access model recursively based on layer number and block index. This ensures that each butterfly operation maintains a strictly continuous arrangement of elements in memory, avoiding bandwidth waste and memory fragmentation caused by cross-layer jump-size memory access common in GPUs. By establishing a fixed index step and rotation factor offset for each layer, this invention achieves a coarse-grained parallel butterfly operator execution mode that requires no complex address calculations, no shared memory synchronization, and no thread contention, significantly improving throughput efficiency on GPUs. Furthermore, this invention unifies the parallel execution framework in the forward and inverse transformations of FFT / NTT, where the inverse transformation only requires the use of the corresponding inverse rotation factor and simple normalization at the end to complete the overall recovery. The above method constructs a general high-concurrency polynomial transformation core applicable to both integer modulo domain and real number domain. Its protection scope includes linear indexing system, coarse-grained GPU butterfly execution model, rotation factor hierarchical anchoring strategy, and unified parallel implementation of forward and inverse transformation.

[0094] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any other way. Any modifications or equivalent changes made based on the technical essence of the present invention shall still fall within the scope of protection claimed by the present invention.

Claims

1. A method for accelerating the Hawk algorithm based on GPU multi-threaded parallelism, characterized in that, Includes the following steps: (1) Thread resource allocation and task mapping; (2) Kernel fusion and peak throughput detection; (3) Parallelization and memory access optimization of NTT / iNTT; (4) FFT / iFFT structured parallelization optimization and butterfly operator fusion.

2. The method for accelerating the Hawk algorithm based on GPU multi-threaded parallelism according to claim 1, characterized in that, The thread resource allocation and task mapping in step (1) are implemented in a coarse-grained manner.

3. The method for accelerating the Hawk algorithm based on GPU multi-threaded parallelism according to claim 2, characterized in that, The throughput peak detection in step (2) is determined by setting a reasonable number of threads in the GPU's stream processor specification to determine the throughput peak.

4. The method for accelerating the Hawk algorithm based on GPU multi-threaded parallelism according to claim 3, characterized in that, The NTT / iNTT parallelization reconstruction and memory access optimization in step (3) are achieved through butterfly operations of positive and inverse number theory transformations.

5. The method for accelerating the Hawk algorithm based on GPU multi-threaded parallelism according to claim 4, characterized in that, The FFT / iFFT structured parallelization optimization and butterfly operator fusion in step (4) are achieved through forward and inverse fast Fourier transform optimization.

6. The method for accelerating the Hawk algorithm based on GPU multi-threaded parallelism according to claim 2, characterized in that, The coarse-grained approach is based on multi-threaded parallelism, and is determined according to the thread number. The calculations performed are as follows: ； in, This indicates the number of the thread block in which the current thread resides. This indicates the number of threads in each thread block. This indicates the local number of the thread within the thread block.

7. The method for accelerating the Hawk algorithm based on GPU multi-threaded parallelism according to claim 4, characterized in that, The specific methods for implementing the butterfly operation of the positive and inverse number theory transformations include: Employing a layered butterfly structure, in each layer of butterfly operations, the algorithm groups the input sequence into even-numbered and odd-numbered items, performs weighted combinations using pre-calculated twiddle factors, and replaces the original complex exponentiation operations with addition, subtraction, and multiplication operations, thus reducing the computational complexity from... Reduce to , where n represents the order of the polynomial or the length of the sequence; make This is the current butterfly layer number. This represents the current length of the butterfly-shaped layer. It has a butterfly-shaped span. This is the current layer span, used to control the butterfly index stepping.

8. The method for accelerating the Hawk algorithm based on GPU multi-threaded parallelism according to claim 7, characterized in that, The layered butterfly structure includes original butterfly pairs. The calculation is as follows: ； in, Represents the corresponding number in the array There are elements, where k represents the power of the rotation factor. This represents a temporary variable representing the butterfly effect on the original coefficients. Indicates when The frequency domain result obtained at time i.e., the input sequence at the t-th time... Transformation values ​​on discrete frequency components; current rotation factor Represented as: ； in, The rotation factor table stores the root power of unit required for NTT / iNTT. Indicates the index of the current sub-block. The current layer offset is used to calculate the rotation factor in... Indexes in the table; This linear index design enables butterfly pairs The butterfly blocks are arranged contiguously in memory, and each butterfly block is represented as follows, where j represents the starting offset index of the butterfly block in the current level; h represents the spacing between the two elements to be combined within the block: ； After index reconstruction is complete, all NTT calculations can be transformed into: ； The Butterfly operation's accumulation model consists of fixed-length odd-even pairs, where a[j] represents the j-th element in the input array.

9. The method for accelerating the Hawk algorithm based on GPU multi-threaded parallelism according to claim 5, characterized in that, The specific method for optimizing the forward and inverse fast Fourier transforms is as follows: In the Hawk algorithm, polynomial multiplication involves Fast Fourier Transform and Inverse Fourier Transform modules, for a length of... sequence : ； in, Indicates the input sequence number 1 There are 1 sampling point, where j represents the starting offset index of the butterfly block in the current level. Represents the output frequency domain coefficients. The rotation factor is a positive exponent used to iterate through the original data, and i represents the imaginary unit; for a sequence of length n... The inverse transform is shown below: ； Where k represents the index of the transformed frequency domain result, i.e. the kth frequency component, and n represents the sequence length or the order of the polynomial.

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