Memory bad block parallel detection and repair system based on multi-core processor

Abstract

The invention belongs to the technical field of computer hardware and memories, and particularly discloses a memory bad block parallel detection and repair system based on a multi-core processor. The system comprises a memory array, a multi-core processor, a system state monitoring module, a dynamic strategy generation module and a task scheduling and executing module. The system state monitoring module collects multivariate state parameters in real time; the dynamic strategy generation module calculates optimal scheduling control parameters in real time according to the state parameters on the basis of a reinforcement learning decision model; and the task scheduling and execution module schedules the multi-core processor to execute bad block detection and repair tasks of the storage area in parallel according to the parameters. According to the invention, adaptive global optimization balance of performance, power consumption and reliability in a dynamic change environment is realized.

Description

Technical Field

[0001] This invention belongs to the field of computer hardware and memory technology, specifically relating to a parallel detection and repair system for bad blocks in memory based on a multi-core processor. Background Technology

[0002] In the field of integrated circuits and computer systems, the reliability and data integrity of memory are fundamental to ensuring the long-term stable operation of the system. With the continuous advancement of semiconductor technology and the increasing storage density, memory cells are more susceptible to physical defects, electrical stress aging, and environmental interference, resulting in bad blocks. This makes the efficient detection and repair of bad blocks in memory a crucial technology.

[0003] This parallel detection and repair system based on multi-core processors aims to improve the speed of identifying and processing bad blocks in large-scale memory arrays by leveraging the computational parallelism of multi-core architecture. The goal is to overcome the throughput and real-time performance limitations of traditional single-core processing by decomposing the detection and repair task into multiple subtasks and distributing them concurrently across different processor cores.

[0004] Existing technologies typically employ fixed priority or simple round-robin scheduling strategies to allocate these parallel detection and repair tasks. These static scheduling methods suffer from the following problems: they cannot detect real-time load changes during system operation and struggle to dynamically adjust task allocation based on the current utilization of each processor core; furthermore, they lack consideration for overall system power consumption constraints, failing to effectively manage power consumption while meeting performance targets. Static scheduling strategies struggle to adapt to the dynamic changes in memory reliability requirements across different application scenarios, such as the need for higher detection frequencies and repair priorities during critical task execution. This rigidity in scheduling mechanisms prevents the system from achieving a dynamic, globally optimal balance among the three interdependent objectives of real-time performance, power efficiency, and reliability assurance. This limits the full realization of the potential of multi-core parallel architectures and may affect the overall performance and applicability of the final system. Summary of the Invention

[0005] The purpose of this invention is to provide a parallel detection and repair system for bad blocks in memory based on multi-core processors, so as to solve the problem that static scheduling strategies in the prior art cannot achieve a dynamic global optimal balance between real-time performance, power efficiency and reliability assurance.

[0006] This invention provides a parallel detection and repair system for bad blocks in memory based on a multi-core processor, comprising: The memory array is used to store user data and system data, and is logically divided into multiple independent detection areas; A multi-core processor contains multiple physical or logical processor cores for parallel execution of memory bad block detection and repair tasks; The system status monitoring module is used to collect and quantify multi-dimensional parameters that characterize the system's operating status in real time. These multi-dimensional parameters include the real-time utilization percentage of each processor core, the real-time power consumption of the system as a whole and each core, the current bad block rate of the memory array, and the current reliability level requirement specified by the upper-layer application. The module continuously updates these multi-dimensional parameters at a fixed sampling period to form a system status vector. The dynamic strategy generation module is connected to the system state monitoring module and is used to calculate a set of optimal scheduling control parameters in real time based on the received system state vector and a preset decision model based on a reinforcement learning framework. The task scheduling and execution module is connected to the dynamic policy generation module, the memory array, and the multi-core processor, respectively. It is used to receive and parse the scheduling control parameters issued by the dynamic policy generation module, and then generate specific, executable task instruction sequences.

[0007] Preferably, the scheduling control parameters include the set of detection region identifiers allocated to each processor core, the strength level of the detection algorithm used by each detection task, and the highest frequency level that each processor core is allowed to run at. The decision model is a deep neural network that has been trained offline and fine-tuned online. The input layer receives the normalized system state vector, and the output layer is directly mapped to the scheduling control parameters. The training objective function of the decision model is a comprehensive reward function, which simultaneously considers the reciprocal of the task completion time, the negative of the total system power consumption, and the reliability satisfaction index calculated based on the current bad block rate and the target reliability level.

[0008] Preferably, the task scheduling and execution module divides and binds the detection tasks according to the set of region identifiers in the scheduling control parameters; Configure the corresponding detection threshold and scanning mode according to the algorithm strength level, and adjust the operating voltage and frequency of the corresponding processor core through the underlying driver interface according to the highest frequency level. Then, distribute the packaged task instructions to each designated processor core. Each processor core independently executes its assigned detection task, performs read and write verification and error code verification on the designated memory area, identifies bad blocks and records their physical addresses. After a core completes its detection task, the task scheduling and execution module collects bad block address information and initiates a repair task as needed. The repair task adopts a redundant storage unit replacement mechanism, in which a designated processor core maps the bad block address to a preset spare storage block and updates the system's bad block mapping table.

[0009] Preferably, the online fine-tuning process of the deep neural network in the decision model is as follows: The system maintenance experience replay buffer is used to store historical state vectors, the scheduling control parameters adopted, the immediate rewards obtained after execution, and the experience tuples composed of new state vectors. The system periodically samples a batch of empirical data from the empirical replay buffer, calculates the policy gradient using the temporal difference error, and updates the weight parameters of the deep neural network slightly using the backpropagation algorithm.

[0010] Preferably, the detection algorithm intensity level is divided into at least 3 discrete levels; Level 1 is a fast scan, which uses a lower voltage margin test and a simplified data mode for verification; Level 2 is a standard scan, which uses the factory test standard voltage and timing parameters and a complete check code algorithm; Level 3 is Enhanced Scan, which introduces additional stress test modes and stricter timing tolerances on top of the standard scan.

[0011] Preferably, the calculation process for the reliability satisfaction index is as follows: The system presets a target bad block rate threshold corresponding to the reliability level requirements specified by the current application. The reliability satisfaction index is defined as the absolute value of the difference between the current actual bad block rate and the target bad block rate threshold. It is then mapped by a negative exponential function and normalized to the range of 0 to 1. When the actual bad block rate is less than the target threshold, the reliability satisfaction index value approaches 1.

[0012] Preferably, the task scheduling and execution module further includes a task execution status tracking submodule; The task execution status tracking submodule monitors the execution progress and status of each distributed task in real time, including the estimated remaining execution time and whether an execution timeout or error has occurred. When an abnormal task execution is detected or a processor core becomes saturated due to a sudden load change, the task execution status tracking submodule sends an interrupt signal to the dynamic policy generation module, triggering it to immediately recalculate the scheduling control parameters based on the latest system status.

[0013] Preferably, the system operates within a hierarchical control framework; The hierarchical control framework includes an application policy layer located in user space, a scheduling decision layer located in the operating system kernel space, and a direct execution layer located in the hardware abstraction layer. The application strategy layer is responsible for defining and communicating reliability level requirements; The scheduling decision layer encapsulates the core algorithm of the dynamic policy generation module; The direct execution layer corresponds to the part of the task scheduling and execution module that directly interacts with the hardware. The three layers communicate with each other through clearly defined interfaces and data formats.

[0014] Preferably, the comprehensive reward function R in the dynamic strategy generation module is defined as: ; This represents the average completion time of all detection tasks within the current scheduling period. This represents the system's average total power consumption during this period. As a reliability satisfaction index, , , These are non-negative weighting coefficients.

[0015] The reliability satisfaction index The calculation formula is: ; This represents the current actual bad block rate. The target bad block rate threshold, This is the sensitivity coefficient.

[0016] Preferably, the memory array has a set of redundant storage units pre-set inside. The redundant storage units have completed functional verification at the factory and are in standby mode, used to perform physical address mapping replacement operation after bad blocks are detected.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention constructs an intelligent scheduling system with environmental awareness and autonomous decision-making capabilities by introducing a system state monitoring module and a reinforcement learning-based dynamic policy generation module. This system can respond in real-time to changes in processor load, power consumption, bad block rate, and reliability requirements, dynamically generating optimal scheduling parameters. This achieves a dynamic and global optimal balance among the three mutually constraining objectives of performance, power consumption, and reliability, overcoming the rigidity of traditional static scheduling strategies and unleashing the parallel computing potential of multi-core processors.

[0018] 2. The deep neural network decision model employed in this invention, through a combination of offline training and online fine-tuning, can not only learn the complex, nonlinear mapping relationship between system states and scheduling strategies, but also continuously adapt to changes in the operating environment. The experience playback and periodic fine-tuning mechanisms enable the system to continuously learn and self-optimize, improving its adaptability and robustness in different application scenarios and long-term operation.

[0019] 3. This invention designs a configurable multi-level detection algorithm strength and a real-time interrupt reconfiguration mechanism. The multi-level strength allows the system to finely adjust the detection overhead according to real-time reliability requirements, avoiding unnecessary performance and power consumption losses while ensuring necessary reliability. The interrupt reconfiguration mechanism ensures the agility of the scheduling strategy, enabling timely responses to sudden loads or task anomalies, guaranteeing the real-time response of the system and the reliability of task execution, forming a complete closed-loop control from strategy generation to execution feedback. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the overall technical solution architecture of the present invention; Figure 2 This is a schematic diagram of the core principle framework of the dynamic policy generation module based on reinforcement learning in this invention; Figure 3 This is a logical flow diagram of the task scheduling and execution module in this invention; Figure 4 This is a schematic diagram of the multi-level interaction relationship and data flow of the system status monitoring and hierarchical control framework in this invention; Figure 5 This is a schematic diagram comparing the principle of the strength and reliability satisfaction index of the multi-level detection algorithm in this invention. Detailed Implementation

[0021] Example 1: The overall architecture of the parallel detection and repair system for bad blocks in memory based on a multi-core processor proposed in this invention is shown in the attached figure. Figure 1 As shown in the figure. This system consists of a memory array, a multi-core processor, a system status monitoring module, a dynamic strategy generation module, and a task scheduling and execution module. These modules work together through well-defined data interfaces and control signals to form an adaptive control system with environmental perception, intelligent decision-making, and closed-loop feedback capabilities. The following will be discussed in conjunction with the attached... Figure 1 To be continued Figure 5 The specific implementation methods of this system will be described in detail layer by layer.

[0022] The memory array is the physical carrier for persistently storing user data and critical system metadata. Its internal structure is logically divided into several non-overlapping and address-contiguous detection regions. The size of each detection region can be configured according to the actual application scenario, total memory capacity, and parallel processing granularity requirements, with typical values ​​of 64KB, 128KB, or 256KB. This logical division allows subsequent bad block detection tasks to be split and allocated to multiple processor cores, thereby achieving parallel processing in the spatial dimension. Each detection region is assigned a unique region identifier during system initialization, which serves as a key index for task binding and result aggregation by the task scheduling and execution module. The memory array also has a set of redundant storage units pre-installed. These units have undergone functional verification at the factory and are in standby mode, used to perform physical address mapping replacement operations after bad blocks are detected.

[0023] The multi-core processor comprises multiple physical or logical processor cores, typically 2, 4, 8, or 16, depending on the computing power and cost constraints of the target platform. Each processor core has an independent instruction pipeline, cache subsystem, and memory access interface, enabling concurrent execution of different detection or repair tasks. In this system, the multi-core processor is not only the execution engine for tasks but also the direct target for power consumption and performance control. Each core supports dynamic voltage-frequency adjustment technology, allowing its operating frequency to switch between multiple preset levels, such as 0.8GHz, 1.2GHz, 1.6GHz, and 2.0GHz, with corresponding adjustments to the supply voltage to optimize energy efficiency. All cores share access to the memory array, but through precise coordination of task scheduling and execution modules, performance bottlenecks or data consistency issues caused by concurrent access conflicts can be avoided.

[0024] The system status monitoring module is responsible for real-time acquisition and quantification of multiple parameters characterizing the system's operating status. Its sampling period is fixed at 10 milliseconds to ensure the timeliness and continuity of status information. This module acquires the following four key parameters through hardware performance counters, the power management unit, the diagnostic registers built into the memory controller, and the system call interface provided by the operating system kernel: The first is the real-time utilization percentage of each processor core, calculated as the percentage of time a core is in a non-idle state within the most recent sampling period; the second is the real-time power consumption of the entire system and each core, measured in watts, by a current sensor and voltage monitoring circuit integrated on the motherboard; the third is the current bad block rate of the memory array, defined as the ratio of the number of identified bad blocks to the total number of memory blocks, updated and returned by the task scheduling and execution module after each detection task; the fourth is the current reliability level requirement specified by the upper-layer application through a standard interface, expressed in discrete levels, such as Level 1 (low), Level 2 (medium), and Level 3 (high), corresponding to different service scenarios and fault tolerance requirements. The above four types of parameters, after normalization, are combined into a high-dimensional system state vector, which serves as the input for the dynamic policy generation module. Please refer to the appendix. Figure 4 The diagram clearly illustrates how the system status monitoring module collects raw data from the hardware abstraction layer and uploads it to the scheduling decision layer in the operating system kernel space.

[0025] Fourth, the dynamic strategy generation module is the core intelligent decision-making unit of this system, and its internal structure is shown in the attached figure. Figure 2 As shown, this module receives the normalized system state vector from the system state monitoring module and inputs it into a pre-defined deep neural network model based on a reinforcement learning framework. This model employs a three-layer fully connected neural network structure. The number of neurons in the input layer matches the dimension of the system state vector (e.g., 12 dimensions), the hidden layer contains 64 neurons and uses the ReLU activation function, and the output layer is directly mapped to a set of scheduling control parameters. These parameters specifically include: the set of detection region identifiers allocated to each processor core, the strength level of the detection algorithm used for each detection task (values ​​of 1, 2, or 3), and the highest frequency level allowed for each processor core to run (corresponding to an index in the pre-defined frequency list). The weight parameters of the deep neural network have undergone initial training using a large amount of offline simulation data before system deployment. Its training objective function is a comprehensive reward function R, defined as follows: ; This represents the average completion time (in seconds) of all detection tasks within the current scheduling period. This represents the system's average total power consumption during this period (in watts). As a reliability satisfaction index, , , These are non-negative weighting coefficients used to adjust the priority weights among performance, power consumption, and reliability, with typical values ​​of 0.4, 0.3, and 0.3, respectively. The design of this reward function ensures that the model can simultaneously consider task response speed, energy efficiency, and data reliability during optimization.

[0026] Regarding reliability satisfaction indicators In the specific calculation process, the system first looks up the corresponding target bad block rate threshold from the preset configuration table based on the reliability level requirements specified by the current application. For example, when the reliability level is 3 (high), The value is set to 0.001%; ​​0.01% for level 2 (medium); and 0.1% for level 1 (low). Given the current actual bad block rate, the reliability satisfaction index is defined as: ; This is the sensitivity coefficient, typically 10000, used to control the steepness of exponential decay. After this mapping, the indicator is naturally normalized to the 0-1 range. hour, A value approaching 1 indicates that reliability requirements are fully met; conversely, a value deviating rapidly reflects an increase in reliability risk. This calculation logic is explained in the appendix. Figure 5 There is an intuitive display.

[0027] The dynamic strategy generation module also implements an online fine-tuning mechanism. The system maintains an experience replay buffer with a capacity of 10,000 experience tuples. Each experience tuple contains a quadruple. , For a moment The system state vector, The scheduling and control parameters adopted. The immediate reward obtained after execution. This represents the state vector for the next time step. Every 100 scheduling cycles, the system randomly samples 256 tuples from the buffer, calculates the policy gradient using the temporal difference error, and slightly updates the neural network weights using the Adam optimizer with a learning rate of 0.001. This mechanism enables the model to continuously adapt to long-term dynamic changes such as hardware aging, temperature drift, or sudden changes in load patterns, improving the system's long-term robustness.

[0028] The task scheduling and execution module serves as a bridge connecting the decision-making layer and the execution layer, and its logical flow is shown in the attached figure. Figure 3As shown, this module first receives a scheduling control parameter packet from the dynamic policy generation module. This packet uses a binary serialization format and contains fields such as core ID, region identifier set, algorithm strength level, and frequency level index. The task parser inside the module deserializes the packet and generates a specific task instruction sequence. For each processor core, the task scheduling and execution module performs the following operations: First, based on the region identifier set, it extracts the corresponding physical address range from the logical address space of the memory array; then, it configures the specific behavior of the detection task according to the algorithm strength level—if the level is 1, it uses a simplified data pattern (such as all 0s, all 1s, alternating 0s and 1s) and a 10% reduction in read / write voltage margin for fast scanning; if the level is 2, it uses a complete pseudo-random data sequence and standard JEDEC test timing; if the level is 3, it adds high-temperature simulation (simulating thermal stress by extending the access interval) and a narrower timing window (±0.5 nanoseconds) on top of the standard. Subsequently, the module sends a frequency adjustment instruction to the specified core through the underlying driver interface, locking its operating frequency within the highest level allowed by the policy. After the task instructions are encapsulated, they are distributed to each target core through a dedicated queue of the kernel scheduler.

[0029] After receiving the task, each processor core independently executes the bad block detection process: sequentially performing write-read-verify operations on each storage block within the allocated area, using Hamming codes or BCH codes for error detection and correction. If the read data is inconsistent with the written data and the number of error bits exceeds the error correction capability, the block is determined to be a bad block, and its physical address is recorded. After the detection is completed, the core returns a completion report containing a list of bad block addresses to the task scheduling and execution module. After collecting all reports, the module starts the repair process: traversing the bad block addresses, querying the redundant storage unit pool, allocating an unused spare block for each bad block, updating the global bad block map table, and marking the original bad block as unusable. The map table is organized using a hash structure, supporting address lookups with O(1) time complexity, ensuring the transparency of subsequent data access.

[0030] Furthermore, the task scheduling and execution module embeds a task execution status tracking submodule. This submodule maintains a status record for each distributed task, including fields such as task ID, core to which it belongs, start time, estimated completion time, current progress percentage, and timeout flag. The estimated completion time is dynamically estimated based on the average execution time of similar historical tasks and the current core frequency. If the actual execution time of a task exceeds 150% of the estimated time, or if a core's utilization rate remains above 95% for more than 20 milliseconds due to a sudden high load, the status tracking submodule immediately sends an interrupt signal to the dynamic policy generation module. This signal triggers an emergency scheduling recalculation, and the new policy will take effect in the next scheduling cycle. This policy may include measures such as task migration, intensity degradation, or frequency increase, thereby achieving rapid response to abnormal operating conditions.

[0031] Finally, the entire system operates within a hierarchical control framework, as shown in the attached diagram. Figure 4 As shown, the framework is divided into three layers from top to bottom: the application policy layer in user space, the scheduling decision layer in the operating system kernel space, and the direct execution layer in the hardware abstraction layer. The application policy layer exposes the reliability level setting interface to upper-layer applications through standard system calls (such as ioctl or sysfs interfaces); the scheduling decision layer encapsulates all the logic of the dynamic policy generation module and loads it as a kernel module to ensure low-latency response; the direct execution layer consists of the hardware-interacting parts of the task scheduling and execution module, including frequency adjustment drivers, memory access controllers, interrupt handlers, etc. The three layers communicate through strictly defined interface protocols: the application policy layer transmits reliability level change events downwards; the scheduling decision layer returns the current policy summary and system health status upwards; and the direct execution layer periodically reports raw hardware status data. All cross-layer data is transmitted using fixed-length message structures containing checksum fields to prevent transmission errors.

[0032] In summary, this embodiment deeply integrates multi-core parallel computing, reinforcement learning-driven dynamic scheduling, multi-level detection intensity, closed-loop feedback control, and hierarchical software architecture to construct a highly adaptive memory bad block management ecosystem. This system can perceive environmental changes on a millisecond-level timescale and achieve a fine, dynamic, and globally optimal trade-off between performance, power consumption, and reliability, outperforming traditional bad block management schemes based on fixed thresholds or static rules.

[0033] Example 2: In certain specific application scenarios, such as edge computing devices or embedded IoT terminals, system resources are limited, making it impossible to deploy a complete deep neural network model. Therefore, this example provides a lightweight alternative, the core of which is to replace the deep neural network in the dynamic policy generation module with a hybrid decision-maker based on rule engines and fuzzy logic, while retaining the main architecture of the rest of the system.

[0034] In this embodiment, the sampling period of the system status monitoring module can be appropriately relaxed to 50 milliseconds to reduce monitoring overhead. The dynamic policy generation module no longer relies on neural networks, but maintains a predefined decision rule base. This rule base consists of several production rules in the form of "IF condition THEN action", where the condition part is composed of the various dimensions of the system state vector after fuzzification. For example, for processor core utilization, three fuzzy sets are defined: "low" (0%–30%), "medium" (30%–70%), and "high" (70%–100%); for bad block rate, three fuzzy sets are defined: "safe" (<0.001%), "warning" (0.001%–0.01%), and "dangerous" (>0.01%). The action part of each rule specifies a combination of detection region allocation strategy, algorithm strength level, and frequency level.

[0035] The fuzzy inference process is as follows: First, the real-time collected system state parameters are mapped to the membership degrees of each fuzzy set; then, the activation strength of each rule is calculated using the Mamdani inference method; next, the outputs of all activated rules are weighted and aggregated; finally, the centroid method is used for defuzzification to obtain the specific scheduling control parameters. For example, when the system is in a state of "high core utilization" and "bad block rate warning", the rule base may activate a strategy of "reducing the detection strength of non-critical areas to level 1, using level 3 strength only for high-risk areas, and limiting the frequency to 1.2GHz to control power consumption".

[0036] To improve the adaptability of the rule base, this embodiment introduces an online rule evolution mechanism. The system records the actual effect after each scheduling decision and compares it with the expected target. If large deviations occur repeatedly, a rule correction process is triggered: the condition thresholds or action parameters of existing rules are fine-tuned using a genetic algorithm, or new rules are introduced from the candidate rule pool. This process is executed in a low-priority background thread and does not affect the real-time performance of the main detection task.

[0037] The task scheduling and execution module remains unchanged in this embodiment, still supporting multi-level detection algorithms and interrupt reconfiguration. However, due to the simplified decision-making logic, its task instruction generation latency is reduced, typically less than 1 millisecond, making it more suitable for resource-constrained environments. To save storage space, the number of redundant storage units can be reduced as needed, for example, reserving only 1% of the total capacity as a spare, instead of the 3%–5% of traditional solutions. The system uses more frequent lightweight scans to provide early warnings of potential bad blocks, thereby maintaining an acceptable level of reliability with limited redundancy.

[0038] While this embodiment sacrifices some global optimization capabilities, it has advantages in terms of computing resources, memory usage, and energy consumption, making it suitable for embedded scenarios that are extremely sensitive to cost and power consumption. At the same time, it can still achieve a certain degree of dynamic adaptability through fuzzy logic and rule evolution mechanisms, demonstrating the flexibility and scalability of the architecture of this invention.

[0039] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0040] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A parallel detection and repair system for bad blocks in memory based on a multi-core processor, characterized in that, include: The memory array is used to store user data and system data, and is logically divided into multiple independent detection areas; A multi-core processor contains multiple physical or logical processor cores for parallel execution of memory bad block detection and repair tasks; The system status monitoring module is used to collect and quantify multi-dimensional parameters that characterize the system's operating status in real time. These multi-dimensional parameters include the real-time utilization percentage of each processor core, the real-time power consumption of the system as a whole and each core, the current bad block rate of the memory array, and the current reliability level requirement specified by the upper-layer application. The module continuously updates these multi-dimensional parameters at a fixed sampling period to form a system status vector. The dynamic strategy generation module is connected to the system state monitoring module and is used to calculate a set of optimal scheduling control parameters in real time based on the received system state vector and a preset decision model based on a reinforcement learning framework. The task scheduling and execution module is connected to the dynamic policy generation module, the memory array, and the multi-core processor, respectively. It is used to receive and parse the scheduling control parameters issued by the dynamic policy generation module, and then generate specific, executable task instruction sequences.

2. The parallel detection and repair system for bad blocks in memory based on a multi-core processor according to claim 1, characterized in that, The scheduling control parameters include the set of detection region identifiers allocated to each processor core, the strength level of the detection algorithm used by each detection task, and the highest frequency level that each processor core is allowed to run at. The decision model is a deep neural network that has been trained offline and fine-tuned online. The input layer receives the normalized system state vector, and the output layer is directly mapped to the scheduling control parameters. The training objective function of the decision model is a comprehensive reward function, which simultaneously considers the reciprocal of the task completion time, the negative of the total system power consumption, and the reliability satisfaction index calculated based on the current bad block rate and the target reliability level.

3. The parallel detection and repair system for bad blocks in memory based on a multi-core processor according to claim 2, characterized in that, The task scheduling and execution module divides and binds the detection tasks according to the set of region identifiers in the scheduling control parameters; Configure the corresponding detection threshold and scanning mode according to the algorithm strength level, and adjust the operating voltage and frequency of the corresponding processor core through the underlying driver interface according to the highest frequency level. Then, distribute the packaged task instructions to each designated processor core. Each processor core independently executes its assigned detection task, performs read and write verification and error code verification on the designated memory area, identifies bad blocks and records their physical addresses. After a core completes its detection task, the task scheduling and execution module collects bad block address information and initiates a repair task as needed. The repair task adopts a redundant storage unit replacement mechanism, in which a designated processor core maps the bad block address to a preset spare storage block and updates the system's bad block mapping table.

4. The parallel detection and repair system for bad blocks in memory based on a multi-core processor according to claim 3, characterized in that, The online fine-tuning process of the deep neural network in the decision model is as follows: The system maintenance experience replay buffer is used to store historical state vectors, the scheduling control parameters adopted, the immediate rewards obtained after execution, and the experience tuples composed of new state vectors. The system periodically samples a batch of empirical data from the empirical replay buffer, calculates the policy gradient using the temporal difference error, and updates the weight parameters of the deep neural network slightly using the backpropagation algorithm.

5. The parallel detection and repair system for bad blocks in memory based on a multi-core processor according to claim 4, characterized in that, The detection algorithm strength level is divided into at least 3 discrete levels; Level 1 is a fast scan, which uses a lower voltage margin test and a simplified data mode for verification; Level 2 is a standard scan, which uses the factory test standard voltage and timing parameters and a complete check code algorithm; Level 3 is Enhanced Scan, which introduces additional stress test modes and stricter timing tolerances on top of the standard scan.

6. The parallel detection and repair system for bad blocks in memory based on a multi-core processor according to claim 5, characterized in that, The calculation process for the reliability satisfaction index is as follows: The system presets a target bad block rate threshold corresponding to the reliability level requirements specified by the current application. The reliability satisfaction index is defined as the absolute value of the difference between the current actual bad block rate and the target bad block rate threshold. It is then mapped by a negative exponential function and normalized to the range of 0 to 1. When the actual bad block rate is less than the target threshold, the reliability satisfaction index value approaches 1.

7. The parallel detection and repair system for bad blocks in memory based on a multi-core processor according to claim 6, characterized in that, The task scheduling and execution module also includes a task execution status tracking submodule; The task execution status tracking submodule monitors the execution progress and status of each distributed task in real time, including the estimated remaining execution time and whether an execution timeout or error has occurred. When an abnormal task execution is detected or a processor core becomes saturated due to a sudden load change, the task execution status tracking submodule sends an interrupt signal to the dynamic policy generation module, triggering it to immediately recalculate the scheduling control parameters based on the latest system status.

8. The parallel detection and repair system for bad blocks in memory based on a multi-core processor according to claim 7, characterized in that, The system operates within a hierarchical control framework; The hierarchical control framework includes an application policy layer located in user space, a scheduling decision layer located in the operating system kernel space, and a direct execution layer located in the hardware abstraction layer. The application strategy layer is responsible for defining and communicating reliability level requirements; The scheduling decision layer encapsulates the core algorithm of the dynamic policy generation module; The direct execution layer corresponds to the part of the task scheduling and execution module that directly interacts with the hardware. The three layers communicate with each other through clearly defined interfaces and data formats.

9. The parallel detection and repair system for bad blocks in memory based on a multi-core processor according to claim 8, characterized in that, The comprehensive reward function R in the dynamic strategy generation module is defined as: ； This represents the average completion time of all detection tasks within the current scheduling period. This represents the system's average total power consumption during this period. As a reliability satisfaction index, , , These are non-negative weighting coefficients. The reliability satisfaction index... The calculation formula is: ； This represents the current actual bad block rate. The target bad block rate threshold, This is the sensitivity coefficient.

10. The parallel detection and repair system for bad blocks in memory based on a multi-core processor according to claim 9, characterized in that, The memory array has a set of redundant storage units pre-set inside. The redundant storage units have completed functional verification at the factory and are in standby mode, used to perform physical address mapping replacement operation after bad blocks are detected.

Images