Baud rate serial port configuration system and electronic equipment

Abstract

The invention provides a Baud rate serial port configuration system and electronic equipment, and relates to the technical field of computers, a processing module sends a Baud rate parameter signal to a clock generation module, and the Baud rate parameter signal comprises a target Baud rate type and a control signal corresponding to the target Baud rate type; the clock generation module generates a serial port sending clock matched with a target baud rate and a serial port receiving clock which is a preset multiple of the target baud rate according to the baud rate parameter signal; the serial port receiving unit writes the data into a receiving FIFO cache under the synchronization of a serial port receiving clock; and when the sending FIFO cache is not empty, the serial port sending unit reads the parallel data in the sending FIFO cache, converts the parallel data into serial data under the synchronization of a serial port sending clock, and sends the serial data outwards. And the data transmission reliability and continuity in the full baud rate range are improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a baud rate serial port configuration system and electronic device. Background Technology

[0002] In actual project development, not only is it necessary for general serial ports to meet the usual baud rates, but also to meet some special baud rate values, such as lower baud rates like 75~300bps, and even more special high-speed baud rates like 100kbps, 200Kbps, 500Kbps, 1Mbps, 1.44 Mbps, and 2.4Mbps. Using ordinary serial port chips often only covers a portion of the baud rates and cannot achieve all baud rates. Summary of the Invention

[0003] In view of this, this application provides a baud rate serial port configuration system and electronic device, which aims to solve the limitations of ordinary serial port chips in dealing with low baud rates and high baud rates.

[0004] In a first aspect, this application provides a baud rate serial port configuration system, characterized in that it includes: a processing module, a clock generation module, a receive FIFO buffer, a transmit FIFO buffer, a serial port receiving unit, and a serial port transmitting unit. The processing module is connected to the clock generation module, the clock generation module is connected to the serial port receiving unit and the serial port transmitting unit, the serial port receiving unit is connected to the processing module through the receive FIFO buffer, and the serial port transmitting unit is connected to the processing module through the transmit FIFO buffer.

[0005] The processing module is used to send a baud rate parameter signal to the clock generation module. The baud rate parameter signal includes a target baud rate type and a corresponding control signal for the target baud rate type.

[0006] The clock generation module is used to generate a serial port transmission clock that matches the target baud rate and a serial port reception clock that is a preset multiple of the target baud rate, based on the baud rate parameter signal.

[0007] The serial port receiving unit is used to convert the received serial data into parallel data and write it into the receive FIFO buffer under serial port receiving clock synchronization.

[0008] The serial port transmission unit is used to read parallel data in the transmission FIFO buffer when the transmission FIFO buffer is not empty, and convert it into serial data for transmission under the synchronization of the serial port transmission clock.

[0009] Optionally, the target baud rate type includes adjustable baud rate and fixed baud rate;

[0010] The control signal corresponding to the adjustable baud rate includes the adjustable baud rate division coefficient and the adjustable baud rate output enable;

[0011] The control signals corresponding to the fixed baud rate include one or more of the following: 2.4 Mbps baud rate output enable, 1.44 Mbps baud rate output enable, 1 Mbps baud rate output enable, 500 kbps baud rate output enable, 200 kbps baud rate output enable, 100 kbps baud rate output enable, 128 kbps baud rate output enable, and 256 kbps baud rate output enable.

[0012] In the clock generation module, only one enable function is active at a time.

[0013] Optionally, the target baud rate type is an adjustable baud rate;

[0014] The processing module is used to calculate the ratio of the first clock division to the target baud rate value as the adjustable baud rate division coefficient, and send the adjustable baud rate output enable and the division coefficient to the clock generation module.

[0015] The clock generation module is used to shift the frequency division coefficient one bit to the right to obtain a 0.5 frequency division coefficient; based on an adjustable baud rate counter, using the first clock frequency division as the excitation source, at each rising edge of the clock, if the count value of the adjustable baud rate counter is less than or equal to the 0.5 frequency division coefficient minus one, the count value is incremented by one; otherwise, the count value is cleared and the clock is inverted, and the adjustable baud rate transmission clock is generated cyclically; shifting the frequency division coefficient seven bits to the right to obtain a 1 / 128 frequency division coefficient; based on an adjustable baud rate counter, using the first clock frequency division as the excitation source, at each rising edge of the clock, if the count value of the adjustable baud rate counter is less than or equal to the 1 / 128 frequency division coefficient minus one, the count value is incremented by one; otherwise, the count value is cleared and the clock is inverted, and the adjustable baud rate reception clock is generated cyclically.

[0016] Optionally, the clock generation module is used to use a clock at a preset multiple of 2.4 Mbps as the 2.4 Mbps baud rate receiving clock when the 2.4 Mbps baud rate output enable is valid; based on the 2.4 Mbps baud rate counter, using a clock at a preset multiple of 2.4 Mbps as the excitation source, at each rising edge of the clock, if the count value of the 2.4 Mbps baud rate counter is less than or equal to the value of the frequency division coefficient minus one, the count value is incremented by 1; otherwise, the count value is cleared and the clock is inverted, and the 2.4 Mbps baud rate transmitting clock is generated cyclically.

[0017] Optionally, the clock generation module is used to use a clock of a preset multiple of 1.44 Mbps as the 1.44 Mbps baud rate receiving clock when the 1.44 Mbps baud rate output enable is valid; based on the 1.44 Mbps baud rate counter, using a clock of a preset multiple of 1.44 Mbps as the excitation source, at each rising edge of the clock, if the count value of the 1.44 Mbps baud rate counter is less than or equal to the value of the frequency division coefficient minus one, the count value is incremented by 1; otherwise, the count value is cleared and the clock is inverted, and the 1.44 Mbps baud rate transmitting clock is generated cyclically.

[0018] Optionally, the clock generation module is used to determine the division coefficient based on the first division coefficient multi-selector when any of the 1Mbps, 500kbps, 200kbps, and 100kbps baud rate output enable is valid. Based on the corresponding baud rate counter, with 64MHz as the excitation source, at each rising edge of the clock, if the count value of the counter is less than or equal to the value of the division coefficient minus one, the count value is incremented by one; otherwise, the counter is cleared and the clock is inverted, and the corresponding baud rate transmission clock is generated cyclically.

[0019] Optionally, the clock generation module is used to use a 64MHz reference clock as the 1Mbps baud rate receiving clock when the 1Mbps baud rate output enable is active; when either the 500kbps or 100kbps baud rate output enable is active, it determines the division coefficient based on the second division coefficient multi-selector, and based on the corresponding baud rate counter, using 64MHz as the excitation source, at each rising edge of the clock, if the count value of the counter is less than or equal to the value of the division coefficient minus one, the count value is incremented by one; otherwise, the counter is cleared and the clock is inverted, and the corresponding baud rate receiving clock is generated cyclically; when the 200kbps baud rate output enable is active, based on the 200kbps receiving counter, using 64MHz as the excitation source, the receiving clock is high when the count value of the counter is less than or equal to 3, and low when the count value of the counter is greater than 3, thus forming a 200kbps baud rate receiving clock.

[0020] Optionally, the clock generation module is used to determine the division coefficient based on the third division coefficient multi-selector when either the 128kbps or 256kbps baud rate output enable is active. Based on the corresponding baud rate counter, with 32.768MHz as the excitation source, at each rising edge of the clock, if the count value of the counter is less than or equal to the value of the division coefficient minus one, the count value is incremented by one; otherwise, the counter is cleared and the clock is inverted, and the corresponding baud rate transmission clock is generated cyclically.

[0021] Optionally, the clock generation module is used to determine the division coefficient based on the fourth division coefficient multi-selector when either the 128kbps or 256kbps baud rate output enable is active. Based on the corresponding baud rate counter, with 32.768MHz as the excitation source, at each rising edge of the clock, if the count value of the counter is less than or equal to the value of the division coefficient minus one, the count value is incremented by one; otherwise, the counter is cleared and the clock is inverted, and the corresponding baud rate receiving clock is generated cyclically.

[0022] Secondly, this application also provides an electronic device that employs a baud rate serial port configuration system as described in any of the above claims.

[0023] This application provides a baud rate serial port configuration system and electronic device, including: a processing module, a clock generation module, a receive FIFO buffer, a transmit FIFO buffer, a serial port receiving unit, and a serial port transmitting unit. The processing module is connected to the clock generation module, and the clock generation module is connected to the serial port receiving unit and the serial port transmitting unit. The serial port receiving unit is connected to the processing module through the receive FIFO buffer, and the serial port transmitting unit is connected to the processing module through the transmit FIFO buffer. The processing module is used to send a baud rate parameter signal to the clock generation module. The baud rate parameter signal includes a target baud rate type and a corresponding control signal for the target baud rate type. The clock generation module is used to generate a serial port transmitting clock that matches the target baud rate and a serial port receiving clock that is a preset multiple of the target baud rate, based on the baud rate parameter signal. The serial port receiving unit is used to convert received serial data into parallel data and write it into the receive FIFO buffer under serial port receiving clock synchronization. The serial port transmitting unit is used to read the parallel data in the transmit FIFO buffer when the transmit FIFO buffer is not empty, convert it into serial data, and transmit it externally under serial port transmitting clock synchronization. Thus, the serial port receiving clock of this application adopts an oversampling mechanism with a preset multiple of the target baud rate, combined with the temporary storage function of the FIFO buffer. This high-multiple oversampling accurately captures the attribute information of the serial data, such as start bits, data bits, and stop bits, avoiding data misalignment caused by clock synchronization deviations. Simultaneously, the introduction of the FIFO buffer alleviates the mismatch between data transmission speed and processing module speed, preventing data loss or overflow and improving data transmission reliability across the entire baud rate range. Furthermore, the processing module of this application can complete the configuration by directly sending baud rate parameters to the clock generation module, generating a serial port transmitting clock matching the target baud rate and a serial port receiving clock with a preset multiple of the target baud rate. Even during configuration switching, the serial port transceiver module can still maintain data transmission through the FIFO buffer, preventing service interruption or data loss. This is particularly suitable for devices requiring continuous operation, ensuring service continuity. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in this embodiment or the prior art, the drawings used in the description of the embodiment or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A schematic diagram of a baud rate serial port configuration system provided in this application embodiment;

[0026] Figure 2 A flowchart illustrating one method provided in this application embodiment;

[0027] Figure 3 A schematic diagram of a data acquisition device provided in an embodiment of this application;

[0028] Figure 4 A schematic diagram of a serial port transmission clock multiplexer provided in an embodiment of this application;

[0029] Figure 5 A schematic diagram illustrating the determination process of another adjustable baud rate timer provided in an embodiment of this application;

[0030] Figure 6 A schematic diagram of a serial port clock receiving multiplexer provided in an embodiment of this application;

[0031] Figure 7 A schematic diagram of the determination process of a 2.4Mbps baud rate counter provided for an embodiment of this application;

[0032] Figure 8 A schematic diagram illustrating the determination process of a 1.44Mbps baud rate counter provided in an embodiment of this application;

[0033] Figure 9 A schematic diagram of a first frequency division coefficient multiplexer provided in an embodiment of this application;

[0034] Figure 10 A schematic diagram of a second frequency division coefficient multi-selector provided in an embodiment of this application;

[0035] Figure 11 A schematic diagram of the counting process of a 200kbps receiver counter provided in this application embodiment;

[0036] Figure 12 This is a schematic diagram of a third frequency division coefficient multi-selector provided in an embodiment of this application. Detailed Implementation

[0037] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0038] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0039] Unless otherwise stated, the term "multiple" means two or more. In embodiments of this disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B means: A or B. The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0041] See Figure 1 The diagram illustrates a baud rate serial port configuration system. The system includes: a processing module, a clock generation module, a receive FIFO buffer, a transmit FIFO buffer, a serial port receiving unit, and a serial port transmitting unit. The processing module is connected to the clock generation module, which in turn is connected to both the serial port receiving unit and the serial port transmitting unit. The serial port receiving unit is connected to the receive FIFO buffer, and the serial port transmitting unit is connected to the transmit FIFO buffer. Both the receive and transmit FIFO buffers are connected to the processing module.

[0042] The processing module is used to send a baud rate parameter signal to the clock generation module. The baud rate parameter signal includes a target baud rate type and a corresponding control signal for the target baud rate type.

[0043] The processing module can be the FPGA's built-in processing system (PS).

[0044] The clock generation module is used to generate a serial port transmission clock that matches the target baud rate and a serial port reception clock that is a preset multiple of the target baud rate, based on the baud rate parameter signal.

[0045] Optionally, the preset multiplier can be 64 times.

[0046] The aforementioned serial port is a general data communication protocol that converts parallel data into serial data for transmission when sending data, and converts received serial data into parallel data when receiving data.

[0047] The serial port receiving unit receives external serial data through the Rx terminal, converts the serial data into parallel data under serial port receive clock synchronization, and writes it into the receive FIFO buffer. The processing module reads the data in the receive FIFO buffer through the AXI bus. The processing module writes parallel data into the transmit FIFO buffer through the AXI bus. When the transmit FIFO buffer is not empty, the serial port transmitting module reads the parallel data in the transmit FIFO buffer, converts it into serial data under serial port transmit clock synchronization, and transmits it outward through the Tx terminal.

[0048] Based on the above-mentioned device, the serial port receiving clock of this application adopts an oversampling mechanism of a preset multiple of the target baud rate, combined with the temporary storage function of the FIFO buffer. In this way, the high-multiple oversampling accurately captures the attribute information of the serial data, such as the start bit, data bits, and stop bits, avoiding data misalignment caused by clock synchronization deviation. Simultaneously, the introduction of the FIFO buffer alleviates the contradiction between the data transmission speed and the processing speed of the processing module, preventing data loss or overflow and improving the reliability of data transmission across the entire baud rate range. Furthermore, the processing module of this application can complete the configuration by directly sending the baud rate parameter to the clock generation module, generating a serial port transmitting clock matching the target baud rate and a serial port receiving clock of a preset multiple of the target baud rate. Even during configuration switching, the serial port transceiver module can still maintain data transmission through the FIFO buffer, preventing service interruption or data loss. This is particularly suitable for devices requiring continuous operation, ensuring service continuity.

[0049] Based on the above embodiments, the target baud rate type includes adjustable baud rate and fixed baud rate;

[0050] The control signal corresponding to the adjustable baud rate includes the adjustable baud rate division coefficient and the adjustable baud rate output enable;

[0051] The control signals corresponding to the fixed baud rate include one or more of the following: 2.4 Mbps baud rate output enable, 1.44 Mbps baud rate output enable, 1 Mbps baud rate output enable, 500 kbps baud rate output enable, 200 kbps baud rate output enable, 100 kbps baud rate output enable, 128 kbps baud rate output enable, and 256 kbps baud rate output enable.

[0052] In the clock generation module, only one enable function is active at a time.

[0053] See Figure 2 The diagram shows a signal transmission schematic of a clock generation module. The clock generation module has the following input signals: multiple high-speed clock inputs, adjustable baud rate division coefficient, adjustable baud rate output enable, 2.4Mbps baud rate output enable, 1.44Mbps baud rate output enable, 1Mbps baud rate output enable, 500kbps baud rate output enable, 200kbps baud rate output enable, 100kbps baud rate output enable, 128kbps baud rate output enable, and 256kbps baud rate output enable.

[0054] When the adjustable baud rate output enable is set to active, the clock generation module generates adjustable serial port transmit and receive clocks based on the adjustable baud rate division coefficient.

[0055] When other enable signals are enabled, a fixed serial port transmit and receive clock is generated. The adjustable baud rate output enable and other enable signals are mutually exclusive; only one enable signal is allowed at a time.

[0056] Based on the above embodiments, when the target baud rate type is adjustable baud rate, the generation method for the serial port transmit clock and serial port receive clock is as follows:

[0057] The processing module is used to calculate the ratio of the first clock division to the target baud rate value as the adjustable baud rate division coefficient, and send the adjustable baud rate output enable and the division coefficient to the clock generation module.

[0058] In one example, the adjustable baud rate receiving clock can be derived from a 117.9648MHz clock by dividing the frequency. The formula for calculating the frequency division factor is: Frequency division factor = 117964800 ÷ target baud rate;

[0059] The clock generation module is used to shift the frequency division coefficient one bit to the right to obtain a 0.5 frequency division coefficient; based on an adjustable baud rate counter, using the first clock frequency division as the excitation source, at each rising edge of the clock, if the count value of the adjustable baud rate counter is less than or equal to the 0.5 frequency division coefficient minus one, the count value is incremented by one; otherwise, the count value is cleared and the clock is inverted, and the adjustable baud rate transmission clock is generated cyclically; shifting the frequency division coefficient seven bits to the right to obtain a 1 / 128 frequency division coefficient; based on an adjustable baud rate counter, using the first clock frequency division as the excitation source, at each rising edge of the clock, if the count value of the adjustable baud rate counter is less than or equal to the 1 / 128 frequency division coefficient minus one, the count value is incremented by one; otherwise, the count value is cleared and the clock is inverted, and the adjustable baud rate reception clock is generated cyclically.

[0060] In this way, an adjustable baud rate can be configured to achieve communication functions at multiple baud rates, and can also meet the needs of low baud rates.

[0061] In one specific implementation, see Figure 3 The diagram illustrates the judgment process of an adjustable baud rate timer. When generating the adjustable baud rate transmission clock, the aforementioned frequency division coefficient is first shifted right by one bit to obtain a 0.5 times frequency division coefficient, achieving the purpose of dividing by 2, thus avoiding the problems of high resource consumption, high latency, and difficult timing convergence caused by using a divider. An adjustable baud rate counter is set up, using 117.9648MHz as the excitation source. At each rising edge of the clock, if the adjustable baud rate counter is less than (0.5 times the frequency division coefficient - 1), the adjustable baud rate counter is incremented by 1; otherwise, the adjustable baud rate counter is cleared, and the adjustable baud rate transmission clock is inverted. After the adjustable baud rate counter is cleared, it can be re-judged to see if the adjustable baud rate counter is less than (0.5 times the frequency division coefficient - 1). This process is repeated to generate the adjustable baud rate transmission clock. Furthermore, when the adjustable baud rate output is enabled, the following steps are performed: Figure 4 The diagram shown illustrates a serial port clock multiplexer. Figure 4 The selection of the multiplexer in the middle will select the serial port transmit clock to the adjustable baud rate transmit clock.

[0062] In one specific implementation, see Figure 5The diagram illustrates another process for determining the adjustable baud rate timer. When generating the adjustable baud rate receiving clock, the division factor can be shifted right by one bit to obtain a 0.5x division factor, then shifted right by six bits to achieve a 64x division, generating an oversampled clock. This achieves the overall goal of dividing by 128, avoiding the resource consumption, high latency, and timing convergence difficulties associated with using a divider. An adjustable baud rate counter is set up, using 117.9648MHz as the excitation source. On each rising edge of the clock, if the adjustable baud rate counter is less than (1 / 128x division factor - 1), the adjustable baud rate counter increments by 1; otherwise, it is reset to zero, and the adjustable baud rate receiving clock is inverted. After the adjustable baud rate counter is reset, it can be re-determined whether it is less than (1 / 128x division factor - 1). This process is repeated to generate the adjustable baud rate receiving clock. Furthermore, when the adjustable baud rate output is enabled, the following steps are performed: Figure 6 The diagram shows a serial port clock receiving multiplexer. Figure 6 The selection of the multiplexer in the middle will select the serial port receive clock to the adjustable baud rate receive clock.

[0063] Based on the above embodiments, for a fixed baud rate, the frequency division coefficient can be directly determined, and the frequency division coefficient in the counter is determined by the ratio of the excitation source to the target baud rate.

[0064] In one possible implementation, the clock generation module is configured to use a clock at a preset multiple of 2.4 Mbps as the 2.4 Mbps baud rate receiving clock when the 2.4 Mbps baud rate output enable is active; based on a 2.4 Mbps baud rate counter, using a clock at a preset multiple of 2.4 Mbps as the excitation source, at each rising edge of the clock, if the count value of the 2.4 Mbps baud rate counter is less than or equal to the value of the frequency division coefficient minus one, the count value is incremented by 1; otherwise, the count value is cleared and the clock is inverted, and the 2.4 Mbps baud rate transmitting clock is generated cyclically.

[0065] In one example, when the 2.4 Mbps baud rate output is enabled, combined with Figure 4 and Figure 6 The serial port transmit clock is selected at a 2.4Mbps baud rate, and the serial port receive clock is selected at a 2.4Mbps baud rate. On one hand, for oversampling purposes, since 2.4Mbps is 64 times 153.6MHz, this can be directly used as the 2.4Mbps receive clock. On the other hand, see... Figure 7The diagram illustrates the judgment process of a 2.4Mbps baud rate counter. A 2.4Mbps baud rate counter is established, using 153.6MHz as the excitation source. On each rising edge of the clock, if the 2.4Mbps baud rate counter is less than or equal to (the prescaler - 1), the counter increments by 1; otherwise, it is reset to zero, and the 2.4Mbps baud rate transmission clock is inverted. After the 2.4Mbps baud rate counter is reset, it can continue to use 153.6MHz as the excitation source, and on each rising edge of the clock, it re-determines whether the 2.4Mbps baud rate counter is less than (the prescaler - 1). This process is repeated to generate a 2.4Mbps baud rate transmission clock.

[0066] In one possible implementation, the clock generation module is configured to use a clock at a preset multiple of 1.44 Mbps as the 1.44 Mbps baud rate receiving clock when the 1.44 Mbps baud rate output enable is active; based on a 1.44 Mbps baud rate counter, using a clock at a preset multiple of 1.44 Mbps as the excitation source, at each rising edge of the clock, if the count value of the 1.44 Mbps baud rate counter is less than or equal to the value of the frequency division coefficient minus one, the count value is incremented by 1; otherwise, the count value is cleared and the clock is inverted, thus cyclically generating a 1.44 Mbps baud rate transmitting clock.

[0067] In one example, the excitation source could be 64 times 1.44 Mbps, or 92.16 MHz. Combined with... Figure 4 and Figure 6 The serial port transmit clock is selected at a baud rate of 1.44 Mbps, and the serial port receive clock is selected at a baud rate of 1.44 Mbps. On one hand, for oversampling purposes, 92.16 MHz can be directly used as the 1.44 Mbps receive clock. On the other hand, see... Figure 8 The diagram illustrates the judgment process of a 1.44Mbps baud rate counter. A 1.44Mbps baud rate counter is established, using 92.16MHz as the excitation source. On each rising edge of the clock, if the 1.44Mbps baud rate counter is less than or equal to (the division factor - 1), the counter is incremented by 1; otherwise, it is reset to zero, and the 1.44Mbps baud rate transmission clock is inverted. After the 1.44Mbps baud rate counter is reset, it can continue to use 92.16MHz as the excitation source, and on each rising edge of the clock, it is re-evaluated whether the 1.44Mbps baud rate counter is less than (the division factor - 1). This process is repeated to generate a 1.44Mbps baud rate transmission clock.

[0068] In one possible implementation, the clock generation module is used to determine a division coefficient based on a first division coefficient multiplexer when any of the 1Mbps, 500kbps, 200kbps, or 100kbps baud rate output enable is active. Based on the corresponding baud rate counter, using 64MHz as the excitation source, at each rising edge of the clock, if the count value of the counter is less than or equal to the value of the division coefficient minus one, the count value is incremented by one; otherwise, the counter is cleared and the clock is inverted, and the corresponding baud rate transmission clock is generated cyclically.

[0069] See Figure 9 The diagram shows a first frequency division multiplexer. The frequency division coefficient determined based on the first frequency division multiplexer can be 32 when the output baud rate of 1 Mbps is enabled, 64 when the output baud rate of 500 kbps is enabled, 160 when the output baud rate of 200 kbps is enabled, and 320 when the output baud rate of 100 kbps is enabled.

[0070] In one example, since the baud rates of 1Mbps, 500kbps, 200kbps, and 100kbps are all proportional to the 64MHz clock frequency, a 64MHz clock source is used in combination with different frequency division coefficients to generate transmission clocks at baud rates of 1Mbps, 500kbps, 200kbps, and 100kbps.

[0071] In one example, baud rate counters are set up, using 64MHz as the excitation source. On each rising edge of the clock, if the baud rate counter is less than or equal to (the prescaler corresponding to the baud rate - 1), the baud rate counter increments by 1; otherwise, the baud rate counter is reset to zero, and the baud rate transmission clock is inverted. After the baud rate counter is reset to zero, it can be re-evaluated to see if it is less than (the prescaler corresponding to the baud rate - 1). This process is repeated to generate the transmission clock for that baud rate. The baud rate can be one of 1Mbps, 500kbps, 200kbps, or 100kbps.

[0072] In another example, a single counter can be used to represent multiple baud rates, including 1Mbps, 500kbps, 200kbps, and 100kbps. All counters are driven by a 64MHz clock source, and different baud rates are achieved by dynamically switching the division factor. When a baud rate enable signal is active, the corresponding division factor is selected as the counting threshold. The counter increments from 0 until the threshold is decremented by one, then resets to zero and toggles the output clock, thus generating the desired baud rate. This architecture supports flexible switching between multiple baud rates, ensuring precise and controllable timing during communication, while reducing hardware resource overhead and improving system integration and stability.

[0073] In combination with the above Figure 4 When only one of the 1Mbps, 500kbps, 200kbps, and 100kbps baud rate outputs is enabled, the multiplexer will select the serial port transmit clock to the corresponding baud rate transmit clock.

[0074] In one possible implementation, the clock generation module is configured to use a 64MHz reference clock as the 1Mbps baud rate receiving clock when the 1Mbps baud rate output enable is active; when either the 500kbps or 100kbps baud rate output enable is active, it determines the division coefficient based on the second division coefficient multi-selector, and based on the corresponding baud rate counter, using 64MHz as the excitation source, increments the counter by one at each rising edge of the clock if the counter value is less than or equal to the value of the division coefficient minus one; otherwise, the counter is cleared and the clock is inverted, thus cyclically generating the corresponding baud rate receiving clock; when the 200kbps baud rate output enable is active, based on the 200kbps receiving counter, using 64MHz as the excitation source, the receiving clock is high when the counter value is less than or equal to 3, and low when the counter value is greater than 3, thus forming the 200kbps baud rate receiving clock.

[0075] Understandably, when a 1Mbps baud rate is enabled, the serial port receive clock selects a 1Mbps receive clock. For oversampling purposes, since 64 times 1Mbps is 64MHz, 64MHz can be directly used as the 1Mbps receive clock.

[0076] In one example, since both 500kbps and 100kbps baud rates have a certain multiple relationship with the 64MHz clock frequency, a 64MHz clock source is used, along with their respective frequency division coefficients, to generate the 500kbps and 100kbps receive clocks. See also Figure 10The diagram shows a second frequency division multiplexer. Based on the second frequency division multiplexer, the frequency division coefficient can be determined as follows: a frequency division coefficient of 1 corresponds to the 500kbps baud rate output being enabled, and a frequency division coefficient of 5 corresponds to the 100kbps baud rate output being enabled.

[0077] In one example, corresponding counters can be set for both 500kbps and 100kbps baud rates to determine the baud rate receiving clock for each counter. Alternatively, the same counter can be used, with different division coefficients configured to determine the corresponding baud rate receiving clock.

[0078] In one example, since 64 times the 200kbps baud rate is 12.8MHz, which is exactly one-fifth of 64MHz, it is not an even-number division application. Therefore, this application uses a 2:3 duty cycle to generate the clock. Although the clock duty cycle is not 1:1, it does not affect functionality and performance in oversampling applications for serial port reception, thus saving one input clock source. For details, see [link to relevant documentation]. Figure 11 The diagram illustrates the counting process of a 200kbps receiver counter. Using a 64MHz clock source, a counter is designed to increment from 0 to 5, named the 200kbps receiver counter. When it reaches 5, it is reset to zero and incremented again. A comparator is used to assign the 200kbps receiver clock value. The counter is set to 1 when the 200kbps receiver counter is less than or equal to 3, and 0 when it is greater than 3. This generates three 64MHz high-level signals and two 64MHz low-level signals, thus producing a 12.8MHz receiver clock.

[0079] In one possible implementation, the clock generation module is used to determine the division coefficient based on the third division coefficient multi-selector when either the 128kbps or 256kbps baud rate output enable is active. Based on the corresponding baud rate counter, with 32.768MHz as the excitation source, at each rising edge of the clock, if the count value of the counter is less than or equal to the value of the division coefficient minus one, the count value is incremented by one; otherwise, the counter is cleared and the clock is inverted, and the corresponding baud rate transmission clock is generated cyclically.

[0080] See Figure 12 The diagram shows a third-division multiplexer. Since both 128kbps and 256kbps baud rates have a certain multiple relationship with the 32.768MHz clock frequency, a 32.768MHz clock source is used, along with different division coefficients, to generate 128kbps and 256kbps transmit baud rate clocks. When the 128kbps baud rate is enabled, the division coefficient is 128; when the 256kbps baud rate is enabled, the division coefficient is 64.

[0081] When either the 128kbps or 256kbps baud rate output enable is active, the frequency division coefficient is determined based on the fourth frequency division coefficient multi-selector. Based on the corresponding baud rate counter, with 32.768MHz as the excitation source, at each rising edge of the clock, if the count value of the counter is less than or equal to the value of the frequency division coefficient minus one, the count value is incremented by one; otherwise, the counter is cleared and the clock is inverted, and the corresponding baud rate receiving clock is generated cyclically.

[0082] In one example, since both 128kbps and 256kbps baud rates have a certain multiple relationship with the 32.768MHz clock frequency, a 32.768MHz clock source is used, along with different frequency division ratios, to generate 128kbps and 256kbps receive baud rate clocks. Because the receive clock requires 64 times frequency oversampling, the frequency division ratio is 2 when 128kbps baud rate is enabled, and 1 when 256kbps baud rate is enabled.

[0083] In one example, the counters corresponding to the 128kbps and 256kbps baud rates can be a single counter, both driven by a 32.768MHz clock source. Different baud rate clock outputs are achieved by dynamically switching the frequency division coefficient based on the baud rate. When a baud rate enable signal is valid, the corresponding frequency division coefficient is selected as the counting threshold. The counter accumulates from 0 until the threshold is decremented by one, then resets to zero and the clock is inverted, thereby generating the required 128kbps or 256kbps baud rate transmit clock. Similarly, the 128kbps or 256kbps baud rate receive clock operates similarly, which will not be elaborated here. This supports flexible switching between multiple baud rates, ensuring precise and controllable timing during communication, while reducing hardware resource overhead and improving system integration and stability.

[0084] Based on the above embodiments, this application has the following advantages:

[0085] First, the processing module sends simple command signals to the clock generation module to achieve the output of various serial port clocks. Furthermore, the clock source used in this application is simple; it can be generated by an external phase-locked loop or by a clock crystal oscillator. Finally, this application can output both adjustable and special clocks, meeting the needs of different communication scenarios, and has good scalability, adapting to future baud rate standards.

[0086] This application also provides corresponding devices for implementing the solutions provided in this application.

[0087] An electronic device, characterized in that it employs a baud rate serial port configuration system as described in any one of the above-mentioned methods.

[0088] In the embodiments of this application, the terms "first" and "second" (if they exist) are used only as name identifiers and do not represent the order of first and second.

[0089] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that all or part of the steps in the methods of the above embodiments can be implemented by means of software plus a general-purpose hardware platform. Based on this understanding, the technical solution of this application can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as a read-only memory (ROM) / RAM, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, a server, or a network communication device such as a router) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0090] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0091] The above description is merely an exemplary implementation of this application and is not intended to limit the scope of protection of this application.

Claims

1. A baud rate serial port configuration system, characterized in that, include: The system includes a processing module, a clock generation module, a receive FIFO buffer, a transmit FIFO buffer, a serial port receiving unit, and a serial port transmitting unit. The processing module is connected to the clock generation module, and the clock generation module is connected to the serial port receiving unit and the serial port transmitting unit. The serial port receiving unit is connected to the processing module through the receive FIFO buffer, and the serial port transmitting unit is connected to the processing module through the transmit FIFO buffer. The processing module is used to send a baud rate parameter signal to the clock generation module. The baud rate parameter signal includes a target baud rate type and a corresponding control signal for the target baud rate type. The clock generation module is used to generate a serial port transmission clock that matches the target baud rate and a serial port reception clock that is a preset multiple of the target baud rate, based on the baud rate parameter signal. The serial port receiving unit is used to convert the received serial data into parallel data and write it into the receive FIFO buffer under serial port receiving clock synchronization. The serial port transmission unit is used to read parallel data in the transmission FIFO buffer when the transmission FIFO buffer is not empty, and convert it into serial data for transmission under the synchronization of the serial port transmission clock.

2. The system according to claim 1, characterized in that, The target baud rate type includes adjustable baud rate and fixed baud rate; The control signal corresponding to the adjustable baud rate includes the adjustable baud rate division coefficient and the adjustable baud rate output enable; The control signals corresponding to the fixed baud rate include one or more of the following: 2.4 Mbps baud rate output enable, 1.44 Mbps baud rate output enable, 1 Mbps baud rate output enable, 500 kbps baud rate output enable, 200 kbps baud rate output enable, 100 kbps baud rate output enable, 128 kbps baud rate output enable, and 256 kbps baud rate output enable. In the clock generation module, only one enable function is active at a time.

3. The system according to claim 2, characterized in that, The target baud rate type is adjustable baud rate; The processing module is used to calculate the ratio of the first clock division to the target baud rate value as the adjustable baud rate division coefficient, and send the adjustable baud rate output enable and the division coefficient to the clock generation module. The clock generation module is used to shift the frequency division coefficient one bit to the right to obtain a frequency division coefficient of 0.

5. Based on the adjustable baud rate counter, using the first clock division as the excitation source, at each rising edge of the clock, if the count value of the adjustable baud rate counter is less than or equal to the value of the 0.5 times division coefficient minus one, the count value is incremented by one; otherwise, the count value is cleared and the clock is inverted, and the adjustable baud rate transmission clock is generated cyclically; the division coefficient is shifted seven bits to the right to obtain a 1 / 128 times division coefficient; Based on the adjustable baud rate counter, using the first clock division as the excitation source, at each rising edge of the clock, if the count value of the adjustable baud rate counter is less than or equal to the value of the 1 / 128 times division coefficient minus one, the count value is incremented by one; otherwise, the count value is cleared and the clock is inverted, and the adjustable baud rate receiving clock is generated cyclically.

4. The system according to claim 2, characterized in that, The clock generation module is used to use a clock that is a preset multiple of 2.4 Mbps as the 2.4 Mbps baud rate receiving clock when the 2.4 Mbps baud rate output enable is valid. Based on a 2.4Mbps baud rate counter, with a clock frequency that is a preset multiple of 2.4Mbps as the excitation source, at each rising edge of the clock, if the count value of the 2.4Mbps baud rate counter is less than or equal to the value of the frequency division coefficient minus one, the count value is incremented by 1; otherwise, the count value is cleared and the clock is inverted, and a 2.4Mbps baud rate transmission clock is generated cyclically.

5. The system according to claim 2, characterized in that, The clock generation module is used to use a clock of a preset multiple of 1.44 Mbps as the 1.44 Mbps baud rate receiving clock when the 1.44 Mbps baud rate output enable is valid; based on the 1.44 Mbps baud rate counter, using a clock of a preset multiple of 1.44 Mbps as the excitation source, at each rising edge of the clock, if the count value of the 1.44 Mbps baud rate counter is less than or equal to the value of the frequency division coefficient minus one, the count value is incremented by 1; otherwise, the count value is cleared and the clock is inverted, and the 1.44 Mbps baud rate transmitting clock is generated cyclically.

6. The system according to claim 2, characterized in that, The clock generation module is used to determine the division coefficient based on the first division coefficient multi-selector when any of the 1Mbps, 500kbps, 200kbps, and 100kbps baud rate output enable is valid. Based on the corresponding baud rate counter, with 64MHz as the excitation source, at each rising edge of the clock, if the count value of the counter is less than or equal to the value of the division coefficient minus one, the count value is incremented by one; otherwise, the counter is cleared and the clock is inverted, and the corresponding baud rate transmission clock is generated cyclically.

7. The system according to claim 6, characterized in that, The clock generation module is used to use a 64MHz reference clock as the 1Mbps baud rate receiving clock when the 1Mbps baud rate output enable is active; when either the 500kbps or 100kbps baud rate output enable is active, it determines the division coefficient based on the second division coefficient multi-selector, and uses a 64MHz excitation source based on the corresponding baud rate counter. At each rising edge of the clock, if the counter value is less than or equal to the division coefficient minus one, the counter value is incremented by one; otherwise, the counter is cleared and the clock is inverted, thus generating the corresponding baud rate receiving clock in a loop. When the 200kbps baud rate output enable is active, based on the 200kbps receiving counter, using a 64MHz excitation source, the receiving clock is high when the counter value is less than or equal to 3, and low when the counter value is greater than 3, thus forming the 200kbps baud rate receiving clock.

8. The system according to claim 2, characterized in that, The clock generation module is used to determine the division coefficient based on the third division coefficient multi-selector when either the 128kbps or 256kbps baud rate output enable is active. Based on the corresponding baud rate counter, with 32.768MHz as the excitation source, at each rising edge of the clock, if the count value of the counter is less than or equal to the value of the division coefficient minus one, the count value is incremented by one; otherwise, the counter is cleared and the clock is inverted, and the corresponding baud rate transmission clock is generated cyclically.

9. The system according to claim 8, characterized in that, The clock generation module is used to determine the division coefficient based on the fourth division coefficient multi-selector when either the 128kbps or 256kbps baud rate output enable is active. Based on the corresponding baud rate counter, with 32.768MHz as the excitation source, at each rising edge of the clock, if the count value of the counter is less than or equal to the value of the division coefficient minus one, the count value is incremented by one; otherwise, the counter is cleared and the clock is inverted, and the corresponding baud rate receiving clock is generated cyclically.

10. An electronic device, characterized in that, A baud rate serial port configuration system according to any one of claims 1-9.

Images