Graphic processor architecture, branch execution method and compiling method thereof
By introducing structures such as condition code registers, active thread mask registers, and SIMD schedulers into the graphics processor, and combining this with specific instructions inserted by the compiler, the deadlock problem in the graphics processor during conditional branch execution is solved, improving hardware utilization and execution efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- METAX INTEGRATED CIRCUITS (SHANGHAI) CO LTD
- Filing Date
- 2026-04-15
- Publication Date
- 2026-05-15
AI Technical Summary
Graphics processors are prone to SIMD deadlock when executing conditional branches, resulting in low ALU utilization and difficulty in efficiently executing branch instructions.
By employing condition code registers, active thread mask registers, SIMD barrier registers, and SIMD schedulers, combined with the SIMD scheduler, branch control and deadlock detection are achieved through the insertion of SIMD barrier initialization, yield instructions, and conditional jump instructions.
This improves hardware utilization, reduces the probability of SIMD deadlock, and ensures efficient execution of the graphics processor.
Smart Images
Figure CN122048626A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip design, and in particular to an architecture of a graphics processor, a branch execution method, and a compilation method thereof. Background Technology
[0002] To improve throughput, graphics processing units (GPUs) typically employ massively parallel architectures, dividing threads into several groups, also known as warps or wavefronts. Threads within each group execute in lockstep mode on a shared ALU array using Single Instruction Multiple Threading (SIMT). When encountering conditional branches, the compiler is required to linearize the basic blocks. To support high concurrency, the system also maintains a complete context for all active threads and has the ability to quickly switch between threads. However, this architecture faces a series of technical challenges in practical applications. For example, during program execution, SIMD deadlock may occur, meaning that when some threads in the same thread group need other threads to unlock them, the program will enter a deadlock state. Another example is that when executing a conditional branch, threads that do not meet the condition are disabled, resulting in low ALU utilization and some ALUs remaining idle and waiting.
[0003] Therefore, how to enable graphics processors to execute branch instructions correctly and efficiently has become a technical problem that urgently needs to be solved. Summary of the Invention
[0004] To address the aforementioned technical problems, the technical solution adopted by this invention is as follows: This invention provides a graphics processor architecture, the architecture comprising: The condition code register cmsk is a set of bit-field registers used to store condition codes. Its bit width is equal to the number of threads included in the thread group. Each bit of the condition code corresponds to one thread in the thread group and is used to store the result of the condition judgment. The active thread mask register xmsk is a bit-field register used to store the active thread mask. Its bit width is equal to the number of threads included in the thread group. Each bit of the active thread mask corresponds to a thread in the thread group and controls whether the corresponding thread is currently active, so that the SIMD scheduler can correctly execute the differentiated control flow. The SIMD barrier register is a set of bit-field registers used to store the barrier participation mask. Its bit width is equal to the number of threads in the thread group and is used to indicate whether the corresponding thread participates in the barrier. The SIMD scheduling table is used to store all currently active thread groups. Each thread group corresponds to one table entry, and each table entry includes a program counter and an active thread mask. It supports inserting or retrieving table entries from any position. The SIMD scheduler is used to perform splitting, merging, or scheduling on currently active thread groups by combining the condition codes, active thread masks, barrier participation masks, and the SIMD scheduling table.
[0005] Furthermore, embodiments of the present invention also provide a branch execution method based on a graphics processor, the method comprising: If the graphics processor configured with the above architecture acquires and decodes an unconditional jump instruction with a first preset format, the graphics processor jumps the program counter to the instruction position specified by the unconditional jump instruction. If the graphics processor configured with the above architecture acquires and decodes a conditional jump instruction with a second preset format, then different jump operations are executed according to the relationship between the condition code in the condition code register specified in the conditional jump instruction and the current active thread mask stored in the active thread mask register. If the graphics processor configured with the above architecture obtains and decodes the SIMD barrier initialization instruction with a third preset format, then the current active thread mask is stored as the initial value of the barrier participation mask in the SIMD barrier register specified by the SIMD barrier initialization instruction, and the counter specified by the SIMD barrier initialization instruction is initialized. If a graphics processor configured with the above architecture acquires and decodes a SIMD barrier instruction with a fourth preset format, the SIMD scheduler of the graphics processor determines the thread group participating in the barrier based on the relationship between the barrier participation mask stored in the SIMD barrier register specified by the SIMD barrier instruction and the mask of the currently active thread, and performs different barrier operations in conjunction with the SIMD scheduling table. If the graphics processor configured with the above architecture acquires and decodes a SIMD barrier concession instruction with a fifth preset format, then the counter specified by the SIMD barrier concession instruction of the graphics processor is incremented by one. When the number of executions of the counter exceeds a preset threshold, the SIMD barrier specified by the SIMD barrier concession instruction is released.
[0006] Furthermore, this invention also provides a high-level language compilation method based on branch instructions. The method includes: for each branch header block that may cause control flow differentiation, the compiler of the graphics processor configured with the architecture inserts a SIMD barrier initialization instruction and a jump instruction into the branch header block; and inserts a SIMD barrier instruction into the common direct post-control block of all branch exits; wherein the jump instruction is used to perform branch control at runtime by combining the condition code stored in the condition code register and the current active thread state; for loops that are determined to have a risk of SIMD deadlock, the compiler of the graphics processor configured with the architecture inserts a SIMD barrier initialization instruction into the loop's pre-loop block; inserts a SIMD barrier yield instruction into loops with a risk of SIMD deadlock; and inserts a SIMD barrier yield instruction into the common direct post-control block of all loop exits. The SIMD barrier instruction is inserted into the dominating block; wherein, the SIMD scheduler determines the thread group participating in the barrier based on the relationship between the barrier participation mask stored in the SIMD barrier register specified by the SIMD barrier instruction and the currently active thread mask stored in the active thread mask register, and performs different barrier operations in conjunction with the SIMD scheduling table; the SIMD barrier yield instruction is used to increment a specified counter by one, and when the number of executions of the counter exceeds a preset threshold, the SIMD barrier specified by the SIMD barrier yield instruction is released; wherein, the principle for determining the risk of SIMD deadlock loop is: the loop exit condition has the potential to cause the thread group-level control flow to diverge; the loop exit condition depends on the shared variable S; there is a write operation to the variable S on the path after the exit block of the loop.
[0007] The present invention has at least the following beneficial effects: This invention improves hardware utilization by allowing the system to flexibly switch to any pending branch and improves efficiency by supporting the active suspension of the current branch to the SIMD scheduler at any position and the retrieval of any branch from the SIMD scheduler. SIMD deadlock is prevented by inserting SIMD barrier initialization instructions, SIMD barrier instructions, and yield instructions into the compiler. Branch control, as well as SIMD deadlock detection and automatic exit, are achieved through the coordination of unconditional jump instructions, conditional jump instructions, SIMD barrier initialization instructions, SIMD barrier instructions, and SIMD barrier yield instructions, significantly reducing the probability of deadlock occurrence. Attached Figure Description
[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0009] Figure 1The overall hardware architecture diagram provided for embodiments of the present invention; Figure 2 This invention provides a SIMD-oriented branch instruction set. Figure 3 A comparative diagram showing the program code with multi-level nested branches provided in the embodiments of the present invention and the assembly code generated by the compiler; Figure 4 for Figure 3 Control flow graph; Figure 5 A comparative diagram showing the program code with a loop branch that has the risk of SIMD deadlock loop provided for embodiments of the present invention and the assembly code generated by the compiler; Figure 6 for Figure 5 The control flow graph. Detailed Implementation
[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0011] Unless otherwise defined, all technical and scientific terms used in the embodiments of this invention have the same meaning as commonly understood by those skilled in the art.
[0012] Example 1 This invention provides an architecture for a graphics processor, which includes: a condition code register (cmsk), an active thread mask register (xmsk), a SIMD barrier register, a SIMD scheduling table, and a SIMD scheduler.
[0013] Please see Figure 1The SIMD system comprises a storage system, an instruction fetch unit, an instruction fetch buffer, a SIMD scheduler, a SIMD scheduler table, an execution unit (ALU), and vector / scalar registers. The instruction fetch buffer includes an instruction cache, a program counter (PC), an active thread mask (xmsk), and condition codes (cmsk). The instruction cache unit stores recently used instructions. The storage system stores data and instructions; it interacts with the system when an instruction cache miss occurs, or when data needs to be loaded or stored. The program counter stores the program address of the thread group currently being fetched, pointing to the next instruction to be read. The active thread mask (xmsk) indicates which threads in the currently fetching thread group are truly active. The condition codes (cmsk) handle control flow differentiation; when a branch is encountered, the cmsk records which threads follow which path. The SIMD scheduler table manages the context of multiple thread groups. The instruction fetch unit retrieves instructions to be executed from the instruction cache. The SIMD scheduler combines the condition codes, active thread masks, barrier participation masks, and the SIMD scheduling table to perform splitting, merging, or scheduling of currently active thread groups, thereby achieving fast switching between multiple threads. The execution unit obtains the corresponding data by reading and writing vector / scalar registers according to the scheduling instructions.
[0014] In one implementation, the graphics processor is a SIMD-based GPU, and all threads within the same thread group execute in lockstep.
[0015] Control flow divergence refers to the phenomenon in a graphics processing unit (GPU) single instruction multiple data architecture (SMI) where different branch conditions lead to different targets for branch jumps in different threads within the same thread group.
[0016] Furthermore, the condition code register is a set of bit-field registers used to store condition codes. Its bit width is equal to the number of threads included in the thread group. Each bit of the condition code corresponds to one thread in the thread group and is used to store the result of the condition judgment. As an example, when 1 indicates that the judgment result of the corresponding thread is true and 0 indicates that the judgment result of the corresponding thread is false, if the condition code is 0110, it means that the judgment result of the thread corresponding to the 0th and 3rd bits of the condition code is false, and the judgment result of the thread corresponding to the 1st and 2nd bits is true.
[0017] Furthermore, the active thread mask register is a bit-field register used to store the active thread mask xmsk. Its bit width is equal to the number of threads included in the thread group. Each bit of the active thread mask xmsk corresponds to a thread in the thread group, controlling whether the corresponding thread is currently active, so that the SIMD scheduler can correctly execute the differentiated control flow. As an example, threads with a mask bit value of 1 in the active thread mask xmsk are currently active threads and will participate in the execution of the current code block; threads with a mask bit value of 0 are currently inactive threads and will not participate in the execution of the current code block.
[0018] The SIMD barrier register is a set of bit-field registers used to store the barrier participation mask. Its bit width is equal to the number of threads in the thread group, and it is used to indicate whether the corresponding thread participates in the barrier. As an example, when 1 indicates that the corresponding thread participates in the barrier and 0 indicates that the corresponding thread does not participate in the barrier, if the barrier participation mask is 0110, it means that the threads corresponding to the 0th and 3rd bits of the barrier participation mask do not participate in the barrier, and the threads corresponding to the 1st and 2nd bits participate in the barrier.
[0019] The SIMD scheduling table is used to store all currently active thread groups. Each thread group corresponds to one entry in the table, and each entry contains a program counter (PC) and an active thread mask (xmsk). It supports inserting or retrieving entries from any position.
[0020] The SIMD scheduler is used to perform splitting, merging, or scheduling of currently active thread groups by combining the condition codes, active thread masks, barrier participation masks, and the SIMD scheduling table.
[0021] Furthermore, the splitting steps performed by the SIMD scheduler include: when it is determined that the control flow has split according to the condition code, the SIMD scheduler splits the current thread group into two new thread groups, selects one of the new thread groups to execute immediately, and stores the other new thread group in the SIMD scheduling table.
[0022] Furthermore, the scheduling steps performed by the SIMD scheduler include: actively saving the currently executing thread group to the SIMD scheduling table at any time, and restoring other thread groups from the SIMD scheduling table to continue execution.
[0023] Furthermore, the merging step performed by the SIMD scheduler includes: when a barrier instruction is encountered and the program counter of the thread group in the SIMD schedule table is the same as the value stored in the program counter of the currently executing thread group, merging the thread group in the SIMD schedule table into the currently executing thread group.
[0024] The hardware uses a SIMD scheduler instead of a traditional SIMD stack. Unlike the stack structure that only supports Last-In-First-Out (LIFO) access, the SIMD scheduler supports inserting or retrieving entries from any position, providing greater scheduling flexibility.
[0025] Furthermore, when the SIMD scheduler is at the barrier instruction, it merges thread groups with the same PC when the barrier condition is met.
[0026] Furthermore, the same thread group synchronously locksteps to execute the same instruction.
[0027] In summary, Embodiment 1 of the present invention enables the system to flexibly switch to any branch to be executed by supporting the active suspension of the current branch to the SIMD scheduler at any position and the retrieval of any branch from the SIMD scheduler to continue execution, thereby improving hardware utilization.
[0028] Example 2 This invention provides a branch execution method based on a graphics processor, the method comprising: S100, the SIMD scheduler retrieves the instruction pointed to by the program counter of the current thread group.
[0029] It should be noted that the branch instructions provided in the embodiments of the present invention include various types, such as unconditional jump instructions, conditional jump instructions, SIMD barrier initialization instructions, SIMD barrier instructions, and SIMD barrier concession instructions. Please refer to [link to relevant documentation]. Figure 2 , Figure 2 It is one implementation of the instruction.
[0030] S200, if the graphics processor configured with the above architecture acquires and decodes an unconditional jump instruction with a first preset format, then the execution unit of the graphics processor controls the program counter to jump to the instruction position specified in the unconditional jump instruction.
[0031] In one implementation, please refer to Figure 2 An unconditional jump instruction with a first preset format is "instruction type [branch target address]". For example, "bra [dest]".
[0032] S300, if the graphics processor configured with the above architecture acquires and decodes a conditional jump instruction with a second preset format, then different jump operations are executed according to the relationship between the condition code cmsk in the condition code register specified in the conditional jump instruction and the current active thread mask xmsk stored in the active thread mask register.
[0033] In one implementation, please refer again. Figure 2The conditional jump instruction with the second preset format is "instruction type condition code cmsk [branch target address]". For example, "bra cmsk, [dest]".
[0034] In one implementation, for the conditional jump instruction, the graphics processor performs different jump operations based on the relationship between the condition code cmsk and the currently active thread mask xmsk, including: S310, if the condition code cmsk is 0, no operation is performed. Here, a condition code cmsk of 0 indicates that none of the current threads meet the condition judgment; therefore, no jump operation is performed.
[0035] S320, if the condition code cmsk is equal to the current active thread mask xmsk, then jump directly to the instruction position specified in the conditional jump instruction.
[0036] S330, otherwise, the current thread group is split into two new thread groups, and the active thread mask xmsk and program counter PC of each new thread group are calculated; the hardware selects to execute one of the thread groups immediately, and saves the active thread mask xmsk and program counter PC of the other thread group to the SIMD scheduling table.
[0037] The condition code `cmsk` can directly divide threads into two groups: one group of threads that meet the condition and another group of threads that do not. Therefore, the current thread group is re-divided into two new thread groups: one group of threads that meet the condition and the other group of threads that do not. The active thread mask for the active thread group that meets the condition is `xmsk&cmsk`, representing the intersection of the condition code `cmsk` and the current active thread mask `xmsk`, i.e., the thread group formed by threads where the corresponding bits of both the condition code `cmsk` and the current active thread mask `xmsk` are 1. Its branch target address is the branch target address "dest" specified in the conditional jump instruction, representing the address of the first instruction to be executed when the condition is true. Among them, the thread group that does not meet the condition satisfies: xmsk&(~cmsk), which represents the difference between the condition code cmsk and the current active thread mask xmsk, that is, the thread group formed by the threads whose corresponding bits of the condition code cmsk are 0 and the corresponding bits of the current active thread mask xmsk are 1; its branch target address is the current program counter automatically incremented by 1, which represents the address of the first instruction to be executed when the condition is not met.
[0038] It should be noted that during compilation, the compiler inserts SIMD barrier instructions into the direct common subsequent control blocks of the branches. This means that when the hardware selects to execute one of the branches, it executes the subsequent control blocks sequentially. However, due to the presence of the SIMD barrier instructions, the hardware cannot continue to execute the code blocks downwards and is triggered to resume the execution of other branches from the SIMD scheduler until the SIMD barrier instructions are removed, and then the subsequent program blocks are executed sequentially.
[0039] S400, if the graphics processor configured with the above architecture acquires and decodes a SIMD barrier initialization instruction with a third preset format, then the currently active thread mask is stored as the initial value of the barrier participation mask in the SIMD barrier register specified in the SIMD barrier initialization instruction, and the count value of the counter specified in the SIMD barrier initialization instruction is initialized. The SIMD barrier initialization instruction, in conjunction with the SIMD barrier instruction, indicates the threads participating in the barrier.
[0040] In one implementation, the SIMD barrier initialization instruction further includes a counter field, used in conjunction with the barrier yield instruction to prevent SMID deadlock. Please refer again to [the relevant documentation]. Figure 2 The SIMD barrier initialization instruction is "instruction mnemonic barrier register counter". For example, "simdbar.init bar, cnt", where the counter cnt is used to count the number of times the loop is executed, and its initial value is set to 0 during initialization. When the graphics processor executes the barrier initialization instruction, it also initializes the counter to 0.
[0041] S500, if the graphics processor configured with the above architecture acquires and decodes a SIMD barrier instruction with a fourth preset format, the SIMD scheduler of the graphics processor determines the thread group participating in the barrier based on the relationship between the barrier participation mask stored in the SIMD barrier register specified by the SIMD barrier instruction and the currently active thread mask xmsk, and performs different barrier operations in conjunction with the SIMD scheduling table. Specifically, the SIMD scheduler checks whether all threads recorded in the barrier register have reached the barrier. If and only if all threads have reached the barrier, it continues to execute the next instruction; otherwise, the SIMD scheduler suspends the execution of the currently executing thread group, saves its context to the SIMD scheduling table, and selects another thread group from the scheduling table to continue execution.
[0042] Please refer to the following again. Figure 2 The SIMD barrier instruction with the fourth preset format is the "instruction mnemonic barrier register". For example, "simdbar.wait bar".
[0043] In one implementation, for SIMD barrier instructions, the thread group participating in the barrier is determined based on the relationship between the barrier register and the currently active thread mask xmsk, and different barrier operations are performed in conjunction with the SIMD scheduling table, including: S510: If the barrier participation mask is the same as the current active thread mask xmsk, no operation is performed, and execution continues downward.
[0044] S520 If the barrier participation mask is different from the current active thread mask xmsk, and the current active thread mask xmsk is not a subset of the barrier participation mask, then an exception is reported.
[0045] It should be noted that if the current active thread mask xmsk and the barrier participation mask satisfy xmsk&(~mask)!=0, it means that the current active thread mask xmsk is not a subset of the barrier participation mask. In other words, the active thread mask xmsk includes threads that are not allowed to be activated in the barrier participation mask, and the current active thread mask xmsk cannot be properly aggregated into the barrier participation mask. In this case, an exception will be reported.
[0046] S530, if the barrier participation mask and the current active thread mask xmsk are different, and the current active thread mask xmsk is a subset of the barrier participation mask, then the thread group corresponding to the current active thread mask xmsk is determined to be the thread group participating in the barrier, and it is checked whether the SIMD scheduling table stores the entry of the PC of the current active thread group: S531, if it does not exist, then the currently executing thread group participating in the barrier is suspended, its context is saved to the SIMD scheduling table, and another thread group is selected from the SIMD scheduling table to continue execution. The context includes the program counter (PC) and the active thread mask (xmsk). Specifically, saving its context to the SIMD scheduling table includes: creating a new table entry containing the PC field and the xmsk field.
[0047] It should be noted that by maintaining the SIMD scheduling table, each entry includes the current program counter (PC) and its current active thread mask (xmsk). The current program counter can save the address of the instruction currently being executed, and the current active thread mask (xmsk) can save which threads are currently active.
[0048] S532, if it exists, then all the thread groups that meet the requirements for suspension found in the SIMD scheduling table will be merged with the currently executing thread group participating in the barrier, and the barrier conditions will be re-evaluated after merging.
[0049] S600, if the graphics processor configured with the architecture obtains and decodes a SIMD barrier concession instruction with a fifth preset format, then the counter specified by the SIMD barrier concession instruction of the graphics processor is incremented by one. When the number of executions counted by the counter exceeds a preset threshold, the SIMD barrier specified by the SIMD barrier concession instruction is released.
[0050] In one implementation, the step of removing the SIMD barrier includes: removing the currently executing thread from the barrier participation mask and reinitializing the counter value to the default value to remove the barrier.
[0051] The SIMD barrier yield instruction is used to resolve SIMD deadlock. Please refer again for details. Figure 2 The SIMD barrier yield instruction is "instruction mnemonic barrier register, counter". The barrier register in the SIMD barrier yield instruction is the same as the barrier register in the SIMD barrier instruction, used to store the barrier participation mask. For example, "simdbar.yieldbar, cnt". It's important to note that the counter cnt specified in the SIMD barrier initialization instruction and the SIMD barrier yield instruction is the same. This barrier yield instruction is set within a loop that carries the risk of deadlock. Each time the loop executes, the counter cnt specified by the barrier yield instruction is incremented by 1. When the counter exceeds a preset threshold, it is determined that the currently executing thread is deadlocked. Therefore, the graphics processor directly removes the currently executing thread from the barrier participation mask, preventing it from participating in subsequent barrier operations.
[0052] In one implementation, the strategy for removing the currently executing thread from the barrier participation mask for the SIMD barrier concession instruction is to clear all bits that have been set in the currently active thread mask xmsk from the barrier participation mask, that is, to execute bar=bar &(~xmsk), where bar represents the barrier participation mask stored in the SIMD barrier register.
[0053] It should be noted that there is no specific order between S300 and S500; the hardware will execute the corresponding operation based on whichever instruction it parses.
[0054] In summary, the branch instruction execution method provided in Embodiment 2 of the present invention implements conventional branch control through unconditional jump instructions, conditional jump instructions, SIMD barrier initialization instructions, and SIMD barrier instructions, and implements SIMD deadlock detection and automatic exit mechanism through SIMD barrier concession instructions, significantly reducing the probability of occurrence.
[0055] Example 3 Please see Figure 3The embodiments of the present invention shown provide a high-level language compilation method for branch instructions that works in conjunction with the architecture of the present invention, the method comprising: P100, the compiler of the graphics processor configured with the architecture inserts a SIMD barrier initialization instruction and a jump instruction in the header block of each branch that may cause control flow divergence, and inserts a SIMD barrier instruction in the common direct post-dominant block of all exits of the branch; wherein, the jump instruction is used to perform branch control at runtime in combination with the condition code stored in the condition code register and the current active thread state.
[0056] Control flow differentiation refers to the situation in the Single Instruction Multiple Data (SIMD) execution model where the same thread group encounters a conditional branch and differentiates into multiple different new thread groups, with each new thread group executing along a different path.
[0057] The head block of a branch is the source of differentiation for conditional branches.
[0058] In this context, the common direct post-dominant block is the closest convergence point that all paths from the same branch head block to the program exit must pass through in the control flow graph.
[0059] P200, the compiler of the graphics processor configured with the aforementioned architecture inserts a SIMD barrier initialization instruction into the pre-loop block of loops deemed to have a risk of SIMD deadlock; inserts a SIMD barrier yield instruction into the loop body; and inserts a SIMD barrier instruction into the common direct post-controlling block of all exit blocks of the loop. The SIMD scheduler determines the thread group participating in the barrier based on the relationship between the barrier participation mask stored in the SIMD barrier register specified by the SIMD barrier instruction and the currently active thread mask stored in the active thread mask register, and performs different barrier operations in conjunction with the SIMD scheduling table. The SIMD barrier yield instruction increments a specified counter; when the counter's execution count exceeds a preset threshold, the SIMD barrier specified by the SIMD barrier yield instruction is released. The criteria for determining the risk of SIMD deadlock are: the loop exit condition may cause a divergence in the control flow at the thread group level; the loop exit condition depends on a shared variable S; and there is a write operation to the variable S on the path after the loop's exit block.
[0060] The preceding block of the loop branch is the only entry channel specifically set up by the compiler for the loop, used to safely insert SIMD barrier initialization instructions.
[0061] In this context, the exit block of a loop refers to the code block corresponding to the jump node that leads from inside the loop to outside the loop.
[0062] Among them, the common direct post-dominant block of all exit blocks of the loop is the closest common post-dominant node that the path from the loop exit block to the program exit must pass through in the control flow graph, and it is the convergence point after the loop exits.
[0063] It should be noted that P100 can guarantee the correct execution of conventional conditional branch control. P200, by inserting SIMD barrier yield instructions into loop branches with the risk of SIMD deadlock, can count the number of loop body executions in real time, ensuring that when a deadlock is detected in a loop branch, it can promptly exit the loop branch and resolve the deadlock state.
[0064] In summary, the compilation method provided in Embodiment 3 of this invention can achieve conventional branch control and ensure the normal execution of conventional branches by inserting SIMD barrier initialization instructions into the branch header block and inserting SIMD barrier instructions into the direct common post-dominant block of the branch. Furthermore, it further reduces the risk of SIMD deadlock by inserting SIMD barrier yield instructions into the loop body with the risk of SIMD deadlock, monitoring the execution count of the loop body in real time, and automatically unlocking the loop when the execution count exceeds a preset threshold by removing the active thread mask xmsk of the currently executing thread group from the barrier participation mask.
[0065] Example 4 This example uses a piece of pseudocode containing nested conditional branches and its corresponding assembly instruction sequence. Please refer to [link to example]. Figure 3 and Figure 4 Both demonstrate how to achieve dynamic splitting, parallel execution, and safe merging of warp using instructions such as SIMD barrier initialization (simdbar.init), conditional jump (bra cmsk), and SIMD barrier (simdbar.wait). This embodiment assumes that a single warp contains 4 threads.
[0066] Figure 3 The program code contains two levels of nested conditional branches, with the active thread mask dynamically changing according to the branch path. For example, in the outer if(idx>0) branch, the active thread mask is 1110, and the inner branch further splits into 1000 (area C) and 0110 (area D). Finally, all paths converge at point G, and the active thread mask returns to 1111.
[0067] Figure 3 The program is compiled into assembly code by the compiler. The compiler will explicitly insert simdbar.init and simdbar.wait to manage branch divergence and merging.
[0068] Figure 3The program starts execution from label L_A, first executing two consecutive cos instructions, keeping all threads active with a mask of 1111. Then, `simdbar.init b0` is executed, storing the current active thread mask 1111 in scalar register b0 as the base mask for final merging at L_G. Next, `bra cmsk L_B` is executed. Assuming the condition code register `cmsk` has a value of 1110 (i.e., threads satisfying `idx > 0`), since `cmsk` is not equal to the current active thread mask 1111, a divergence jump mechanism is triggered. The hardware splits the current warp into two new warps: one warp with an active thread mask of 1110 and an entry address at the jump target address L_B; the other warp with an active thread mask of 0001 and an entry address at the next instruction, L_F. The hardware can choose either one to execute first, for example, choosing to execute L_B, and temporarily pushing the active thread mask (0001) and entry address of the warp corresponding to L_F into the SIMD scheduling table.
[0069] Upon entering L_B, two add instructions are executed first, followed by simdbar.init b1, which stores the current active thread mask 1110 into register b1 for merging point synchronization in the inner branch. Next, bra cmsk L_C is executed. Assuming the inner condition cmsk = 1000 (idx > 2), a diversity jump is triggered again, and the current warp is further split into two new warps with active thread masks and entry addresses {1000, L_C} and {0110, L_D}, respectively. The hardware can choose to execute L_C first and push L_D onto the SIMD scheduling table.
[0070] In L_C, after executing two sub instructions, execution proceeds sequentially to L_E, where it encounters simdbar.wait b1. At this point, the hardware queries the SIMD scheduler table and finds that the L_D branch has not yet reached the barrier, thus not meeting the unlocking condition of simdbar.wait b1. The hardware then suspends the current branch to the SIMD scheduler table and switches to another warp saved in the SIMD scheduler table, such as the previously saved L_D.
[0071] In L_D, the mask is 0110. `mul` is executed twice, then `bra` jumps to L_E and executes `simdbar.waitb1`. At this point, the hardware queries the SIMD scheduling table and finds that both the L_D and L_C branches have reached the barrier, the unlocking condition for `b1` is met, and the program can continue execution. `div` is executed twice more, the inner branch execution is complete, the scheduling is restored to the active thread mask 1110, and the program enters L_G.
[0072] The `simdbar.wait b0` function at L_G, where b0 = 1111, aggregates the L_F and L_E branches, restores the current active thread mask to 1111, and continues executing the last two sin instructions.
[0073] Example 5 As another example, please refer to Figure 5 Figure 6 This embodiment details how the present invention handles loop structures with SIMD deadlock risk, particularly addressing loop control variables that diverge at the warp level, depend on global variables, and have a write operation in the current warp that is related to and subsequently dominates the loop control variable clobber. Figure 5 As shown in the pseudocode, the loop contains a global lock variable `lock`. After a write operation to `lock`, the loop control variable is controlled, and different threads diverge when judging the loop condition.
[0074] Figure 5 The code in the middle is generated after being compiled by the compiler. Figure 6 In the assembly code, when warp reaches L_A, the simdbar.init b0, cnt instruction stores the current active thread mask (1111) into register b0 and initializes the counter cnt.
[0075] The subsequent `bra cmsk L_D` instruction causes some threads to skip the loop body and enter L_D. At L_D, the `simdbar.wait b0` instruction triggers the SIMD barrier. The currently active thread mask does not match the participation mask stored in b0, so these threads can only suspend execution.
[0076] When another group of threads enters loop L_B, the execution of the fma instruction triggers the SIMD barrier yield instruction (simdbar.yield b0, cnt). This instruction increments the counter cnt. When cnt exceeds a preset threshold, the operation b0 = b0 & (~xmsk) is executed to remove the current thread from the barrier participation mask. This operation is equivalent to releasing the barrier b0 in the barrier instruction simdbar.wait b0 at L_D. The previously suspended thread can then execute and unlock the loop at L_B through the atomicExch(&lock,false) instruction.
[0077] Ultimately, the entire thread group successfully executed up to L_E.
[0078] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.
[0079] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.
Claims
1. An architecture for a graphics processor, characterized in that, The architecture includes: The condition code register is a set of bit-field registers used to store condition codes. Its bit width is equal to the number of threads included in the thread group. Each bit of the condition code corresponds to one thread in the thread group and is used to store the result of the condition judgment. The active thread mask register is a bit-field register used to store the active thread mask. Its bit width is equal to the number of threads included in the thread group. Each bit of the active thread mask corresponds to a thread in the thread group and controls whether the corresponding thread is currently active, so that the SIMD scheduler can correctly execute the differentiated control flow. The SIMD barrier register is a set of bit-field registers used to store the barrier participation mask. Its bit width is equal to the number of threads in the thread group and is used to indicate whether the corresponding thread participates in the barrier. The SIMD scheduling table is used to store all currently active thread groups. Each thread group corresponds to one table entry, and each table entry includes a program counter and an active thread mask. It supports inserting or retrieving table entries from any position. The SIMD scheduler is used to perform splitting, merging, or scheduling on currently active thread groups by combining the condition codes, active thread masks, barrier participation masks, and the SIMD scheduling table.
2. The architecture according to claim 1, characterized in that, in, The splitting steps performed by the SIMD scheduler include: When it is determined that the control flow has diverged based on the condition code, the current thread group is split into two new thread groups, one of the new thread groups is selected for immediate execution, and the other new thread group is stored in the SIMD scheduling table.
3. The architecture according to claim 1, characterized in that, in, The scheduling steps performed by the SIMD scheduler include: At any given time, the currently executing thread group is proactively saved to the SIMD scheduler table, and other thread groups are restored from the SIMD scheduler table to continue execution.
4. The architecture according to claim 1, characterized in that, in, The merging steps performed by the SIMD scheduler include: When a barrier instruction is encountered and the program counter of the thread group in the SIMD scheduler is the same as the value stored in the program counter of the currently executing thread group, the thread group in the SIMD scheduler is merged into the currently executing thread group.
5. A branch execution method based on a graphics processor, characterized in that, The method includes: If a graphics processor configured with the architecture described in claim 1 acquires and decodes an unconditional jump instruction with a first preset format, the graphics processor jumps its program counter to the instruction position specified by the unconditional jump instruction. If a graphics processor configured with the architecture described in claim 1 acquires and decodes a conditional jump instruction with a second preset format, then different jump operations are performed according to the relationship between the condition code in the condition code register specified in the conditional jump instruction and the currently active thread mask stored in the active thread mask register. If a graphics processor configured with the architecture described in claim 1 acquires and decodes a SIMD barrier initialization instruction with a third preset format, then the current active thread mask is stored as the initial value of the barrier participation mask in the SIMD barrier register specified by the SIMD barrier initialization instruction, and the counter specified by the SIMD barrier initialization instruction is initialized. If a graphics processor configured with the architecture described in claim 1 acquires and decodes a SIMD barrier instruction with a fourth preset format, the SIMD scheduler of the graphics processor determines the thread group participating in the barrier based on the relationship between the barrier participation mask stored in the SIMD barrier register specified by the SIMD barrier instruction and the mask of the currently active thread, and performs different barrier operations in conjunction with the SIMD scheduling table. If a graphics processor configured with the architecture described in claim 1 acquires and decodes a SIMD barrier concession instruction with a fifth preset format, then the counter specified by the SIMD barrier concession instruction of the graphics processor is incremented by one. When the number of executions counted by the counter exceeds a preset threshold, the SIMD barrier specified by the SIMD barrier concession instruction is released.
6. The method according to claim 5, characterized in that, For the conditional jump instruction, the graphics processor performs different jump operations based on the relationship between the condition code and the currently active thread mask, including: An error is reported if the condition code is not a subset of the mask of the currently active thread; If the condition code is 0, no operation is performed; If the condition code is equal to the mask of the currently active thread, then jump directly to the position specified by the conditional jump instruction; Otherwise, the current thread group is split into two new thread groups, and the active thread mask xmsk and program counter PC of each new thread group are calculated. The hardware selects one of the thread groups to execute immediately and saves the active thread mask xmsk and program counter PC of the other thread group to the SIMD scheduling table.
7. The method according to claim 5, characterized in that, in, The steps of splitting the current thread group into two new thread groups and assigning an active thread mask (xmsk) and program counter (PC) to each thread group also include: The active thread mask of the first new thread group is the intersection of the condition code cmsk and the currently active thread mask xmsk, and the program counter PC is the jump target specified by the conditional jump instruction; The active thread mask for the second new thread group is the difference between the condition code cmsk and the currently active thread mask xmsk, and the program counter PC is the instruction following the conditional jump instruction.
8. The method according to claim 5, characterized in that, For SIMD barrier instructions, the threads participating in the barrier are determined based on the relationship between the barrier participation mask and the currently active thread mask (xmsk), and different barrier operations are performed in conjunction with the SIMD scheduling table, including: If the barrier participation mask is the same as the current active thread mask xmsk, no operation is performed, and execution continues to the next step; If the barrier participation mask is different from the current active thread mask xmsk, and the current active thread mask xmsk is not a subset of the barrier participation mask, then an exception is reported. If the barrier participation mask and the current active thread mask xmsk are different, and the current active thread mask xmsk is a subset of the barrier participation mask, then the thread group corresponding to the current active thread mask xmsk is determined to be the thread group participating in the barrier, and the entry for the current program counter PC is checked in the SIMD scheduling table. If it does not exist, the currently executing thread group participating in the barrier will be suspended and its context will be saved to the SIMD scheduler table. Then, another thread group will be selected from the SIMD scheduler table to continue execution. If they exist, all eligible suspended thread groups found in the SIMD scheduling table will be merged with the currently executing thread group participating in the barrier, and the barrier conditions will be reassessed after the merge.
9. The method according to claim 5, characterized in that, For the SIMD barrier concession instruction, the steps to remove the SIMD barrier include: removing the currently executing thread from the barrier participation mask and reinitializing the counter value to the default value to remove the barrier.
10. A high-level language compilation method based on branch instructions, characterized in that, The method includes: The compiler of the graphics processor configured with the architecture of claim 1 inserts a SIMD barrier initialization instruction and a jump instruction in the branch header block for each branch that may cause control flow divergence, and inserts a SIMD barrier instruction in the common direct post-dominant block of all branch exits; wherein the jump instruction is used to perform branch control at runtime in combination with the condition code stored in the condition code register and the current active thread state. The compiler of the graphics processor configured with the architecture described in claim 1 inserts a SIMD barrier initialization instruction into the pre-loop block of a loop that is determined to have a risk of SIMD deadlock; inserts a SIMD barrier concession instruction into the loop that has a risk of SIMD deadlock; and inserts a SIMD barrier instruction into the common direct post-dominant block of all exit blocks of the loop. The SIMD scheduler determines the thread group participating in the barrier based on the relationship between the barrier participation mask stored in the SIMD barrier register specified by the SIMD barrier instruction and the currently active thread mask stored in the active thread mask register, and performs different barrier operations in conjunction with the SIMD scheduling table. The SIMD barrier concession instruction is used to increment a specified counter by one. When the number of executions of the counter exceeds a preset threshold, the SIMD barrier specified by the SIMD barrier concession instruction is released. The criteria for determining the risk of SIMD deadlock loops are as follows: the loop exit condition may cause a divergence in the control flow at the thread group level; the loop exit condition depends on the shared variable S; and there is a write operation to the variable S on the path after the exit block of the loop.