Buck-Boost converter circuit
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING COMM INST OF TECH
- Filing Date
- 2026-02-03
- Publication Date
- 2026-05-15
AI Technical Summary
Traditional Buck-Boost converters consume a lot of power through the parasitic DC resistance of the inductor when the load current ratio is too high, resulting in low energy conversion efficiency. Furthermore, using an inductor with low parasitic DC resistance occupies a large area.
The first and second switching units are used, and their on and off states are controlled by two-phase alternating periodic digital control signals. Combined with the first and second flying capacitors, the ratio of inductor current to load current is reduced, thereby reducing power consumption on the inductor's parasitic DC resistance.
It improves energy conversion efficiency, reduces system power consumption, and eliminates the need for low parasitic DC resistance inductors that occupy a larger area, ensuring stability and good transient performance over a wide load range.
Smart Images
Figure CN122052522A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of DC-DC converter technology, and more particularly to a Buck-Boost converter circuit. Background Technology
[0002] Buck-Boost converters play a crucial role in portable electronic products. Some modules require a fixed supply voltage, such as 3.3V, and Buck-Boost converters can maintain a constant output voltage despite fluctuations in the input voltage. Lithium-ion batteries are widely used in mobile devices due to their excellent portability and charging capabilities. When a lithium-ion battery discharges, its output voltage gradually drops from 4.2V to 2.8V. To maximize the utilization of the battery voltage to provide a 3.3V supply voltage, Buck-Boost converters become indispensable in the system.
[0003] While keeping the physical size of the device under control, achieving richer functionality and longer battery life is a major challenge currently facing mobile devices. This requires chips to be able to adapt to more complex application scenarios, such as a wider load current range and faster load transient recovery time, while also having higher energy conversion efficiency.
[0004] Figure 1 This shows the traditional Buck-Boost circuit structure. Figure 1 In the circuit shown, switches S1 and S3 are turned on in phase D, and the voltage across inductor L is VIN. Switches S2 and S4 are turned on in phase D', and the voltage across inductor L is -VOUT. According to the volt-second balance theorem, the relationship between the output voltage VOUT and the input voltage VIN is VIN × D = VOUT × (1-D). Therefore, the voltage conversion ratio M between the output voltage VOUT and the input voltage VIN is M = VOUT / VIN = D / (1-D). The relationship between the inductor current IL and the load current IO is IL × (1-D)T = IO × T. The ratio of the inductor current IL to the load current IO is too large, IL / IO = 1 / (1-D) = 1+M, where D represents the duty cycle of phase D in period T. This means that a large amount of power is consumed on the parasitic DC resistance DCR of the inductor, resulting in low energy conversion efficiency. However, using an inductor with lower parasitic DC resistance would require a larger area. Summary of the Invention
[0005] To address the aforementioned technical problems, this invention provides a Buck-Boost converter circuit.
[0006] The present invention provides a Buck-Boost converter circuit, comprising: a first switching unit, a second switching unit, an inductor, a first flying capacitor, and a second flying capacitor;
[0007] The first terminal of the first switching unit is connected to the positive terminal of the power supply to obtain the input voltage. Its second and third terminals are electrically connected to the first flying capacitor. Its fourth terminal is electrically connected to the first terminal of the inductor. Its fifth terminal is electrically connected to the first terminal of the second flying capacitor. Its sixth terminal is connected to the negative terminal of the power supply.
[0008] The first terminal of the second switching unit is electrically connected to the second terminal of the inductor to provide the output voltage, the second terminal of the unit is electrically connected to the second terminal of the second flying capacitor, and the third terminal of the unit is connected to the negative terminal of the power supply.
[0009] The first switching unit and the second switching unit are controlled by two-phase alternating periodic digital control signals to control their on and off states.
[0010] When the digital control signal is in the first phase, the first terminal of the first switching unit is cut off from the second terminal, the first terminal is connected to the third terminal, the second terminal is connected to the fourth terminal, the third terminal is connected to the fifth terminal, the third terminal is cut off from the sixth terminal, the fourth terminal is cut off from the fifth terminal, the first terminal of the second switching unit is connected to the second terminal, and the second terminal is cut off from the third terminal.
[0011] When the digital control signal is in the second phase, the first terminal of the first switching unit is connected to the second terminal, the first terminal is cut off from the third terminal, the second terminal is cut off from the fourth terminal, the third terminal is cut off from the fifth terminal, the third terminal is connected to the sixth terminal, and the fourth terminal is connected to the fifth terminal. The first terminal of the second switching unit is cut off from the second terminal, and the second terminal is connected to the third terminal.
[0012] In one possible implementation, the first switching unit includes a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, and an eighth switching transistor;
[0013] The first end of the first switching transistor is electrically connected to the first end of the second switching transistor as the first end of the first switching unit, and its second end is electrically connected to the first end of the eighth switching transistor as the second end of the first switching unit.
[0014] The second terminal of the second switch is electrically connected to the first terminal of the third switch and the first terminal of the fourth switch, respectively, to form the third terminal of the first switch unit;
[0015] The second end of the third switching transistor serves as the sixth end of the first switching unit;
[0016] The second end of the fourth switch is electrically connected to the first end of the fifth switch to serve as the fifth end of the first switch unit;
[0017] The second end of the fifth switch is electrically connected to the second end of the eighth switch to serve as the fourth end of the first switch unit.
[0018] In one possible implementation, the second switching unit includes a sixth switching transistor and a seventh switching transistor;
[0019] The first end of the sixth switch transistor serves as the first end of the second switch unit, and its second end is electrically connected to the first end of the seventh switch transistor to serve as the second end of the second switch unit.
[0020] The second terminal of the seventh switch transistor serves as the third terminal of the second switch unit.
[0021] In one possible implementation, the first switch and the eighth switch are PMOS transistors;
[0022] The second, third, fourth, fifth, sixth, and seventh switching transistors are NMOS transistors.
[0023] In one possible implementation, the digital control signal is high when it is in the first phase and low when it is in the second phase.
[0024] In one possible implementation, when the digital control signal is in the first phase, the gate voltages of the first switch, the second switch, the fourth switch, and the sixth switch are twice the input voltage, the gate voltages of the third switch, the fifth switch, and the seventh switch are low, and the gate voltage of the eighth switch is the input voltage.
[0025] When the digital control signal is in the second phase, the gate voltages of the first, second, fourth, and sixth switching transistors are low, and the gate voltages of the third, fifth, seventh, and eighth switching transistors are the input voltage.
[0026] In one possible implementation, the gate voltages of the first, second, fourth, and sixth switching transistors are provided by the node voltage at the first terminal of the first switching unit under the drive of the digital control signal; the gate voltages of the third, fifth, and seventh switching transistors are provided by the input voltage under the drive of the digital control signal; and the gate voltage of the eighth switching transistor is directly provided by the input voltage.
[0027] In one possible implementation, the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch, and the eighth switch are low-voltage transistors.
[0028] In one possible implementation, the first terminal of the second switching unit is electrically connected to an RC filter unit.
[0029] The technical solution provided by this invention has at least the following beneficial effects:
[0030] By setting up a first switching unit, a second switching unit, a first flying capacitor, and a second flying capacitor, and controlling the on and off states of the first and second switching units with two-phase alternating periodic digital control signals, the ratio of the converter's inductor current to the load current can be further reduced, thereby reducing the power consumption consumed on the inductor's parasitic DC resistance, improving energy conversion efficiency, and eliminating the need to use an inductor with lower parasitic DC resistance that occupies a larger area. Attached Figure Description
[0031] Figure 1 This is a circuit diagram of a traditional single-mode Buck-Boost circuit;
[0032] Figure 2 This is a schematic diagram of a Buck-Boost converter circuit provided in an embodiment of this application;
[0033] Figure 3 This is a schematic diagram of the working state of a Buck-Boost converter circuit in phase D according to an embodiment of this application;
[0034] Figure 4 This is a schematic diagram of the working state of a Buck-Boost converter circuit in phase D' provided in an embodiment of this application;
[0035] Figure 5 This is a schematic diagram of a Buck-Boost converter circuit implemented using MOSFETs, provided in an embodiment of this application.
[0036] Figure 6 This is a waveform diagram of the driving voltage of each MOS transistor in a Buck-Boost converter circuit provided in an embodiment of this application;
[0037] Figure 7 This is a waveform diagram of the voltage VL across the inductor, the inductor current IL, and the capacitor current IC in a Buck-Boost converter circuit provided in an embodiment of this application;
[0038] Figure 8 This is a schematic diagram of the driving circuit provided in an embodiment of this application;
[0039] In the attached diagram: 10, first switching unit; 20, second switching unit; 30, RC filter unit. Detailed Implementation
[0040] To enhance understanding of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. These embodiments are only used to explain the present invention and do not constitute a limitation on the scope of protection of the present invention.
[0041] Please refer to Figures 2 to 8 The present invention provides a Buck-Boost converter circuit, comprising: a first switching unit 10, a second switching unit 20, an inductor L, a first flying capacitor CF1, and a second flying capacitor CF2;
[0042] The first terminal of the first switching unit 10 is connected to the positive terminal of the power supply to obtain the input voltage VIN. Its second terminal (as the SW1 switching node) and third terminal (as the SW2 switching node) are electrically connected to the first flying capacitor CF1. Its fourth terminal (as the SW3 switching node) is electrically connected to the first terminal of the inductor L. Its fifth terminal (as the SW4 switching node) is electrically connected to the first terminal of the second flying capacitor CF2. Its sixth terminal is connected to the negative terminal of the power supply.
[0043] The first end of the second switching unit 20 is electrically connected to the second end of the inductor L to provide the output voltage VOUT, its second end (as the SW5 switching node) is electrically connected to the second end of the second flying capacitor CF2, and its third end is connected to the negative terminal of the power supply.
[0044] The first switching unit 10 and the second switching unit 20 are controlled by a periodic digital control signal VD that alternates between two phases (the first phase, i.e., phase D, and the second phase, i.e., phase D').
[0045] When the digital control signal VD is in the first phase D, the first terminal of the first switching unit 10 is cut off from the second terminal, the first terminal is connected to the third terminal, the second terminal is connected to the fourth terminal, the third terminal is connected to the fifth terminal, the third terminal is cut off from the sixth terminal, and the fourth terminal is cut off from the fifth terminal. The first terminal of the second switching unit 20 is connected to the second terminal, and the second terminal is cut off from the third terminal.
[0046] When the digital control signal VD is in the second phase D', the first end and the second end of the first switching unit 10 are turned on, the first end and the third end are turned off, the second end and the fourth end are turned off, the third end and the fifth end are turned off, the third end and the sixth end are turned on, the fourth end and the fifth end are turned on, the first end and the second end of the second switching unit 20 are turned off, and the second end and the third end are turned on.
[0047] In this embodiment, the first switching unit 10 can be constructed by 6 power switches, and the second switching unit 20 can be constructed by 2 power switches. The inductor L can adopt a conventional model applied to a Buck-Boost converter. The first flying capacitor CF1 and the second flying capacitor CF2 can adopt conventional capacitors.
[0048] The Buck-Boost converter circuit provided by this application can achieve single-mode control within the voltage conversion range, that is, there is no need to perform mode switching when the input voltage VIN is different, avoiding the design problem of the mode switching circuit and the problem of large voltage fluctuations in the output caused by it. The switching of the first switching unit 10 and the second switching unit 20 only has two phases, namely the D phase and the D' phase.
[0049] In the Buck-Boost converter circuit of the present invention, when the digital control signal VD is in the first phase D, the node voltage of the SW1 switching node is doubled to 2VIN through its own charge pump structure. The voltage across the inductor L is 2VIN–VOUT, and the voltage across the second flying capacitor CF2 is charged to VIN-VOUT, and the second flying capacitor CF2 provides a path of current to the line where the output voltage VOUT is located within this phase. When the digital control signal VD is in the second phase D', the voltage across the first flying capacitor CF1 is charged to VIN, the inductor L and the second flying capacitor CF2 are in series, and the voltage across the inductor L is VIN–2VOUT. At this time, the inductor L supplies current to the load.
[0050] Combined Figure 7 , the voltages across the inductor L in the D phase and the D' phase are 2VIN-VOUT and VIN-2VOUT respectively. Since (2VIN-VOUT)×D=(2VOUT-VIN)×(1-D), the voltage conversion ratio M=VOUT / VIN=(1+D) / (2-D) of the converter can be calculated, where 0<D<1, and D represents the duty cycle of the D phase within the period T.
[0051] By calculating the energy transferred to the output load through the current in each phase, the relationship between the average inductor current IL and the load current IO can be calculated. For example, when the circuit enters steady state, the second flying capacitor CF2 maintains its charge balance after one cycle. In phase D', the current in the second flying capacitor CF2 flows from the SW5 switching node to the SW4 switching node. At this time, the current in the second flying capacitor CF2 is the same as the inductor current IL, and the transferred charge is IL×(1-D)T. Therefore, in phase D, the charge transferred by the current in the second flying capacitor CF2 is also IL×(1-D)T. Thus, the energy transferred in phase D within one cycle T is IL×DT+IL×(1-D)T, and the energy transferred in phase D' is IL×(1-D)T. The sum of the two is IO×T. From IL×DT+IL×(1-D)T+IL×(1-D)T=IO×T, we get IL×(2-D)T=IO×T. Finally, we can obtain the relationship between the average inductor current and the load current of the converter as IL / IO=1 / (2-D)=(M+1) / 3. The relationship between the average inductor current and the load current of the traditional structure is IL / IO=M+1. Therefore, this converter can significantly reduce the large inductor loss caused by the high DCR value of the inductor and reduce the system power consumption.
[0052] In the high-performance Buck-Boost converter circuit of this invention, since this structure avoids the discontinuity of energy transfer from the inductor current to the load in the traditional structure, the inductor L transfers energy to the load in each phase operating state. The resulting right half-plane zero position is much larger than that of the traditional Buck-Boost structure and also much larger than the system bandwidth, ensuring that the structure has good stability over a wide load range and exhibits good transient effect in load dynamic switching, without the right half-plane zero problem.
[0053] In practical implementation, the power supply in this application can be a lithium battery, with an input voltage VIN of 4.2V to 2.8V and an output voltage VOUT of 3.3V. The Buck-Boost converter circuit provided in this application has simple control, excellent transient performance, and high energy conversion efficiency.
[0054] In one possible implementation, the first switching unit 10 includes a first switching transistor S1, a second switching transistor S2, a third switching transistor S3, a fourth switching transistor S4, a fifth switching transistor S5, and an eighth switching transistor S8.
[0055] The first end of the first switch transistor S1 is electrically connected to the first end of the second switch transistor S2 as the first end of the first switch unit 10, and its second end is electrically connected to the first end of the eighth switch transistor S8 as the second end of the first switch unit 10.
[0056] The second terminal of the second switch S2 is electrically connected to the first terminal of the third switch S3 and the first terminal of the fourth switch S4, respectively, to serve as the third terminal of the first switch unit 10.
[0057] The second end of the third switch S3 serves as the sixth end of the first switch unit 10;
[0058] The second end of the fourth switch S4 is electrically connected to the first end of the fifth switch S5 to serve as the fifth end of the first switch unit 10.
[0059] The second end of the fifth switch S5 is electrically connected to the second end of the eighth switch S8 to serve as the fourth end of the first switch unit 10.
[0060] In this embodiment, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and the eighth switch S8 can be conventional MOSFETs. The drive signals for the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and the eighth switch S8 are VG1, VG2, VG3, VG4, VG5, and VIN, respectively. The voltage range of VG1, VG2, and VG4 is 0 or SW1 (i.e., the node voltage of the SW1 switching node). The voltage range of VG3 and VG5 is 0 or VIN. The eighth switch S8 is directly driven by VIN.
[0061] In one possible implementation, the second switching unit 20 includes a sixth switching transistor S6 and a seventh switching transistor S7;
[0062] The first end of the sixth switch S6 serves as the first end of the second switch unit 20, and its second end is electrically connected to the first end of the seventh switch S7 to serve as the second end of the second switch unit 20.
[0063] The second terminal of the seventh switch S7 serves as the third terminal of the second switch unit 20.
[0064] In this embodiment, the sixth switch S6 and the seventh switch S7 can be conventional MOSFETs. The drive signals for the sixth switch S6 and the seventh switch S7 are VG6 and VG7, respectively. The voltage range of VG6 is 0 or SW1. The voltage range of VG7 is 0 or VIN.
[0065] In one possible implementation, the first switch S1 and the eighth switch S8 are PMOS transistors;
[0066] The second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, and the seventh switch S7 are NMOS transistors.
[0067] In this embodiment, the PMOS transistor is a conventional P-type MOS transistor, and the NMOS transistor is a conventional N-type MOS transistor.
[0068] In one possible implementation, the digital control signal VD is high when it is in the first phase D and low when it is in the second phase D'.
[0069] In this embodiment, the digital control signal VD is a periodic signal. When a new cycle begins, the digital control signal VD rises to a high level. After a dead time, the digital control signal VD falls to a low level. During this stage (when the digital control signal VD is high), the circuit operates in the first phase, i.e., the D-phase operating state. After the first phase operating state ends, the circuit enters the second phase operating state, i.e., the D'-phase operating state. The digital control signal VD falls to a low level, and after a dead time, the digital control signal VD rises to a high level. During this stage (when the digital control signal VD is low), the circuit operates in the second phase, i.e., the D'-phase operating state.
[0070] In phase D operation: The gate voltage VG1 of the first switch S1 is obtained from the digital control signal VD through a level conversion circuit and a drive circuit. At this time, VG1 = SW1, the first switch S1 is off, and the node voltage of switch node SW1 is 2VIN; The gate voltage VG2 of the second switch S2 is obtained from the digital control signal VD through a level conversion circuit and a drive circuit. At this time, VG2 = SW1 = 2VIN, the second switch S2 is on, and the node voltage of switch node SW2 is VIN; The gate voltage VG3 of the third switch S3 is first obtained from the digital control signal VD through a delay dead time and then through an inverter to obtain the VD' signal, and then through the drive circuit. At this time, VG3 = 0, and the third switch S3 is off; The gate voltage VG4 of the fourth switch S4 is obtained from the digital control signal VD through a level conversion circuit and a drive circuit. VG4=SW1=2VIN, the fourth switch S4 is turned on, and the node voltage of switch node SW4 is VIN; the gate voltage VG5 of the fifth switch S5 is obtained by the VD' signal through the driving circuit. At this time, VG5=0, and the third switch S5 is turned off; the gate voltage VG6 of the sixth switch S6 is obtained by the digital control signal VD through the level conversion circuit and the driving circuit. At this time, VG6=SW1=2VIN, the sixth switch S6 is turned on, and the node voltage of switch node SW5 is VOUT; the gate voltage VG7 of the seventh switch S7 is obtained by the VD' signal through the driving circuit. At this time, VG7=0, and the seventh switch S7 is turned off; the gate voltage VG8 of the eighth switch S8 is VIN. At this time, VG8=VIN, SW1=2VIN, the eighth switch S8 is turned on, and the node voltage of switch node SW3 is 2VIN. Therefore, in the D-phase operating state, the node voltage of switch node SW1 is 2VIN, the node voltage of switch node SW2 is VIN, the node voltage of switch node SW3 is 2VIN, the node voltage of switch node SW4 is VIN, the node voltage of switch node SW5 is VOUT, the voltage across inductor L is VL = 2VIN - VOUT, the inductor current rises with a slope of (2VIN - VOUT) / L and flows to the line where the output voltage VOUT is located, the current IC1 on the first flying capacitor CF1 is the inductor current IL, that is, |IC1| = |IL|, the voltage across the second flying capacitor CF2 is VIN - VOUT, and the current on the second flying capacitor CF2 also flows to the line where the output voltage VOUT is located.
[0071] In phase D': The gate voltage VG1 of the first switch S1 is obtained by the digital control signal VD through a level conversion circuit and a drive circuit. At this time, VG1=0, the first switch S1 is turned on, and the node voltage of switch node SW1 is VIN; The gate voltage VG2 of the second switch S2 is obtained by the digital control signal VD through a level conversion circuit and a drive circuit. At this time, VG2=0, and the second switch S2 is turned off; The gate voltage VG3 of the third switch S3 is obtained by the VD' signal through a drive circuit. At this time, VG3=VIN, the third switch S3 is turned on, and the node voltage of switch node SW2 is 0; The gate voltage VG4 of the fourth switch S4 is obtained by the digital control signal VD through a level conversion circuit and a drive circuit. At this time, VG4=0, and the fourth switch S4 is turned off. The gate voltage VG5 of the fifth switch S5 is obtained by the VD' signal through the driving circuit. At this time, VG5=VIN, and the third switch S5 is turned on. The gate voltage VG6 of the sixth switch S6 is obtained by the digital control signal VD through the level conversion circuit and the driving circuit. At this time, VG6=0, and the sixth switch S6 is turned off. The gate voltage VG7 of the seventh switch S7 is obtained by the VD' signal through the driving circuit. At this time, VG7=VIN, and the seventh switch S7 is turned on. The node voltage of switch node SW5 is 0, and the node voltage of switch node SW4 is VIN-VOUT. The gate voltage VG8 of the eighth switch S8 is VIN. At this time, VG8=VIN, SW1=VIN, and the eighth switch S8 is turned off. The node voltage of switch node SW3 is VIN-VOUT. Therefore, in the D' phase operating state, the node voltage of switch node SW1 is VIN, the node voltage of switch node SW2 is 0, the node voltage of switch node SW3 is VIN-VOUT, the node voltage of switch node SW4 is VIN-VOUT, the node voltage of switch node SW5 is 0, the voltage across inductor L is VL=VIN-2VOUT, the inductor current decreases with a slope of (2VOUT-VIN) / L and flows to the line where the output voltage VOUT is located, the voltage across the first flying capacitor CF1 is VIN, and the current IC2 on the second flying capacitor CF2 is the inductor current IL, i.e., |IC2|=|IL|.
[0072] In practical implementation, the dead time delay can be achieved using conventional delay circuits or existing delay units. The drive circuit can be implemented using, for example... Figure 8The circuit structure shown consists of an NPN transistor Q1, a PNP transistor Q2, resistors R1 and R2. For example: when obtaining VG1, V1=VD, VCC=SW1, V2=VG1; when obtaining VG2, V1=VD, VCC=SW1, V2=VG2; when obtaining VG3, V1=VD', VCC=VIN, V2=VG3; when obtaining VG4, V1=VD, VCC=SW1, V2=VG4; when obtaining VG5, V1=VD', VCC=VIN, V2=VG5; when obtaining VG6, V1=VD, VCC=SW1, V2=VG6; when obtaining VG7, V1=VD', VCC=VIN, V2=VG7.
[0073] In one possible implementation, when the digital control signal VD is in the first phase D, the gate voltages of the first switch S1, the second switch S2, the fourth switch S4, and the sixth switch S6 are twice the input voltage VIN, the gate voltages of the third switch S3, the fifth switch S5, and the seventh switch S7 are low, and the gate voltage of the eighth switch S8 is the input voltage VIN.
[0074] When the digital control signal VD is in the second phase D', the gate voltages of the first switch S1, the second switch S2, the fourth switch S4, and the sixth switch S6 are at a low level, and the gate voltages of the third switch S3, the fifth switch S5, the seventh switch S7, and the eighth switch S8 are the input voltage VIN.
[0075] In one possible implementation, the gate voltages of the first switch S1, the second switch S2, the fourth switch S4, and the sixth switch S6 are provided by the node voltage at the first terminal of the first switching unit 10 under the drive of the digital control signal VD; the gate voltages of the third switch S3, the fifth switch S5, and the seventh switch S7 are provided by the input voltage VIN under the drive of the digital control signal VD; and the gate voltage of the eighth switch S8 is directly provided by the input voltage VIN.
[0076] In one possible implementation, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 are all low-voltage transistors, i.e., low-voltage switching transistors, with a maximum voltage stress of less than 5V. It should be noted that many existing Buck-Boost structures also achieve single-mode control and reduced inductor current, but their structures must use high-voltage switching transistors to withstand higher voltage stress. The low-voltage switching transistors used in this application have lower on-resistance, thus resulting in less power loss and voltage drop caused by current flowing through the switching transistors.
[0077] In one possible implementation, the first terminal of the second switching unit 20 is electrically connected to an RC filter unit 30.
[0078] In this embodiment, the RC filter unit 30 can be obtained by connecting the filter resistor RL and the filter capacitor CL in parallel, with one end connected to the first end of the second switch unit 20 and the other end connected to the negative terminal of the power supply.
[0079] The above embodiments should not limit the present invention in any way. All technical solutions obtained by equivalent substitution or equivalent conversion fall within the protection scope of the present invention.
Claims
1. A Buck-Boost converter circuit, characterized in that, include: First switching unit, second switching unit, inductor, first flying capacitor, second flying capacitor; The first terminal of the first switching unit is connected to the positive terminal of the power supply to obtain the input voltage. Its second and third terminals are electrically connected to the first flying capacitor. Its fourth terminal is electrically connected to the first terminal of the inductor. Its fifth terminal is electrically connected to the first terminal of the second flying capacitor. Its sixth terminal is connected to the negative terminal of the power supply. The first terminal of the second switching unit is electrically connected to the second terminal of the inductor to provide the output voltage, the second terminal of the unit is electrically connected to the second terminal of the second flying capacitor, and the third terminal of the unit is connected to the negative terminal of the power supply. The first switching unit and the second switching unit are controlled by two-phase alternating periodic digital control signals to control their on and off states. When the digital control signal is in the first phase, the first terminal of the first switching unit is cut off from the second terminal, the first terminal is connected to the third terminal, the second terminal is connected to the fourth terminal, the third terminal is connected to the fifth terminal, the third terminal is cut off from the sixth terminal, the fourth terminal is cut off from the fifth terminal, the first terminal of the second switching unit is connected to the second terminal, and the second terminal is cut off from the third terminal. When the digital control signal is in the second phase, the first terminal of the first switching unit is connected to the second terminal, the first terminal is cut off from the third terminal, the second terminal is cut off from the fourth terminal, the third terminal is cut off from the fifth terminal, the third terminal is connected to the sixth terminal, and the fourth terminal is connected to the fifth terminal. The first terminal of the second switching unit is cut off from the second terminal, and the second terminal is connected to the third terminal.
2. The Buck-Boost converter circuit according to claim 1, characterized in that, The first switching unit includes a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, and an eighth switching transistor; The first end of the first switching transistor is electrically connected to the first end of the second switching transistor as the first end of the first switching unit, and its second end is electrically connected to the first end of the eighth switching transistor as the second end of the first switching unit. The second terminal of the second switch is electrically connected to the first terminal of the third switch and the first terminal of the fourth switch, respectively, to form the third terminal of the first switch unit; The second end of the third switching transistor serves as the sixth end of the first switching unit; The second end of the fourth switch is electrically connected to the first end of the fifth switch to serve as the fifth end of the first switch unit; The second end of the fifth switch is electrically connected to the second end of the eighth switch to serve as the fourth end of the first switch unit.
3. The Buck-Boost converter circuit according to claim 2, characterized in that, The second switching unit includes a sixth switching transistor and a seventh switching transistor; The first end of the sixth switch transistor serves as the first end of the second switch unit, and its second end is electrically connected to the first end of the seventh switch transistor to serve as the second end of the second switch unit. The second terminal of the seventh switch transistor serves as the third terminal of the second switch unit.
4. The Buck-Boost converter circuit according to claim 3, characterized in that, The first switch and the eighth switch are PMOS transistors; The second, third, fourth, fifth, sixth, and seventh switching transistors are NMOS transistors.
5. The Buck-Boost converter circuit according to claim 4, characterized in that, The digital control signal is high when it is in the first phase and low when it is in the second phase.
6. The Buck-Boost converter circuit according to claim 5, characterized in that, When the digital control signal is in the first phase, the gate voltages of the first switch, the second switch, the fourth switch, and the sixth switch are twice the input voltage, the gate voltages of the third switch, the fifth switch, and the seventh switch are at a low level, and the gate voltage of the eighth switch is the input voltage. When the digital control signal is in the second phase, the gate voltages of the first, second, fourth, and sixth switching transistors are low, and the gate voltages of the third, fifth, seventh, and eighth switching transistors are the input voltage.
7. The Buck-Boost converter circuit according to claim 3, characterized in that, The gate voltages of the first, second, fourth, and sixth switching transistors are provided by the node voltage at the first terminal of the first switching unit under the drive of the digital control signal. The gate voltages of the third, fifth, and seventh switching transistors are provided by the input voltage under the drive of the digital control signal. The gate voltage of the eighth switching transistor is directly provided by the input voltage.
8. The Buck-Boost converter circuit according to claim 3, characterized in that, The first, second, third, fourth, fifth, sixth, seventh, and eighth switching transistors are low-voltage transistors.
9. The Buck-Boost converter circuit according to claim 1, characterized in that, An RC filter unit is electrically connected to the first terminal of the second switching unit.