Multi-phase power supply and control circuit thereof

Abstract

The invention discloses a multiphase power supply and a control circuit thereof, the multiphase power supply comprises a loop control module and a plurality of logic control modules which are connected to form a daisy chain architecture, and the plurality of logic control modules adopt a time division multiplexing mode to sequentially respond to jump edges of output signals of the loop control module to generate switching control signals of the phases, and time sequence information is transmitted between adjacent logic control modules through phase transmission signals, so that accurate staggered conduction of each phase switch is realized. According to the multi-phase power supply, phase dislocation control among a plurality of power level circuits can be realized only by adopting one control loop, the circuit structure is simple, and circuit design simplification and circuit cost reduction are facilitated.

Description

Technical Field

[0001] This invention relates to the field of switching power supply technology, and more specifically, to a multiphase power supply and its control circuit. Background Technology

[0002] The exponential growth of Internet of Things (IoT) cloud services has driven significant advancements in data centers, networks, and telecommunications equipment. At the same time, the ever-increasing volume of data and information poses new challenges to the processing efficiency of data center servers. Therefore, how to efficiently power and cool these devices while minimizing power consumption has become an important issue in the field of power technology.

[0003] Multiphase power supplies utilize a technique that connects multiple power stage circuits in parallel and distributes the switching modulation process across different phases to achieve power supply regulation and control. In a multiphase power supply, the PWM (pulse width modulation) signals between phases can be identical or staggered by a certain phase, ensuring that the fluctuation frequency observed at the output and input is the product of the switching frequency of each phase and the number of phases. This reduces the need for filter capacitors and lowers the current surge to the input, while also accelerating the response to load changes. Due to their superior performance, multiphase power supplies are widely used in high-current, low-voltage power supply scenarios such as high-performance CPUs, GPUs, and AI accelerator chips.

[0004] Figure 1 A schematic circuit diagram of a multiphase power supply according to the prior art is shown. (e.g.) Figure 1 As shown, the existing multiphase power supply 100 consists of multiple power stage circuits 101~104 connected in parallel. Figure 1 The system consists of a 4-phase multiphase power supply, multiple slope compensation modules 111~114, multiple PWM comparators 121~124, an error amplifier 130, and feedback resistors R1 and R2.

[0005] Each power stage circuit includes a driver, switching transistors HS and LS, an inductor Lx, and an output capacitor Cout. Switches HS and LS are connected between the input voltage Vin and ground. The first terminal of inductor Lx is connected to the midpoint between switches HS and LS, and the second terminal is connected to the first terminal of output capacitor Cout. The second terminal of output capacitor Cout is grounded. The drivers in each power stage circuit 101-104 receive switching control signals PWM1-PWM4 from PWM comparators 121-124, and control the corresponding transistors to turn on and off according to the received switching control signals, charging the output capacitor Cout of that phase to generate the output voltage Vo1-Vo4 of that phase. The output voltages Vo1-Vo4 are combined into a single output voltage Vout to drive the load.

[0006] In the existing multiphase power supply 100, the slope compensation modules 111-114 generate slope signals Ramp1-Ramp4 for each phase to stabilize current control. The error amplifier 130 compares the feedback signal Vfb of the output voltage Vout with the reference voltage signal Vref and, after compensation, outputs the loop error signal EA. This signal EA is input to the PWM comparators 121-124 of each phase. The PWM comparators 121-124 of each phase compare the loop error signal EA with the slope signals Ramp1-Ramp4 of that phase to generate corresponding switching control signals PWM1-PWM4 to adjust the switching duty cycle of the power stage circuit of each phase, thereby achieving precise control of the output voltage Vout.

[0007] Existing multiphase power supplies require the same number of PWM comparators in the circuit as the power stage circuit. This not only increases the chip's circuit size, significantly increasing its area and power consumption, but also necessitates the introduction of additional built-in clock modules and phase shift logic control circuits to achieve phase shift control, further increasing system complexity and static power consumption. As the number of system phases increases, existing solutions lead to a linear or even disproportionate increase in system area and power consumption, severely impacting the applicability of multiphase power supplies in high-integration, low-power applications. Summary of the Invention

[0008] In view of the above problems, the purpose of this invention is to provide a multiphase power supply and its control circuit, which can realize phase-shift control between multiple power stage circuits using only one control loop. The circuit structure is simple, which is beneficial to simplifying circuit design and reducing circuit cost.

[0009] According to one aspect of the present invention, a control circuit for a multiphase power supply is provided. The multiphase power supply includes multiple power stage circuits connected in parallel. The control circuit includes: a loop control module for generating a loop compensation signal based on the output voltage and reference voltage signal of the multiphase power supply; and multiple logic control modules connected in a daisy-chain architecture, each connected to a corresponding power stage circuit. Each logic control module has a loop control terminal, a first synchronization terminal, and a second synchronization terminal. The loop control terminal is used to receive the loop compensation signal. The first synchronization terminal is connected to the second synchronization terminal of the preceding logic control module to receive the phase transmission signal of the preceding phase. The second synchronization terminal is connected to the first synchronization terminal of the following logic control module to transmit the phase transmission signal of the current phase. Each logic control module is enabled when it receives the phase transmission signal of the preceding phase, and after being enabled, generates a switching control signal for the corresponding power stage circuit and the phase transmission signal of the current phase based on the loop compensation signal.

[0010] Optionally, each of the logic control modules is configured to trigger the high-side switch of the corresponding power stage circuit to turn on according to the first edge of the loop compensation signal after the enable is turned on, and to generate the phase transmission signal of the current phase when the second edge of the loop compensation signal or the first preset time arrives.

[0011] Optionally, each of the logic control modules is further configured to turn off the high-side switch after the on-time of the high-side switch of the corresponding power stage circuit reaches a second preset time, wherein the second preset time is dynamically adjusted based on the ratio of the input voltage to the output voltage of the multiphase power supply.

[0012] Optionally, one of the plurality of logic control modules is configured as a master logic control module, and the remaining logic control modules are configured as slave logic control modules. The master logic control module is further configured to enable the daisy chain when it receives an external start signal, and after being enabled, generate a switching control signal for the corresponding power stage circuit and a phase transfer signal for the current phase according to the loop compensation signal, so as to realize the initial start of the daisy chain.

[0013] Optionally, each of the plurality of logic control modules includes: a first logic unit, which receives a master-slave configuration signal, an external start signal, a phase transmission signal of the previous phase, and the loop compensation signal, and configures the logic control module as a master logic control module or a slave logic control module according to the master-slave configuration signal. When the logic control module is configured as a master logic control module, the first logic unit is used to generate a set trigger signal according to the external start signal, the phase transmission signal of the previous phase, or the loop compensation signal. When the logic control module is configured as a slave logic control module, the first logic unit generates the set trigger signal according to the phase transmission signal of the previous phase and the loop compensation signal; and a first D flip-flop, which is used to generate the set trigger signal according to the set trigger signal. The system includes: a signal outputting a conduction enable signal; a reset unit, configured to output a reset trigger signal to the first D flip-flop when the second edge of the loop compensation signal or a first preset time is reached, wherein the first D flip-flop is configured to reset the conduction enable signal according to the reset trigger signal; a second logic unit, configured to perform a logical AND operation between the conduction enable signal and the loop compensation signal, and generate a set control signal according to the operation result; a timing unit, configured to start timing when the set control signal is valid, and generate a reset control signal when the timing reaches the second preset time; and a signal modulation unit, configured to generate a switch control signal according to the set control signal and the reset control signal to drive the corresponding power stage circuit.

[0014] Optionally, the first logic unit includes: a first AND gate for performing a logical AND operation on the phase transfer signal of the previous phase and the loop compensation signal; a first pulse unit for converting the external start signal into a rising edge triggered first pulse signal; a second AND gate for performing a logical AND operation on the master-slave configuration signal and the first pulse signal; a first OR gate for performing a logical OR operation on the output signal of the first AND gate and the output signal of the second AND gate; and a second pulse unit for converting the output signal of the first OR gate into a rising edge triggered set trigger signal.

[0015] Optionally, the clock terminal of the first D flip-flop is used to receive the set trigger signal, the data terminal is connected to a high level, the reset terminal receives the reset trigger signal, and the first output terminal is used to output the turn-on enable signal. The plurality of logic control modules further include: a second D flip-flop, whose clock terminal is connected to the second output terminal of the first D flip-flop, the data terminal is connected to a high level, the reset terminal receives the switch control signal of the next-level logic control module, and the output terminal is used to output the phase transfer signal.

[0016] Optionally, the reset unit includes: an inverter for generating an inverted signal of the loop compensation signal; a delay unit for delaying the first edge of the turn-on enable signal; and a second OR gate for performing a logical OR operation on the output signal of the inverter and the output signal of the delay unit to generate the reset trigger signal.

[0017] Optionally, the second logic unit includes: a third pulse unit for converting the turn-on enable signal into a rising edge triggered third pulse signal; and a third AND gate for performing a logical AND operation on the third pulse signal and the loop compensation signal to generate the set control signal.

[0018] Optionally, the timing unit includes: a current generating module for generating a charging current based on the input voltage; a charging capacitor, the first terminal of which is connected to the current generating module to receive the charging current, and the second terminal of which is grounded; a reset transistor connected between the first terminal of the charging capacitor and ground, controlled to be turned on by the set control signal to discharge the charging capacitor; and a comparator for comparing the voltage across the charging capacitor with the output voltage, and generating the reset control signal based on the comparison result.

[0019] Optionally, the signal modulation unit includes: an SR latch, with a set terminal for receiving the set control signal and a reset terminal for receiving the reset control signal; a fourth AND gate for performing a logical AND operation on the loop compensation signal and the turn-on enable signal; and a third OR gate for performing a logical OR operation on the output signal of the fourth AND gate and the output signal of the SR latch to generate the switch control signal.

[0020] According to another aspect of the present invention, a multiphase power supply is provided, comprising: a plurality of power stage circuits connected in parallel; and the control circuit described above.

[0021] In summary, the multiphase power supply based on the COT control architecture provided in this embodiment of the invention includes multiple logic control modules connected in a daisy-chain architecture. These modules sequentially respond to the transition edges of the loop control module's output signal using a time-division multiplexing method to generate the switching control signal for their respective phases. Timing information is transmitted between adjacent logic control modules via phase transfer signals, thereby achieving precise interleaved conduction of each phase switch and ensuring efficient system operation across a wide load range. Compared to existing multiphase power supplies, only one control loop is needed to achieve interleaved control between multiphase power stage circuits. This eliminates the need for separate PWM comparators and ramp signal generation circuits in each phase power stage circuit, significantly simplifying the circuit structure and reducing system complexity and chip area, while also lowering power consumption and cost. Attached Figure Description

[0022] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0023] Figure 1 A schematic circuit diagram of a multiphase power supply according to the prior art is shown.

[0024] Figure 2 A schematic circuit diagram of a multiphase power supply according to an embodiment of the present invention is shown.

[0025] Figure 3 A schematic circuit diagram of a loop control module according to an embodiment of the present invention is shown.

[0026] Figure 4 A schematic circuit diagram of a logic control module according to an embodiment of the present invention is shown.

[0027] Figure 5 A schematic circuit diagram of a timing unit according to an embodiment of the present invention is shown.

[0028] Figure 6 A timing diagram of a multiphase power supply according to an embodiment of the present invention is shown.

[0029] Figure 7 The diagram shows the current waveform of a multiphase power supply according to an embodiment of the present invention. Detailed Implementation

[0030] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0031] It should be understood that, in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by an electrical or electromagnetic link. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to the other element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0032] In this application, the switching transistor is a transistor that operates in switching mode to provide a current path, including a bipolar transistor or a field-effect transistor. The first terminal and the second terminal of the switching transistor are respectively the high potential terminal and the low potential terminal on the current path, and the control terminal is used to receive a drive signal to control the switching transistor to turn on and off.

[0033] This invention can be presented in various forms, some of which will be described below.

[0034] Figure 2 A schematic circuit diagram of a multiphase power supply according to an embodiment of the present invention is shown. The multiphase power supply of the present invention includes N power stage circuits and a control circuit arranged in parallel, where N is an integer greater than 1. The N power stage circuits share the same control loop. The control circuit is used to control the operating timing and charging time of the N power stage circuits to jointly provide the output voltage Vout.

[0035] Specifically, refer to Figure 2 The multiphase power supply 200 includes N parallel power stage circuits 201~20N (N is the number of phases in the multiphase power supply, and N is an integer greater than 1), and the explanation is based on the example of each power stage circuit being a buck converter.

[0036] In some embodiments, each power stage circuit 20i (i=1,2,...N) includes a driver DRV, a switching transistor HSi (also known as a high-side switch), a switching transistor LSi (also known as a low-side switch), an inductor Lx, and an output capacitor Coi. The drains of the high-side switch HSi and the low-side switch LSi are connected to each other, and their common terminal forms a switching node. The source of the low-side switch LSi is connected to ground, and the source of the high-side switch HSi is connected to the input voltage Vin. The first terminal of the inductor Lx is connected to the switching node, and the second terminal of the inductor Lx is connected to the output voltage Vout. Each driver DRV in each power stage circuit 201~20N receives a control signal from the control circuit and controls the corresponding switching transistor to turn on and off according to the received control signal.

[0037] It should be understood that in this embodiment, the high-side switch HSi is the main power transistor and the low-side switch LSi is the synchronous rectifier transistor. The switches HSi and LSi can be any type of field-effect transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET). Without departing from the teachings of this invention, they can also be other types of field-effect and / or other types of transistors known to those skilled in the art.

[0038] Furthermore, although each power stage circuit can be referenced Figure 2 The structure of the power stage circuits 201-20N in this embodiment is explained. In this embodiment, the inductors for each phase of each power stage circuit in the N power stage circuits 201-20N can be discrete or coupled (e.g., the first and second phase inductors are coupled; the third and fourth phase inductors are coupled, and so on). Although the power stage circuits 201-20N are described as having a buck topology, the technical solution of this invention can be adopted for any type of layout design, such as boost, flyback, buck-boost, Cuk, Sepic, and Zeta types.

[0039] Specifically, the control circuit includes a loop control module 210 and multiple logic control modules 221-22N connected in a daisy chain architecture. The loop control module 210 generates a loop compensation signal Comp based on the output voltage Vout of the multiphase power supply 200 and the reference voltage signal Vref, and transmits this signal to each logic control module 221-22N. Each logic control module 221-22N is connected one-to-one with multiple power stage circuits 201-20N. Each logic control module receives the loop compensation signal Comp as input and generates a switching control signal PWM for the corresponding phase power stage circuit based on the loop compensation signal Comp, thereby adjusting the on and off timing of the corresponding phase's switching transistors and controlling the charging and discharging process of the inductor current in each phase.

[0040] For example, the loop control module 210 can use any existing constant on-time (COT) control scheme to control the multiphase power supply 200. Under this COT control scheme, there are various ways to implement the loop control module 210. For example, in one embodiment, the loop control module 210 directly compares the reference voltage signal Vref with the feedback signal Vfb of the output voltage Vout to generate the loop compensation signal Comp. In another embodiment, the error between the reference voltage signal Vref and the feedback signal Vfb is compensated to obtain an error signal, and the error signal is compared with a ramp compensation signal that characterizes the changing trend of the sum of the inductor currents of each phase to generate the loop compensation signal Comp. The ramp compensation signal can be a current sampling signal characterizing the inductor current of each phase obtained by sampling, or a current ripple signal simulating the change of the inductor current of each phase. That is, any control method of COT in the prior art and its variations can be applied here. Furthermore, other existing power converter control methods, such as adaptive on-time control (compared to COT, the on-time Ton is not fixed, but is adjusted according to the input voltage and / or output voltage), are also applicable to this solution, meaning that this invention does not limit the control method.

[0041] Furthermore, each logic control module 22i has a loop control terminal, a first synchronization terminal Int, and a second synchronization terminal Next. The loop control terminal is connected to the loop control terminals of the other logic control modules and receives the loop compensation signal Comp together. The first synchronization terminal Int is connected to the second synchronization terminal Next of the previous logic control module 22(i-1) to receive the phase transmission signal En_nxt(i-1) of the previous phase, where i is an integer greater than 1. The second synchronization terminal Next is connected to the first synchronization terminal Int of the next logic control module 22(i+1) to output the phase transmission signal En_nxti of the current phase, thereby forming a cascaded synchronization signal transmission path. Each logic control module 22i is used to generate the phase transmission signal En_nxti of the current phase and the switching control signal PWMi of the corresponding power stage circuit 20i based on the phase transmission signal En_nxt(i-1) of the previous phase and the loop compensation signal Comp. In this way, the phase coordination between adjacent logic control modules is achieved through the phase transmission signal En_nxt, ensuring that the switching control signals PWM of each phase are evenly distributed in time, and realizing the interleaved parallel control of multi-phase power supply.

[0042] In some embodiments, the logic control module 22i is configured to enable upon receiving the phase transfer signal En_nxt(i-1) of the previous phase, and after enabling, determine whether the first edge (e.g., rising edge) of the loop compensation signal Comp is detected. When the first edge of the loop compensation signal Comp is detected, the logic control module 22i sets the corresponding switch control signal PWMi to a high level to turn on the high-side switch HSi in the corresponding power stage circuit 20i. The logic control module 22i is further configured to pull the phase transfer signal En_nxti of the current phase to a high level when the second edge (e.g., falling edge) of the loop compensation signal Comp is detected or the conduction time of the high-side switch HSi reaches a first preset time, and pass it to the next logic control module 22(i+1) to trigger the conduction timing of the adjacent phase. Furthermore, each logic control module 22i is also used to reset the phase transmission signal En_nxti of the current phase to a low level when the next logic control module 22(i+1) sets the corresponding switch control signal PWM(i+1) to a high level. This process is passed step by step to achieve a precise staggered distribution of the conduction times of each phase switch.

[0043] In some embodiments, each logic control module 22i is further configured to trigger adaptive on-time detection after the high-side switch HSi is turned on, and reset the corresponding switch control signal PWMi to a low level after the on-time of the high-side switch HSi reaches a second preset time, so as to turn on the low-side switch LSi in the corresponding power stage circuit 20i. In some embodiments, the second preset time is set based on the input voltage Vin and the output voltage Vout of the multiphase power supply 200, so that each logic control module 22i can modulate the duty cycle of the switch control signal PWMi based on the input voltage Vin and the output voltage Vout to realize adaptive COT control logic.

[0044] In some embodiments, the first synchronization terminal Int of the first logic control module among the plurality of logic control modules 221-22N and the second synchronization terminal Next of the last logic control module among the plurality of logic control modules 221-22N are connected to the loopback connection line to connect the plurality of logic control modules 221-22N into a circular chain. Any one of the plurality of logic control modules 221-22N can serve as the first or last logic control module, without needing to correspond to its physical position in the daisy-chain architecture. When a logic control module is configured as the first or last logic control module, it only needs to be connected to the loopback connection line through internal logic to form a circular chain. Only the sequential order of the logic control modules in the circular chain is required; they are not required to be connected in a specific order. Therefore, this greatly improves the convenience for users to design circuits according to specific applications.

[0045] Because of the daisy-chain architecture, users can easily adjust the total number of phases in a multi-phase power supply according to the specific application requirements. If the number of phases needs to be increased, only new logic control modules and corresponding external components need to be added to the daisy-chain architecture. Furthermore, only the phase transfer signal En_nxt is transmitted between the multiple logic control modules in the loop. The signal for the logic control module to turn on the high-side switch of the corresponding power stage module is controlled by the loop compensation signal Comp generated by the loop control module 210. Therefore, the loop control module 210 does not need to distinguish the current position of the unit during the control process of all units, which greatly simplifies the design of the loop control module 210 and reduces circuit costs.

[0046] In one embodiment, each logic control module is coupled to a communication bus and can communicate with a host controller via the communication bus. For example, the host controller can provide an external start signal EN_SYS and a master-slave configuration signal Master to the first logic control module in the daisy-chain architecture (also referred to as the master logic control module) through the communication bus to control the start of the loop. For instance, when multiple logic control modules 221~22N participate in the loop of the daisy-chain architecture, assuming logic control module 221 is the master logic control module and logic control modules 222~22N are slave logic control modules, the host controller can provide the master-slave configuration signal Master and the external start signal EN_SYS to logic control module 221 through the communication bus. Upon receiving the master-slave configuration signal Master and the external start signal EN_SYS, logic control module 221 enables and, after enabling, generates a switching control signal PWM1 and a phase transfer signal En_nxt1 for the corresponding power stage circuit 201 based on the trigger edge of the loop compensation signal Comp. The logic control module 222 is enabled based on the phase transfer signal En_nxt1. After being enabled, it generates the corresponding power stage circuit 202 switching control signal PWM2 and the phase transfer signal En_nxt2 based on the trigger edge of the loop compensation signal Comp. This process continues until the logic control module 22N is enabled based on the phase transfer signal En_nxt(N-1). After being enabled, it generates the corresponding power stage circuit 20N switching control signal PWMN and the phase transfer signal En_nxtN based on the trigger edge of the loop compensation signal Comp. At this point, the logic control module 221 is enabled again based on the phase transfer signal En_nxtN, thus completing a daisy-chain cycle.

[0047] The communication bus here can use common buses such as I2C, SPI, SCI, UART, and CAN. When using the I2C bus, the PMBUS or SMBUS protocol can be selected.

[0048] Figure 3 A schematic circuit diagram of a loop control module 210 according to an embodiment of the present invention is shown. Figure 3As shown, the loop control module 210 of this embodiment includes feedback resistors R1 and R2, an error amplifier 211, a slope compensation module 212, and a PWM comparator 213. The feedback resistors R1 and R2 are used to perform voltage division sampling on the output voltage Vout of the multi-phase power supply to generate a feedback signal Vfb. The error amplifier 211 compares and amplifies the feedback signal Vfb with a reference voltage signal Vref to generate an error signal EA. The slope compensation module 212 generates a slope compensation signal Ramp with a fixed slope based on the clock signal of the oscillator circuit to improve system stability and prevent subharmonic oscillations. The PWM comparator 213 compares the error signal EA with the slope compensation signal Ramp and generates the loop compensation signal Comp based on the comparison result. The rising edge of the loop compensation signal Comp is used to trigger the generation of the switching control signal PWM in each phase power stage circuit. For example, the PWM comparator 213 is used to output a low-level loop compensation signal Comp when the error signal EA is less than the ramp compensation signal Ramp, and to output a high-level loop compensation signal Comp when the error signal EA is greater than the ramp compensation signal Ramp, thereby triggering the corresponding logic control module to generate a switching control signal PWM.

[0049] It is understood that the implementation of the loop control module 210 of the present invention is not limited to... Figure 3 The structure shown can also be replaced by a transconductance amplifier, a digital control loop, or other equivalent circuits.

[0050] Figure 4 A schematic circuit diagram of a logic control module according to an embodiment of the present invention is shown. All logic control modules 221-22N in this embodiment adopt the same structure. Figure 4 The following explanation uses logic control module 221 as an example. Figure 4 As shown, the logic control module 221 includes a first logic unit 231, flip-flop units 232 and 237, a second logic unit 233, a timing unit 234, a signal modulation unit 235, and a reset unit 236.

[0051] The first logic unit 231 receives the phase transfer signal En_nxtN, the loop compensation signal Comp, the master-slave configuration signal Master, and the external start signal EN_SYS output by the previous phase logic control module 22N. It then configures the logic control module to be either a master or slave logic control module based on the master-slave configuration signal Master, and generates a set trigger signal Trig1 according to a preset logic after configuration. For example, when the master-slave configuration signal Master is high, the logic control module is configured as the master logic control module. The first logic unit 231 outputs a high-level set trigger signal Trig1 when the external start signal EN_SYS is high or when both the phase transfer signal En_nxtN and the loop compensation signal Comp are high; otherwise, it outputs a low-level set trigger signal Trig1. When the master-slave configuration signal Master is low, the logic control module is configured as a slave logic control module. In this case, the first logic unit 231 outputs a high-level set trigger signal Trig1 only when both the phase transmission signal En_nxtN and the loop compensation signal Comp are high; otherwise, it outputs a low level. This design ensures that the slave module strictly responds to the preceding transmission signals according to the phase timing, avoiding false triggering.

[0052] Further, the first logic unit 231 includes AND gates AND1 and AND gates AND2, a pulse unit 2311, a pulse unit 2312, and an OR gate OR1. AND gate AND1 performs a logical AND operation on the phase transfer signal En_nxtN and the loop compensation signal Comp; pulse unit 2311 converts the external start signal EN_SYS into a rising-edge triggered pulse signal; AND gate AND2 performs a logical AND operation on the master-slave configuration signal Master and the output of pulse unit 2311; OR gate OR1 performs a logical OR operation on the outputs of AND gates AND1 and AND gate AND2; and pulse unit 2312 converts the output signal of OR gate OR1 into a rising-edge triggered pulse signal, thereby generating the set trigger signal Trig1.

[0053] The trigger unit 232 is, for example, a D flip-flop. Its clock terminal is used to receive the set trigger signal Trig1 as input, and its data terminal is connected to a high level. The trigger unit 232 is used to latch and output the high level state of its data terminal under the triggering of the rising edge of the set trigger signal Trig1, thereby forming the conduction enable signal En_on of this phase at the first output terminal. The conduction enable signal En_on is used to start the conduction of the high-side switch HS1 of the power stage of this phase.

[0054] The reset unit 233 is used to receive the loop compensation signal Comp and the enable signal En_on, and to output a reset trigger signal Trig2 to the trigger unit 232 when the loop compensation signal Comp flips to a low level or the enable signal En_on reaches a first preset time. After receiving the reset trigger signal Trig2, the trigger unit 232 sets the enable signal En_on to a low level.

[0055] Furthermore, the reset unit 233 includes an inverter INV1, a delay unit 2331, and an OR gate OR2. The inverter INV1 is used to invert the loop compensation signal Comp, the delay unit 2331 is used to delay the enable signal En_on for a first preset time, and the OR gate OR2 is used to perform a logical OR operation between the output of the inverter INV1 and the output of the delay unit 2331 to generate a reset trigger signal Trig2.

[0056] Flip-flop unit 237 is, for example, a D flip-flop. Its clock input is connected to the second output of flip-flop unit 232, its data input is connected to a high level, and its reset input is connected to the switch control signal (e.g., switch control signal PWM2) of the next-level logic control module. Its first output is used to output the phase transfer signal En_nxt1 of this stage. When flip-flop unit 232 receives the reset trigger signal Trig2, it sets the enable signal En_on to a low level, and its second output flips to a high level. Triggered by the rising edge of the second output of flip-flop unit 232, flip-flop unit 237 latches and outputs the high-level state of its data input, thereby setting the phase transfer signal En_nxt1 of this stage to a high level to trigger the next-level logic control module to enter the working state. When the switch control signal PWM2 corresponding to the next-level logic control module 222 flips to a high level, flip-flop unit 237 sets the phase transfer signal En_nxt1 to a low level.

[0057] The second logic unit 234 is used to receive the enable signal En_on and the loop compensation signal Comp, and to generate a set control signal SET by performing an AND operation on them. For example, the second logic unit 234 is used to output a high-level set control signal SET when both the enable signal En_on and the loop compensation signal Comp are high, and otherwise output a low-level set control signal SET.

[0058] Furthermore, the second logic unit 234 includes a pulse unit 2313 and an AND gate 3. The pulse unit 2313 receives the loop compensation signal Comp and converts it into a rising-edge triggered pulse signal. The AND gate 3 performs a logical AND operation on the pulse signal and the enable signal En_on to generate a set control signal SET. When the loop compensation signal Comp changes direction and the enable signal En_on is high, the pulse unit 2313 outputs a high-level pulse for a single clock cycle, which is then output as a corresponding high-level set control signal SET via the AND gate 3.

[0059] The timing unit 235 is used to start timing when the set control signal SET flips to a high level, and to output a high-level reset control signal RST when the timing reaches a second preset time.

[0060] The signal modulation unit 235 is used to receive the set control signal SET and the reset control signal RST, and generate the corresponding switch control signal PWM1 based on the two. For example, the signal modulation unit 235 includes an SR latch 2361, whose set terminal receives the set control signal SET, its reset terminal receives the reset control signal RST, and its output terminal generates the switch control signal PWM1. In some other embodiments, the signal modulation unit 235 further includes an AND gate AND4 and an OR gate OR3. The AND gate AND4 is used to perform a logical AND operation on the loop compensation signal Comp and the turn-on enable signal En_on. Its output is connected to one input of the OR gate OR3, and the other input of the OR gate OR3 receives the output signal of the SR latch 2361. Finally, the OR gate OR3 outputs the modulated switch control signal PWM1, thereby ensuring that the switch control signal PWM1 remains on when both the loop compensation signal Comp and the turn-on enable signal En_on are high. This can avoid false turn-off due to interference or timing deviation, and improve system stability and power output accuracy.

[0061] Figure 5 A schematic circuit diagram of a timing unit according to an embodiment of the present invention is shown. Figure 5 As shown, the timing unit 235 in this embodiment includes a current generation module 2351, a charging capacitor C1, a comparator 2352, and a reset transistor M1.

[0062] The current generation module 2351 generates a constant charging current Ic based on the input voltage Vin. One end of the charging capacitor C1 is connected to the current generation module 2351, and the other end is grounded. A reset transistor M1 is connected in parallel across the charging capacitor C1, and its gate receives a set control signal SET. For example, the reset transistor M1 is an NMOS transistor, which is turned on when the set control signal SET is high to short-circuit the charging capacitor C1 and complete its discharge, ensuring that the capacitor voltage is zero at the start of each timing cycle. When the set control signal SET transitions from high to low, the reset transistor M1 turns off, and the charging current Ic begins to linearly charge the charging capacitor C1, causing the voltage across the capacitor to rise. The non-inverting input of the comparator 2352 is connected to the non-grounded end of the charging capacitor C1, and the inverting input is connected to the output voltage Vout. This comparator is used to compare the voltage across the charging capacitor C1 with the output voltage Vout in real time, and its output provides the reset control signal RST. When the voltage across the charging capacitor C1 rises above the output voltage Vout, the output of comparator 2352 flips, generating a high-level reset control signal RST. This enables dynamic on-time adjustment based on the input voltage Vin and the output voltage Vout, ensuring that the on-time of the switching transistor adaptively matches the changes in the input and output voltages.

[0063] Further, the current generation module 2351 includes resistors R3-R5, transistors M2-M4, and an error amplifier 2353. Resistors R3 and R4 are connected in series between the input voltage Vin and ground to perform voltage division sampling on the input voltage Vin, obtaining a voltage reference proportional to Vin. The non-inverting input of the error amplifier 2353 is connected to the junction of resistors R3 and R4, the inverting input is connected to the source of transistor M4 and one end of resistor R5, the other end of resistor R5 is connected to ground, and the output of the error amplifier 2353 is connected to the gate of transistor M4. In this embodiment, transistor M4 is, for example, an NMOS transistor. The error amplifier 2353, transistor M4, and resistor R5 form a negative feedback loop, causing M4 to operate in the linear region. This allows the source voltage of transistor M4 to accurately track the voltage division junction of resistors R3 and R4, thereby generating a current signal proportional to the input voltage at the drain of transistor M4. The current is replicated by the current mirror formed by transistors M2 and M3 and supplied to the charging capacitor C1 as the charging current Ic, ensuring that the current Ic has a precise linear relationship with the input voltage Vin.

[0064] In this embodiment, both transistors M2 and M3 are PMOS transistors, and their sources are connected to the input voltage Vin, respectively. Their gates are interconnected and connected to the drain of transistor M4, thereby mirroring the current generated by transistor M4, which is proportional to the input voltage, to the drain of transistor M3.

[0065] Figure 6 The following is a timing diagram of a multiphase power supply according to an embodiment of the present invention, taking a four-phase power supply as an example. Figure 6 The diagram illustrates the timing relationships of the external start signal EN_SYS, the loop compensation signal Comp, the phase switch control signals PWM1~PWM4, and the phase transfer signals En_nxt1~En_nxt4. For example... Figure 6 As shown, after the external start signal EN_SYS goes high, the logic control module 211 of the first phase responds first. When the rising edge of the loop compensation signal Comp arrives, the switch control signal PWM1 is set to high level, and the high-side switch HS1 of the first phase power stage circuit is turned on. When the falling edge of the loop compensation signal Comp arrives, the logic control module 211 sets the phase transfer signal En_nxt1 of this phase to high level, enabling the logic control module 212 of the second phase. When the rising edge of the loop compensation signal Comp of the next phase arrives, the switch control signal PWM2 is set to high level, and the high-side switch HS2 of the second phase power stage circuit is turned on. At the same time, the rising edge of the switch control signal PWM2 resets the phase transfer signal En_nxt1 of the first phase to low level. And so on, each phase responds to the rising edge of the loop compensation signal Comp in turn, so that the switch control signal of the corresponding phase is successively set to high level, realizing multi-phase interleaved conduction. When the switch control signal PWM4 is set to high level, upon the arrival of the next falling edge of the loop compensation signal Comp, the logic control module 214 of the fourth phase outputs the phase transfer signal En_nxt4, re-enabling the logic control module 211 of the first phase, forming a closed-loop timing cycle. Furthermore, after the high-side switch of each phase's power stage circuit is turned on, the timing unit in its logic control module starts timing and generates a reset signal after the preset on-time is reached. This reset signal is then used by the signal modulation unit to set the corresponding switch control signal PWM to low level, turning off the high-side switch of that phase. This achieves constant on-time control in the power stage circuit of each phase, ensuring consistent operating cycles for each phase, effectively suppressing inter-phase current imbalance, and improving overall system efficiency and output ripple characteristics.

[0066] Figure 7 The current waveform diagram of the multiphase power supply according to the present invention is shown, taking a 6-phase power supply as an example. Figure 7 The waveforms of the inductor currents IL1~IL6 for each phase, the output voltage Vout, the slope compensation signal Ramp, the loop compensation signal Comp, and the total output current Iout are shown. Figure 7As shown, in this embodiment, the inductor currents IL1~IL6 of each phase of the multiphase power supply rise and overlap sequentially, ultimately forming a smooth total output current Iout, significantly reducing output ripple. The consistent rise slope of each phase current reflects the accuracy of current sharing control. The ramp compensation signal Ramp and the loop compensation signal Comp work together to ensure that the system responds quickly and maintains stability during load changes.

[0067] like Figure 7 As shown, under steady-state operating conditions, the inductor currents of each phase rise sequentially and overlap in an alternating manner to form a smooth total output current, which significantly reduces the ripple amplitude of the output voltage Vout.

[0068] In summary, the multiphase power supply based on the COT control architecture provided in this embodiment of the invention includes multiple logic control modules connected in a daisy-chain architecture. These modules sequentially respond to the transition edges of the loop control module's output signal using a time-division multiplexing method to generate the switching control signal for their respective phases. Timing information is transmitted between adjacent logic control modules via phase transfer signals, thereby achieving precise interleaved conduction of each phase switch and ensuring efficient system operation across a wide load range. Compared to existing multiphase power supplies, only one control loop is needed to achieve interleaved control between multiphase power stage circuits. This eliminates the need for separate PWM comparators and ramp signal generation circuits in each phase power stage circuit, significantly simplifying the circuit structure and reducing system complexity and chip area, while also lowering power consumption and cost.

[0069] Furthermore, since the conduction time of each phase power stage circuit of the multiphase power supply in this embodiment is constant and uniformly controlled by the same loop, the phase timing is highly symmetrical, which further reduces the harmonic components of the output current, improves the energy efficiency of the power supply under high frequency and light load conditions, and enhances the robustness of the system to process, voltage and temperature changes, ensuring stable operation across the entire temperature range.

[0070] Furthermore, the multiphase power supply in this embodiment of the invention uses a unified and simple chip or circuit to construct the loop chain. It only requires that the control circuits in the loop chain maintain a sequential order, but does not require that they be connected in sequence, which simplifies the difficulty of circuit modification and greatly reduces the cost of the circuit.

[0071] In the above description, well-known structural elements and steps have not been described in detail. However, those skilled in the art should understand that the corresponding structural elements and steps can be implemented through various technical means. Furthermore, in order to form the same structural elements, those skilled in the art can also design methods that are not entirely the same as those described above. Additionally, although various embodiments have been described separately above, this does not mean that the measures in the various embodiments cannot be effectively combined.

[0072] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of the present invention should be determined by the scope defined in the claims of the present invention.

Claims

1. A control circuit for a multiphase power supply, the multiphase power supply comprising multiple parallel power stage circuits, the control circuit comprising: The loop control module is used to generate a loop compensation signal based on the output voltage and reference voltage signal of the multiphase power supply. as well as Multiple logic control modules connected in a daisy-chain architecture are respectively connected to corresponding power stage circuits. Each logic control module has a loop control terminal, a first synchronization terminal, and a second synchronization terminal. The loop control terminal is used to receive the loop compensation signal. The first synchronization terminal is connected to the second synchronization terminal of the preceding logic control module to receive the phase transmission signal of the preceding phase. The second synchronization terminal is connected to the first synchronization terminal of the following logic control module to transmit the phase transmission signal of the current phase. Each logic control module is configured to enable upon receiving the phase transfer signal of the previous phase, and after enabling, generate the corresponding power stage circuit switching control signal and the phase transfer signal of the current phase based on the loop compensation signal.

2. The control circuit according to claim 1, wherein, Each of the logic control modules is configured to trigger the high-side switch of the corresponding power stage circuit to turn on according to the first edge of the loop compensation signal after being enabled, and to generate the phase transmission signal of the current phase when the second edge of the loop compensation signal or the first preset time arrives.

3. The control circuit according to claim 2, wherein, Each of the logic control modules is further configured to turn off the high-side switch after the on-time of the corresponding power stage circuit reaches a second preset time. The second preset time is dynamically adjusted based on the ratio of the input voltage to the output voltage of the multiphase power supply.

4. The control circuit according to claim 3, wherein, One of the plurality of logic control modules is configured as the master logic control module, and the remaining logic control modules are configured as slave logic control modules. The main logic control module is also used to enable the daisy chain when it receives an external start signal, and after it is turned on, it generates the corresponding power stage circuit switching control signal and the phase transmission signal of the current phase according to the loop compensation signal to realize the initial start of the daisy chain.

5. The control circuit according to claim 4, wherein, Each of the plurality of logic control modules includes: The first logic unit receives a master-slave configuration signal, an external start signal, a phase transmission signal of the previous phase, and the loop compensation signal. It configures the logic control module as either a master logic control module or a slave logic control module based on the master-slave configuration signal. When the logic control module is configured as a master logic control module, the first logic unit generates a set trigger signal based on the external start signal, the phase transmission signal of the previous phase, or the loop compensation signal. When the logic control module is configured as a slave logic control module, the first logic unit generates the set trigger signal based on the phase transmission signal of the previous phase and the loop compensation signal. The first D flip-flop is used to output a conduction enable signal according to the set trigger signal; A reset unit is configured to output a reset trigger signal to the first D flip-flop when the second edge of the loop compensation signal or the first preset time arrives. The first D flip-flop is configured to reset the turn-on enable signal according to the reset trigger signal. The second logic unit is used to perform a logical AND operation on the turn-on enable signal and the loop compensation signal, and generate a set control signal based on the operation result. A timing unit is configured to start timing when the set control signal is valid, and generate a reset control signal when the timing reaches the second preset time; and A signal modulation unit is used to generate a switch control signal based on the set control signal and the reset control signal to drive the corresponding power stage circuit.

6. The control circuit according to claim 5, wherein, The first logic unit includes: The first AND gate is used to perform a logical AND operation on the phase transmission signal of the previous phase and the loop compensation signal; The first pulse unit is used to convert the external start signal into a rising edge triggered first pulse signal; The second AND gate is used to perform a logical AND operation on the master-slave configuration signal and the first pulse signal; The first OR gate is used to perform a logical OR operation on the output signals of the first AND gate and the second AND gate; and The second pulse unit is used to convert the output signal of the first OR gate into the set trigger signal triggered by the rising edge.

7. The control circuit according to claim 5, wherein, The clock input of the first D flip-flop receives the set trigger signal, the data input is connected to a high level, the reset input receives the reset trigger signal, and the first output input outputs the enable signal. Each of the plurality of logic control modules further includes: The second D flip-flop has its clock terminal connected to the second output terminal of the first D flip-flop, its data terminal connected to a high level, its reset terminal receiving the switching control signal from the next-stage logic control module, and its output terminal used to output the phase transmission signal.

8. The control circuit according to claim 5, wherein, The reset unit includes: An inverter is used to generate the inverted signal of the loop compensation signal; A delay unit is used to delay the first edge of the enable signal; and The second OR gate is used to perform a logical OR operation on the output signal of the inverter and the output signal of the delay unit to generate the reset trigger signal.

9. The control circuit according to claim 5, wherein, The second logic unit includes: The third pulse unit is used to convert the turn-on enable signal into a rising-edge triggered third pulse signal; and The third AND gate is used to perform a logical AND operation on the third pulse signal and the loop compensation signal to generate the set control signal.

10. The control circuit according to claim 5, wherein, The timing unit includes: A current generation module is used to generate a charging current based on the input voltage; A charging capacitor, the first end of which is connected to the current generating module to receive the charging current, and the second end of which is grounded; A reset transistor, connected between the first terminal of the charging capacitor and ground, is controlled to be turned on by the set control signal to discharge the charging capacitor; and A comparator is used to compare the voltage across the charging capacitor with the output voltage and generate the reset control signal based on the comparison result.

11. The control circuit according to claim 5, wherein, The signal modulation unit includes: The SR latch has a set terminal for receiving the set control signal and a reset terminal for receiving the reset control signal. The fourth AND gate is used to perform a logical AND operation on the loop compensation signal and the enable signal; and The third OR gate is used to perform a logical OR operation on the output signal of the fourth AND gate and the output signal of the SR latch to generate the switch control signal.

12. A multiphase power supply, comprising: Multiple power stage circuits connected in parallel; as well as The control circuit according to any one of claims 1 to 11.

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