Programmable frequency divider circuit

Abstract

The invention provides a programmable frequency divider circuit. The programmable frequency divider circuit comprises a first-path frequency division clock signal generation unit, a second-path frequency division clock signal generation unit and a target clock signal generation unit, the first path frequency division clock signal generation unit and the second path frequency division clock signal generation unit share a first counter; the first-path frequency division clock signal generation unit is used for sampling the first counter to obtain a first-path frequency division clock signal; the second-path frequency division clock signal generation unit is used for sampling the first counter, performing reset operation on the second counter according to a sampling result, and generating a second-path frequency division clock signal; and the target clock signal generation unit is used for generating a target clock signal according to the first path of frequency division clock signal and the second path of frequency division clock signal, fixed 50% duty ratio output can be realized by utilizing two counters, a duty ratio adjusting circuit without increasing the area and a redundant feedback adjusting loop are not needed, and the power consumption and the design cost are reduced.

Description

Technical Field

[0001] This invention relates to the field of logic circuit technology, and more specifically to a programmable frequency divider circuit. Background Technology

[0002] Currently, programmable multi-mode divider circuit technology in phase-locked loops (PLLs) is relatively mature. The main programmable multi-mode divider structures used in the circuits include 2 / 3 divider cascade structures and counter structures. However, these programmable multi-mode divider circuits are difficult to guarantee a 50% duty cycle. To achieve a 50% duty cycle, it is necessary to add a duty cycle adjustment circuit.

[0003] The inventors discovered that existing multi-mode frequency divider circuits have poor output duty cycles, making them unsuitable for circuits with high clock signal duty cycle requirements, such as dual-edge sampling clock signal circuits. Achieving a 50% duty cycle by adding a duty cycle adjustment circuit would require a significant increase in area and power consumption, and might even necessitate the addition of feedback circuitry, greatly increasing design complexity. Summary of the Invention

[0004] In response to this, this application provides a programmable frequency divider circuit to solve the problems of existing frequency divider circuits requiring the addition of a duty cycle adjustment circuit to achieve duty cycle adjustment, resulting in large area and power consumption, and requiring the addition of a feedback circuit to adjust, resulting in high design complexity.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0006] This application discloses a programmable frequency divider circuit, including: a first frequency divider clock signal generation unit, a second frequency divider clock signal generation unit, and a target clock signal generation unit;

[0007] The first frequency-divided clock signal generation unit and the second frequency-divided clock signal generation unit share the first counter;

[0008] The first frequency-divided clock signal generation unit is used to sample the first counter to obtain the first frequency-divided clock signal;

[0009] The second frequency-divided clock signal generation unit is used to sample the first counter, reset the second counter according to the sampling result, and generate the second frequency-divided clock signal.

[0010] The target clock signal generation unit is used to generate a target clock signal based on the first frequency-divided clock signal and the second frequency-divided clock signal, wherein the duty cycle of the target clock signal is 50%.

[0011] Optionally, in the above-described programmable frequency divider circuit, the first frequency divider clock signal generation unit includes: the first counter and the second flip-flop;

[0012] The reset terminal of the first counter is connected to the data terminal of the second flip-flop, and the clock control terminal of the first counter receives the clock signal to be divided.

[0013] The clock control terminal of the second flip-flop receives the inverted signal of the clock signal to be divided, and the output terminal of the first flip-flop outputs the first divided clock signal.

[0014] Optionally, in the above-described programmable frequency divider circuit, the second flip-flop is a D flip-flop.

[0015] Optionally, in the above-described programmable frequency divider circuit, the second frequency divider clock signal generation circuit includes: the first counter, the second counter, the first flip-flop, and the clock signal selection unit;

[0016] The output terminal of the first counter is connected to the data terminal of the first flip-flop, and the clock control terminal of the first counter receives the clock signal to be divided.

[0017] The output terminal of the clock signal selection unit is connected to the clock control terminal of the first flip-flop and the clock control terminal of the second counter, and is used to select one of the clock signal to be divided and the inverted signal of the clock signal to be divided as the sampling clock signal output according to the input division number of the programmable frequency divider circuit.

[0018] The output terminal of the first flip-flop is connected to the reset terminal of the second counter;

[0019] The output terminal of the second counter outputs the second frequency-divided clock signal.

[0020] Optionally, in the above-described programmable frequency divider circuit, the input division number of the programmable frequency divider circuit is an even number, and the clock signal selection unit selects the inverted signal of the clock signal to be divided as the sampling clock signal output.

[0021] Optionally, in the above-described programmable frequency divider circuit, the input division number of the programmable frequency divider circuit is an odd number, and the clock signal selection unit selects the clock signal to be divided as the sampling clock signal output.

[0022] Optionally, in the above-described programmable frequency divider circuit, the clock signal selection unit includes: a selector;

[0023] The first input terminal of the selector receives the clock signal to be divided.

[0024] The second input terminal of the selector receives the inverted signal of the clock signal to be divided;

[0025] The control terminal of the selector receives the input division number from the programmable frequency divider circuit;

[0026] The output of the selector serves as the output of the clock signal selection unit.

[0027] Optionally, in the above-described programmable frequency divider circuit, the first flip-flop is a D flip-flop.

[0028] Optionally, in the above-described programmable frequency divider circuit, the target clock signal generation unit includes: a third flip-flop;

[0029] The reset terminal of the third flip-flop is connected to the output terminal of the second counter to receive the second frequency-divided clock signal;

[0030] The clock control terminal of the third flip-flop is connected to the output terminal of the second flip-flop and receives the first frequency-divided clock signal;

[0031] The data terminal of the third trigger is set to 1;

[0032] The target clock signal is output from the output terminal of the third flip-flop.

[0033] Optionally, in the above-described programmable frequency divider circuit, the third flip-flop is a D flip-flop.

[0034] This invention provides a programmable frequency divider circuit, comprising: a first-channel frequency divider clock signal generation unit, a second-channel frequency divider clock signal generation unit, and a target clock signal generation unit; the first-channel frequency divider clock signal generation unit and the second-channel frequency divider clock signal generation unit share a first counter; the first-channel frequency divider clock signal generation unit samples the first counter to obtain a first-channel frequency divider clock signal; the second-channel frequency divider clock signal generation unit samples the first counter and resets the second counter based on the sampling result to generate a second-channel frequency divider clock signal; the target clock signal generation unit generates a target clock signal based on the first-channel and second-channel frequency divider clock signals, wherein the target clock signal has a duty cycle of 50%. A fixed 50% duty cycle output can be achieved using only two counters, eliminating the need for a large-area duty cycle adjustment circuit and redundant feedback adjustment loops, thus reducing power consumption and design cost. This solves the problems of existing frequency divider circuits requiring additional duty cycle adjustment circuits for duty cycle adjustment, resulting in larger area and power consumption, and the need for additional feedback circuits for adjustment, leading to greater design complexity. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0036] Figure 1 A schematic diagram of the phase of the input and output clock signals of a counter provided in this application when the frequency is divided by three.

[0037] Figure 2 This is a schematic diagram of a programmable frequency divider circuit provided in an embodiment of this application;

[0038] Figure 3 and Figure 4 Circuit diagrams of two programmable frequency divider circuits provided in embodiments of this application;

[0039] Figure 5 The output waveform diagram of each clock signal of a programmable frequency divider circuit provided in this application embodiment when implementing a 4-fold frequency division;

[0040] Figure 6 The output waveforms of various clock signals of a programmable frequency divider circuit provided in this application embodiment when implementing a 5-fold frequency division are shown. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] First, it should be noted that in a traditional counter-based frequency divider structure, the clock signal pulse width after division by N can achieve the length of one frequency division cycle, i.e., a duty cycle of 1 / N. For example, when N=3, the phase diagram of the input and output clock signals is shown below. Figure 1 As shown, the output duty cycle is 1 / 3.

[0043] This application provides a programmable frequency divider circuit to solve the problems of existing frequency divider circuits that require adding a duty cycle adjustment circuit to adjust the duty cycle, resulting in large area and power consumption, and that adding a feedback circuit to adjust the duty cycle, resulting in large design complexity.

[0044] Please see Figure 2The programmable frequency divider circuit mainly includes: a first frequency divider clock signal generation unit 101, a second frequency divider clock signal generation unit 102, and a target clock signal generation unit 103.

[0045] The first frequency divider clock signal generation unit 101 and the second frequency divider clock signal generation unit 102 share the first counter.

[0046] The first frequency-divided clock signal generation unit 101 is used to sample the first counter to obtain the first frequency-divided clock signal. Specifically, the first frequency-divided clock signal generation unit 101 can obtain the first frequency-divided clock signal by sampling the clock signal from the first counter.

[0047] In some embodiments, such as Figure 3 or Figure 4 As shown, the first frequency divider clock signal generation unit 101 may include: a first counter COUNTER1 and a second flip-flop DFF2.

[0048] The reset terminal RST of the first counter COUNTER1 is connected to the data terminal D of the second flip-flop DFF2, and the clock control terminal CLK of the first counter COUNTER1 receives the clock signal CLK to be divided.

[0049] The clock control terminal CLK of the second flip-flop DFF2 receives the inverted signal CLKN of the clock signal to be divided, and the output terminal OUT of the second flip-flop DFF2 outputs the first divided clock signal D2.

[0050] In practical applications, the clock signal CLK to be divided needs to be divided to finally generate the target clock signal DIV_N with a duty cycle of 50%.

[0051] It should be noted that the second flip-flop DFF2 can sample the clock signal CLK to be divided to obtain the first divided clock signal D2.

[0052] In some embodiments, the second trigger DFF2 can be a D trigger; specifically, it can be a D trigger with a reset function; of course, it is not limited to this, and can also be other existing triggers. This application does not limit the specific type of the second trigger DFF2, and all of them are within the protection scope of this application.

[0053] The second-channel frequency-divided clock signal generation unit 102 is used to sample the first counter and reset the second counter based on the sampling result to generate the second-channel frequency-divided clock signal. Specifically, the second-channel frequency-divided clock signal generation unit 102 can generate the second-channel frequency-divided clock signal by sampling the clock from the first counter and resetting the second counter based on the sampling result.

[0054] In some embodiments, such as Figure 3 As shown, the second frequency divider clock signal generation circuit may include: a first counter COUNTER1, a second counter COUNTER2, a first flip-flop DFF1, and a clock signal selection unit 201;

[0055] The output terminal OUT of the first counter COUNTER1 is connected to the data terminal D of the first flip-flop DFF1, and the clock control terminal CLK of the first counter COUNTER1 receives the clock signal CLK to be divided.

[0056] The output of the clock signal selection unit 201 is connected to the clock control terminal CLK of the first flip-flop DFF1 and the clock control terminal CLK of the second counter COUNTER2. It is used to select one of the clock signals to be divided, CLK and CLKN, as the sampling clock signal output according to the input division number of the programmable frequency divider circuit.

[0057] The output terminal OUT of the first flip-flop DFF1 is connected to the reset terminal RST of the second counter COUNTER2;

[0058] The output terminal OUT of the second counter COUNTER2 outputs the second frequency-divided clock signal C2.

[0059] In practical applications, the input division number of the programmable frequency divider circuit is an even number, and the clock signal selection unit 201 selects the inverted signal CLKN of the clock signal to be divided as the sampling clock signal output.

[0060] It is understandable that, in order to ensure that the duty cycle of the target clock signal DIV_N is 50%, when the input division number of the programmable frequency divider circuit is even, the clock signal selection unit 201 should select the inverted signal CLKN of the clock signal to be divided as the sampling clock signal output.

[0061] However, since the input division number of the programmable frequency divider circuit is odd, the clock signal selection unit 201 selects the clock signal to be divided, CLK, as the sampling clock signal output.

[0062] It is understandable that, in order to ensure that the duty cycle of the target clock signal DIV_N is 50%, when the input division number of the programmable frequency divider circuit is odd, the clock signal selection unit 201 should select the clock signal CLK to be divided as the sampling clock signal output.

[0063] In some embodiments, such as Figure 4 As shown, the clock signal selection unit 201 may include: a strobe MUX;

[0064] The first input of the selector MUX receives the clock signal CLK to be divided.

[0065] The second input of the selector MUX receives the inverted signal CLKN of the clock signal to be divided.

[0066] The control terminal of the strobe MUX receives the input division number D from the programmable frequency divider circuit. <0> ;

[0067] The output of the selector MUX serves as the output of the clock signal selection unit 201, outputting a sampled clock signal.

[0068] In practical applications, in addition to using a selector MUX to implement the clock signal selection unit 201, it can also be implemented using other existing devices. This application does not make specific limitations, and all of them are within the protection scope of this application.

[0069] In some embodiments, the first trigger DFF1 can be a D trigger; specifically, it can be a D trigger with a reset function; of course, it is not limited to this, and can also be other existing triggers. This application does not limit the specific type of the first trigger DFF1, and all of them are within the protection scope of this application.

[0070] The target clock signal generation unit 103 is used to generate a target clock signal based on the first frequency-divided clock signal and the second frequency-divided clock signal, and the duty cycle of the target clock signal is 50%.

[0071] In some embodiments, such as Figure 3 or Figure 4 As shown, the target clock signal generation unit 103 may include: a third flip-flop DFF3;

[0072] The reset terminal RST of the third flip-flop DFF3 is connected to the output terminal OUT of the second counter COUNTER2 to receive the second frequency-divided clock signal C2.

[0073] The clock control terminal CLK of the third flip-flop DFF3 is connected to the output terminal OUT of the second flip-flop CFF2 to receive the first frequency-divided clock signal D2.

[0074] The data terminal D of the third flip-flop DFF3 is set to 1;

[0075] The output terminal OUT of the third flip-flop DFF3 outputs the target clock signal DIV_N.

[0076] In practical applications, since the second divided clock signal C2 received by the reset terminal RST of the third flip-flop DFF3 is the divided signal obtained by resetting the second counter COUNTER2 after the clock signal CLK to be divided is sampled by the first flip-flop DFF1, and the first divided clock signal D2 received by the clock control terminal CLK of the third flip-flop DFF3 is the divided signal obtained after the clock signal CLK to be divided is sampled by the second flip-flop DFF2, the third flip-flop DFF3 can generate a target clock signal DIV_N with an unchanged period, and the duty cycle of the target clock signal DIV_N is 50%.

[0077] In some embodiments, the third flip-flop DFF3 can be a D flip-flop; specifically, it can be a D flip-flop with a reset function; of course, it is not limited to this, and can also be other existing flip-flops. This application does not limit the specific type of the third flip-flop DFF3, and all of them are within the protection scope of this application.

[0078] It should be noted that the first counter COUNTER1 and the second counter COUNTER2 in this application are both programmable frequency dividers with counter structures. Combined with... Figure 4 The binary input divider ratio of the first counter COUNTER1 is n+1 bits D. <n:0>The binary divider ratio of the second counter COUNTER2 is also n+1 bits, but the highest bit is set to 0, and the remaining bits are set to D. <n:1>D <0> As the selection condition for the clock signal CLK to be divided and its inverted signal CLKN, when D <0> When D is 0, the selector MUX selects the inverted signal CLKN of the clock signal to be divided as input; conversely, when D is 0, the selector MUX selects the inverted signal CLKN of the clock signal to be divided as input. <0> When D is 1, the selector MUX selects the clock signal CLK to be divided as input. <0> =0 indicates that the input division number of the programmable frequency divider circuit is even, when D <0> =1 indicates that the input division number of the programmable frequency divider circuit is an odd number.

[0079] exist Figure 4 Based on this, combined Figure 5 When the first counter COUNTER1 implements D <n:1>Frequency division, assuming D <n:1>=100. Utilizing the frequency division characteristic of the counter, the input binary value is converted to a decimal value, which is the frequency division number implemented by the timer. Therefore, the first counter (COUNTER1) implements a 4-fold frequency division. The duty cycle of the clock signal C1 output by the first counter (COUNTER1) is 1 / 4. Since D... <0> =0, the selector MUX selects the inverted signal CLKN of the clock signal to be divided as the sampling clock signal. After sampling by the first flip-flop DFF1, the clock signal D1 is obtained. The rising edge of the clock signal D1 is aligned with the falling edge of the clock signal CLK to be divided. The clock signal D2 output by the second flip-flop DFF2 is the same as the clock signal D1 output by the first flip-flop DFF1. The clock signal D1 output by the first flip-flop DFF1 is used as the reset input RST of the second counter COUNTER2. At this time, the frequency division control of the second counter COUNTER2 is 010, which is a frequency division of 2. The clock control input CLK of the second counter COUNTER is the inverted signal CLKN of the clock signal to be divided (i.e., sampling at the falling edge of the clock signal to be divided). Therefore, starting from the first rising edge generated by the clock signal D1 output by the first flip-flop DFF1, after two clock cycles, the clock signal C2 output by the second counter COUNTER2 starts to go high. Then, the clock signal C2 output by the second counter COUNTER outputs a high level for one cycle width and then goes low. Until the next rising edge of the clock signal D1 output by the first flip-flop DFF1 arrives, the clock signal C2 output by the second counter COUNTER counts again for 2 cycles and then goes high again, and so on. Finally, the clock signal C2 output by the second counter COUNTER is used as the reset signal for the third flip-flop DFF3, and the clock signal D2 output by the second flip-flop DFF2 is used as the sampling signal for the third flip-flop DFF3 to sample a high level. When the clock signal C2 output by the second counter COUNTER2 is low, the clock signal DIV_N output by the third flip-flop DFF3 becomes high at the rising edge of the clock signal D2 output by the second flip-flop DFF2. After the clock signal D2 output by the second flip-flop DFF2 becomes high, the clock signal DIV_N output by the third flip-flop DFF3 is reset to low, which enables the duty cycle of the clock signal DIV_N output by the third flip-flop DFF3 to be 50%.

[0080] exist Figure 4 Based on this, combined Figure 6 When the first counter COUNTER1 implements D <n:1>Frequency division, assuming D <n:1>=101. Utilizing the frequency division characteristic of the counter, the input binary value is converted to a decimal value, which is the frequency division number implemented by the timer. Therefore, the first counter (COUNTER1) implements a 5-fold frequency division, and the duty cycle of the clock signal C1 output by the first counter (COUNTER1) is 1 / 5. Since D... <0> =1, the selector MUX selects the clock signal CLK to be divided as the sampling clock signal. After sampling by the first flip-flop DFF1, the clock signal D1 is obtained. The rising edge of the clock signal D1 is aligned with the rising edge of the clock signal CLK to be divided. The clock signal D1 output by the first flip-flop DFF1 is delayed by half a cycle compared to the clock signal D2 output by the second flip-flop DFF2. At this time, the frequency division control of the second counter COUNTER2 is 010, which is still a division by 2. The clock signal D1 output by the first flip-flop DFF1 is used as the reset signal of the second counter COUNTER2. Starting from the first rising edge generated by the clock signal D1 output by the first flip-flop DFF1, after another clock signal cycle, the clock signal C2 output by the second counter COUNTER2 begins to go high, and so on. Similarly, the clock signal C2 output by the second counter COUNTER2 is used as the reset signal of the third flip-flop DFF3. The clock signal D2 output by the second flip-flop DFF2 is used as the sampling signal to sample a high level. When the clock signal C2 output by the second counter COUNTER2 is low, the second flip-flop... At the rising edge of the clock signal D2 output by flip-flop DFF2, the clock signal DIV_N output by the third flip-flop DFF3 goes high. After the clock signal C2 output by the second counter COUNTER2 goes high, the clock signal DIV_N output by the third flip-flop DFF3 goes low. The pulse width of the clock signal DIV_N output by the third flip-flop DFF3 is 2.5 cycles of the clock signal to be divided. Since the inverted signal CLKN of the clock signal to be divided is a five-fold division of the clock signal CLK, one cycle of the inverted signal CLKN contains five cycles of the clock signal CLK. Therefore, the duty cycle of the clock signal DIV_N output by the third flip-flop DFF3 is still 50%.

[0081] It should be noted that this application only takes the input division number of the programmable frequency divider circuit as 4 and 5 as examples. When the input division number of the programmable frequency divider circuit is other, the principle is the same as above, and will not be described in detail.

[0082] Based on the above principle, it can be understood that this application uses one set of counter outputs as the input of the D flip-flop and another set of counter outputs as the reset signal of the D flip-flop. The two sets of output signals cooperate with the D flip-flop to generate a target clock signal with a duty cycle of 50%.

[0083] Furthermore, a clock signal selection unit 201 is provided in the second frequency divider clock signal generation unit 102, which detects the least significant bit D of the input binary frequency divider. <0> The value of is used to determine whether to select the clock signal to be divided, CLK, or the inverted signal CLKN of the clock signal to be divided, so as to ensure the phase relationship between the edge of the target clock signal DIV_N and the clock signal to be divided, CLK.

[0084] The programmable frequency divider circuit provided in this embodiment includes: a first-channel frequency divider clock signal generation unit 101, a second-channel frequency divider clock signal generation unit 102, and a target clock signal generation unit 103; the first-channel frequency divider clock signal generation unit 101 and the second-channel frequency divider clock signal generation unit 102 share a first counter COUNTER1; the first-channel frequency divider clock signal generation unit 101 is used to sample the first counter COUNTER1 to obtain a first-channel frequency divider clock signal D2; the second-channel frequency divider clock signal generation unit 102 is used to sample the first counter COUNTER1 and adjust the second counter COUNTER1 according to the sampling result. R2 performs a reset operation, generating the second frequency-divided clock signal C2; the target clock signal generation unit 103 generates the target clock signal DIV_N based on the first frequency-divided clock signal D2 and the second frequency-divided clock signal C2. The duty cycle of the target clock signal DIV_N is 50%. A fixed 50% duty cycle output can be achieved using two counters, eliminating the need for a duty cycle adjustment circuit with increased area and redundant feedback adjustment loops. This reduces power consumption and design cost, and solves the problems of existing frequency divider circuits that require adding a duty cycle adjustment circuit to achieve duty cycle adjustment, resulting in larger area and power consumption, and the problem of increased design complexity caused by adding a feedback circuit for adjustment.

[0085] The features described in the various embodiments of this specification can be substituted for or combined with each other. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the description of the method embodiments. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort. Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0086] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0087] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A programmable frequency divider circuit, characterized in that, include: The unit generates a first-channel frequency-divided clock signal, a second-channel frequency-divided clock signal, and a target clock signal; The first frequency-divided clock signal generation unit and the second frequency-divided clock signal generation unit share the first counter; The first frequency-divided clock signal generation unit is used to sample the first counter to obtain the first frequency-divided clock signal; The second frequency-divided clock signal generation unit is used to sample the first counter, reset the second counter according to the sampling result, and generate the second frequency-divided clock signal. The target clock signal generation unit is used to generate a target clock signal based on the first frequency-divided clock signal and the second frequency-divided clock signal, wherein the duty cycle of the target clock signal is 50%.

2. The programmable frequency divider circuit according to claim 1, characterized in that, The first frequency-divided clock signal generation unit includes: the first counter and the second flip-flop; The reset terminal of the first counter is connected to the data terminal of the second flip-flop, and the clock control terminal of the first counter receives the clock signal to be divided. The clock control terminal of the second flip-flop receives the inverted signal of the clock signal to be divided, and the output terminal of the first flip-flop outputs the first divided clock signal.

3. The programmable frequency divider circuit according to claim 2, characterized in that, The second flip-flop is a D flip-flop.

4. The programmable frequency divider circuit according to claim 1, characterized in that, The second frequency-divided clock signal generation circuit includes: the first counter, the second counter, the first flip-flop, and a clock signal selection unit; The output terminal of the first counter is connected to the data terminal of the first flip-flop, and the clock control terminal of the first counter receives the clock signal to be divided. The output terminal of the clock signal selection unit is connected to the clock control terminal of the first flip-flop and the clock control terminal of the second counter, and is used to select one of the clock signal to be divided and the inverted signal of the clock signal to be divided as the sampling clock signal output according to the input division number of the programmable frequency divider circuit. The output terminal of the first flip-flop is connected to the reset terminal of the second counter; The output terminal of the second counter outputs the second frequency-divided clock signal.

5. The programmable frequency divider circuit according to claim 4, characterized in that, The input division number of the programmable frequency divider circuit is an even number, and the clock signal selection unit selects the inverted signal of the clock signal to be divided as the sampling clock signal output.

6. The programmable frequency divider circuit according to claim 4, characterized in that, The input division number of the programmable frequency divider circuit is an odd number, and the clock signal selection unit selects the clock signal to be divided as the sampling clock signal output.

7. The programmable frequency divider circuit according to claim 4, characterized in that, The clock signal selection unit includes: a gate; The first input terminal of the selector receives the clock signal to be divided. The second input terminal of the selector receives the inverted signal of the clock signal to be divided; The control terminal of the selector receives the input division number from the programmable frequency divider circuit; The output of the selector serves as the output of the clock signal selection unit.

8. The programmable frequency divider circuit according to claim 4, characterized in that, The first trigger is a D trigger.

9. The programmable frequency divider circuit according to claim 2, characterized in that, The target clock signal generation unit includes: a third flip-flop; The reset terminal of the third flip-flop is connected to the output terminal of the second counter to receive the second frequency-divided clock signal; The clock control terminal of the third flip-flop is connected to the output terminal of the second flip-flop and receives the first frequency-divided clock signal; The data terminal of the third trigger is set to 1; The target clock signal is output from the output terminal of the third flip-flop.

10. The programmable frequency divider circuit according to claim 9, characterized in that, The third trigger is a D trigger.

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