Modulation and demodulation method for unmanned aerial vehicle communication

Abstract

The invention discloses a modulation and demodulation method for unmanned aerial vehicle communication, which is realized based on a Xilinx Zynq-7000 series FPGA (Field Programmable Gate Array) hardware platform and is suitable for a 50km-level long-distance and high-speed moving scene. A modulation end adopts a 3pi / 8 dynamic phase rotation algorithm to eliminate phase ambiguity, an I / Q signal is generated through an assembly line CORDIC algorithm, a raised cosine filter with a roll-off coefficient of 0.35 is configured, and out-of-band rejection is greater than 45dB. A demodulation end combines an improved Costas ring and a Gardner timing synchronization technology, can realize + / -25kHz frequency offset capture and 0.5-degree RMS phase tracking precision, adopts a normalized LMS equalizer to suppress multipath distortion, and integrates a diversity antenna dynamic switching mechanism. A layered clock architecture and a resource reuse strategy are adopted in the system, logic resource occupation and power consumption are reduced, and 20 / 5MBaud symbol rate dynamic switching is supported. According to actual measurement, the throughput reaches 48.6 Mbps under the transmission distance of 52 km, the end-to-end time delay is smaller than 12.7 ms, the system can adapt to the temperature environment of-40 DEG C to + 85 DEG C and the high-speed moving condition of 200 km / h, frequency hopping anti-interference and error correction capacity is achieved, and the high-reliability communication requirement of the unmanned aerial vehicle in the complex environment is met.

Description

Technical Field

[0001] A modulation and demodulation method for UAV communication is proposed, which is suitable for high-efficiency communication scenarios with 50km UAV data links and features strong noise resistance and high spectrum utilization. Background Technology

[0002] In the field of digital modulation technology, octal phase shift keying (8PSK) is a highly efficient multi-level modulation method. By mapping every 3 bits of binary information to 8 phase states of the carrier, it has a higher spectral efficiency (up to 6 bits / s / Hz) compared to traditional modulation methods such as QPSK. This characteristic makes it widely used in satellite communication, digital broadcast television and mobile communication systems.

[0003] The existing 8PSK technology mainly faces the following technical bottlenecks: (1) Phase ambiguity problem: Traditional coherent demodulation has π / 4 phase uncertainty, which leads to an increase in demodulation bit error rate. Existing solutions mostly use differential coding technology (D8PSK), but this will increase the signal-to-noise ratio requirement by an additional 3-5dB. (2) Amplitude fluctuation defect: The non-constant envelope characteristic of 8PSK results in a signal peak-to-average power ratio of up to 3.7dB, which imposes stringent requirements on the linearity of the RF power amplifier and significantly increases the power amplifier power consumption in mobile platform applications such as drones. (3) High implementation complexity: Existing DSP processor-based implementation schemes are limited by serial processing architecture, making it difficult to meet the stringent real-time requirements of UAV data links, while traditional ASIC schemes lack waveform reconstruction flexibility.

[0004] In recent years, software-defined radio (SDR) technology has offered new solutions to these problems. Integrated RF front-end devices such as the AD9361 support programmable baseband processing, and combined with the parallel processing advantages of FPGAs, can effectively improve system adaptability. Although existing patents propose a general modulation architecture based on FPGAs, they do not offer optimization solutions for the phase ambiguity and amplitude distortion problems of 8PSK. While the π / 8 rotation technology disclosed in the literature can improve signal envelope characteristics, its hardware implementation suffers from excessive delay in the constellation rotation module.

[0005] The innovation of this invention lies in the following: by constructing a hardware platform based on the AD9361 RF front end, and by adopting an optimized 3π / 8 dynamic phase rotation algorithm and an improved biorthogonal demodulation structure, hardware acceleration of key modules such as symbol mapping, shaping filtering, and carrier synchronization is achieved in the FPGA, which effectively solves the problems of traditional 8PSK systems in terms of phase stability, power efficiency, and real-time performance. Summary of the Invention

[0006] This invention provides a modulation and demodulation method for unmanned aerial vehicle (UAV) communication, aiming to overcome the technical bottlenecks of traditional UAV communication in terms of transmission distance, environmental adaptability, and hardware power consumption. Through an innovative digital modulation architecture, adaptive RF configuration algorithm, and low-power hardware design, a highly reliable, multipath-resistant, and dynamically reconfigurable long-distance communication system is constructed, meeting the stringent requirements of high-speed data links for UAVs in complex electromagnetic environments.

[0007] The core solution of this invention is to construct a software-defined radio platform based on the Xilinx Zynq-7000 series FPGA. Specific technical implementation includes: in the RF front-end dynamic configuration system, the AD9361 programmable RF chip (hardware interface as attached) is used. Figure 11 As shown), tri-state bidirectional control is implemented via the SPI bus (see the CONFIG_SI5338 module code segment for details). An innovative multi-clock domain management architecture is designed—the PLL_OSC module generates three clock channels: 40MHz / 110MHz / 200MHz (timing relationships are shown in the appendix). Figure 12 Combined with the SI5338 clock generator, dynamic frequency synthesis from 24MHz to 125MHz is achieved (see attached configuration procedure). Figure 12 Waveform), and developed an online parameter reconfiguration engine to support 0.5dB step adjustment of transmit power in 10ms (implemented through a 16-bit digital attenuator, register mapping see PARAMETER_AD9361 module) and continuous adjustment of the 70-6000MHz operating frequency band (frequency word configured through frq_tx_din / frq_rx_din bus).

[0008] Regarding the 8PSK modulation and demodulation hardware accelerator, the modulation end employs a digital quadrature upconverter based on the CORDIC algorithm (the core operation unit is shown in the T8PSK module), achieving independent I / Q channel output through dual 12-bit DACs (data paths are shown in the dac_data_i1 / dac_data_q1 interfaces). Simultaneously, a built-in raised cosine filter with a roll-off factor α=0.35 achieves out-of-band rejection >45dB. The demodulation end utilizes an improved Costas ring carrier recovery module (frequency offset acquisition range ±25% symbol rate; convergence process comparison is shown in the appendix). Figure 8 →9) Combined with the symbol synchronization circuit based on Gardner algorithm (time recovery logic is in the R8PSK module), and an adaptive equalizer using the normalized LMS algorithm, the convergence speed is improved by 40%.

[0009] To address the channel characteristics of UAVs, the system developed a multi-mode anti-interference strategy that dynamically switches between directional and omnidirectional antenna modes (control logic is shown in the ANT_MODE port). This is combined with real-time RSSI monitoring and a fast AGC response mechanism (signal strength detection is shown in the rssi_1 / rssi_2 registers). A lightweight forward error correction scheme using (3,1,7) convolutional codes and 128-interleaving depth concatenated coding was designed, achieving a 6.2dB coding gain through the DECODER_CONV_DIFF_SCRA module. For low-power hardware implementation, an innovative layered clock gating technique was adopted—the core modulation module operates at 110MHz (clock tree shown in the clk110m network), while the auxiliary control module operates at 40MHz (clock domain partitioning is shown in the CLK40M annotation). Simultaneously, resource reuse strategies such as shared FIR filter banks (multiplexed structure shown in FIR63_Dec4 instantiation) were used to reduce logic consumption. Ultimately, the dynamic partial reconfiguration (PR) region accounts for less than 18% of the total FPGA resources. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This invention uses MATLAB to simulate an 8PSK constellation diagram, demonstrating the signal phase distribution. Figure 2 These are comparison diagrams of the time-domain waveforms simulated in MATLAB in this invention, verifying the time-domain characteristics of the modulated signal; Figure 3 This invention presents a MATLAB simulation of the received signal spectrum analysis (three sub-graphs): (a) Spectrum after bandpass filtering: verifying the RF signal center frequency (30kHz) and bandwidth limitations. (b) Baseband spectrum after downconversion: checking the effect of the mixer in shifting the signal to baseband. (c) Spectrum after low-pass filtering: confirming that residual high-frequency components are suppressed and the purity of the baseband signal is improved. Figure 4 This invention relates to the frequency response of a bandpass filter simulated using MATLAB. Figure 5 This invention relates to the MATLAB simulation of the low-pass filter's frequency response. Figure 6 This invention relates to the I-branch time-domain waveform extraction and interpolation comparison. Figure 7 This invention compares the time-domain waveform extraction and interpolation of the Q-branch. Figure 8 This is the receiver symbol constellation diagram of the present invention when it is not synchronized; Figure 9 This is the synchronized receiver symbol constellation diagram of the present invention; Figure 10 This is the phase-frequency characteristic diagram of the carrier synchronization loop of the present invention; Figure 11 This is a simulation schematic of the Vivado 8PSK modulation and demodulation system in this invention; Figure 12 This is the FPGA implementation layout diagram of the AD9361-based 8PSK system in this invention; Figure 13 This is a waveform diagram for verifying the dynamic parameters of FPGA hardware-coordinated 8PSK modulation and demodulation in this invention. Figure 14 This is a framework overview of the implementation method in this invention; Detailed Implementation

[0012] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0013] To make the technical solution of the present invention clearer, the present invention will be further described below with reference to the accompanying drawings.

[0014] After completing the construction and configuration of the hardware platform (Xilinx Zynq-7000 series FPGA and AD9361 RF chip), the core of this invention lies in the efficient implementation of the 8PSK modulation and demodulation algorithm in the FPGA. The following will describe in detail its specific implementation process from code design to system integration.

[0015] I. Code Implementation and Optimization of the Modulator (T8PSK Module) The core task of the modulator code is to accurately and efficiently convert the input binary bitstream into I / Q analog signals that can be transmitted by the AD9361. The key to its implementation lies in balancing algorithm accuracy with hardware resource consumption.

[0016] First, the code needs to complete the symbol mapping from 3 bits to 8 phase states. To fundamentally solve the phase ambiguity problem of traditional 8PSK, we implemented a 3π / 8 dynamic phase rotation algorithm in the code. This algorithm is not a simple lookup table mapping, but uses a sophisticated state machine to continuously accumulate a fixed phase increment (3π / 8) on the base value of each symbol's phase, thereby uniformly distributing the trajectory of constellation points, effectively improving the signal envelope characteristics, and reducing the peak-to-average power ratio (PAPR).

[0017] After mapping the phase radian value, the next step is to convert it into specific values ​​for in-phase (I) and quadrature (Q) branches using the CORDIC algorithm. We implemented this using a three-stage pipelined CORDIC architecture. In the code, this core computation unit is designed as a highly parallel data path, decomposing complex trigonometric function operations into a series of shift and addition operations. This pipelined design ensures that a complete set of coordinate rotation calculations can be completed within each system clock cycle, keeping the phase calculation error strictly controlled within 0.9° RMS, while meeting the real-time requirements at a high symbol rate of 20 MBaud.

[0018] Subsequently, the I / Q data stream output by CORDIC enters the shaping and filtering stage. We wrote code with symmetric compression storage for the raised cosine filter (α=0.35). Utilizing the symmetry of the FIR filter coefficients, the code logic retains only half of the coefficients during storage, and during convolution operations, it first adds the input data at the symmetric points before multiplying it with the stored coefficients. This optimization strategy significantly reduces Block RAM resource consumption by approximately 35%, while ensuring the filter's excellent out-of-band rejection capability (>45dB). Its superior filtering characteristics can be further demonstrated by... Figure 4 and attached Figure 5 The spectral response was verified.

[0019] The digital I / Q signals ultimately generated by the modulator are sent to the transmit channel of the AD9361 through the dac_data_i1 and dac_data_q1 interfaces defined in the code, completing the digital-to-analog conversion and RF up-conversion.

[0020] II. Synchronization and Signal Recovery Mechanism of the Demodulator (R8PSK Module) The demodulator code is more complex to design, and its core challenge lies in how to accurately recover the original data from the received signal that is affected by channel impairments (such as frequency offset, timing error, and multipath). We adopted a multi-level synchronization and adaptive processing mechanism to address this challenge.

[0021] The demodulation process begins with coarse synchronization, i.e., frame detection. The code implements a sliding correlator based on a specific preamble. This module performs real-time correlation operations between the received data and a locally stored known preamble sequence. When the correlation peak exceeds a dynamically adjustable threshold (range -35dBm to -25dBm), it is determined as the start of a new frame. The acquisition time for this process is optimized to within 15μs, ensuring the system's fast response capability.

[0022] After determining the frame start position, the fine synchronization stage begins to correct symbol timing errors. The core of our code is the Gardner timing error detection algorithm combined with a quadratic interpolation filter. The advantage of the Gardner algorithm is that it requires only two sampling points per symbol period, resulting in low computational complexity, making it very suitable for FPGA implementation. The digitally controlled oscillator (NCO) and loop filter in the code generate control signals to drive the interpolation filter to extract symbol values ​​at the optimal sampling time, successfully suppressing the timing error to below 0.1 times the symbol period. A comparison of the waveforms of the I and Q signals after timing recovery clearly shows the difference. Figure 6 and attached Figure 7 This was observed in [the context].

[0023] Meanwhile, carrier synchronization is handled by an improved Costas loop. This loop, represented in the code, is a complete phase-locked structure, including a phase detector for 8PSK modulation, a second-order loop filter, and an NCO. The introduction of the second-order filter enables the loop to track frequencies, achieving a frequency offset capture range of up to ±25kHz. After the loop stabilizes, its residual phase jitter is less than 0.5° RMS. The significant improvement in carrier synchronization can be seen by comparing it before synchronization (see attached diagram). Figure 8 (Discrete constellation points) and after synchronization (attached) Figure 9 (The constellation points are clearly focused) Figure 1 It's obvious.

[0024] To further improve performance under adverse channel conditions, a normalized LMS adaptive equalizer (16 taps, step factor μ=0.01) is integrated at the end of the demodulation code to compensate for inter-symbol interference caused by multipath effects. Finally, the equalized soft-decision information is fed into a forward error correction decoding module based on (3,1,7) convolutional codes and an interleaver with a depth of 128, thereby achieving a coding gain of 6.2dB.

[0025] III. Collaboration and System Integration with AD9361 The effective operation of the entire modulation and demodulation code relies on close collaboration with the AD9361 RF front-end. At the code level, we have implemented sophisticated interface control logic.

[0026] In the receiving direction, the 12-bit digital I / Q data generated by the AD9361 after down-conversion is input into the FPGA via LVDS differential pairs (e.g., rx_data_in_p / n) and directly read by the signal processing modules in the code (e.g., adc_data_i1 / q1). In the transmitting direction, the processed I / Q data is sent to the AD9361's DAC through the corresponding LVDS interface. More importantly, the dynamic configuration capability is crucial. The code uses the AXI-Lite bus protocol to precisely control the AD9361's internal registers, enabling online reconfiguration of parameters such as operating frequency and gain. The write cycle of a single register is less than 15μs, laying the foundation for advanced functions such as frequency hopping interference suppression. The hardware interconnection and data flow of the entire system can be found in the appendix. Figure 11 To understand the schematic diagram, and attach... Figure 13 The dynamic parameter verification waveforms provide an intuitive basis for system debugging and performance evaluation.

[0027] In summary, through the detailed code-level design and optimization described above, this invention successfully constructed a high-performance, highly reliable 8PSK modulation and demodulation system on an FPGA, effectively meeting the stringent communication requirements of UAV data links in long-distance, high-speed mobile scenarios. The overall system framework and data flow can be found in the appendix. Figure 14 An overview.

Claims

1. A modulation and demodulation method for unmanned aerial vehicle (UAV) communication, characterized in that, The system achieves 50km-level UAV communication through a hardware platform integrated on a Xilinx Zynq-7000 series FPGA. It includes a symbol mapping module, a shaping filter module, a carrier synchronization module, and a hierarchical clock architecture. The symbol mapping module uses a 3π / 8 dynamic phase rotation algorithm to eliminate phase ambiguity. The shaping filter module is configured with a raised cosine filter with a roll-off factor α=0.35 to achieve out-of-band rejection >45dB. The carrier synchronization module uses an improved Costas ring and a digital phase-locked loop (DPLL) to achieve ±25kHz frequency offset acquisition and phase tracking with a residual frequency offset error <10Hz. The hierarchical clock architecture uses a 110MHz master clock to drive the core modulation and demodulation module and a 40MHz clock to drive the control module, with a global clock skew ≤0.15ns and a logic resource reuse rate >80%. The system achieved a measured throughput of 48.6Mbps and an end-to-end latency of <12.7ms in a 50km communication scenario, supporting UAV high-speed movement of 200km / h and extreme temperature environments ranging from -40℃ to +85℃.

2. The modulation and demodulation method for UAV communication according to claim 1, characterized in that, The modulation end uses a three-stage pipelined CORDIC algorithm to generate I / Q signals with a phase calculation error of <0.9°RMS. It outputs dynamic symbol rates of 5-20MBaud through dual 12-bit DACs with an EVM of <5%. The modulation end integrates a dynamic symbol rate switching mechanism, which enables seamless switching between 20MBaud high-speed mode and 5MBaud power-saving mode (switching time ≤2.1ms) through the FPGA register configuration word (do_send_rate). It also uses a pre-distortion compensation module to reduce the signal peak-to-average power ratio (PAPR) to 2.8dB, and combines digital pre-filtering technology to compensate for the in-band unevenness of the AD9361 RF channel (<±0.3dB).

3. The modulation and demodulation method for UAV communication according to claim 1, characterized in that, The demodulation unit achieves high-precision signal recovery through a multi-level synchronization and adaptive anti-interference mechanism, including a coarse synchronization module based on preamble sliding correlation detection (acquisition time <15μs, detection threshold dynamic adjustment range -35dBm~-25dBm), a fine synchronization module cascaded with Gardner timing error detection and a secondary interpolation filter (timing error <0.1 times the symbol period), and a normalized LMS equalizer (tap length 16, step factor μ=0.01) to suppress multipath distortion. The demodulation unit further integrates a diversity reception control module, which dynamically switches between omnidirectional and directional antenna modes based on real-time RSSI intensity monitoring, with a switching response time of <5ms. It also combines an improved Costas ring with a second-order loop filter to achieve ±25% symbol rate frequency offset acquisition and stable carrier recovery with phase jitter <0.5°RMS.

4. The modulation and demodulation method for UAV communication according to claim 1, characterized in that, The system achieves low-power design through dynamic clock gating and resource reuse strategies, with static power consumption ≤1.2W and peak transmit power consumption <3.5W. It also employs a concatenated coding scheme of (3,1,7) convolutional codes and a depth 128 interleaver, achieving a coding gain of 6.2dB in AWGN channels and a bit error rate <1×10⁻⁶ after error correction. -6 The system supports frequency hopping anti-interference mode, and uses FPGA dynamic partial reconfiguration (PR) technology to quickly hop frequencies within a 56MHz bandwidth with a switching time of <8ms. It also uses a temperature compensation algorithm to ensure the performance stability of key modules (CORDIC, Costas ring) within the range of -40℃ to +85℃, with an EVM degradation of <0.4%, meeting the stringent requirements of UAVs in complex electromagnetic environments and extreme climates.

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