Dual-cycle communication state machine jumping method and device
By determining the communication channel status and delaying signal transmission in the FPGA system, the communication blocking problem when dual-cycle signals share the same channel is solved, thus achieving long-term smooth communication and system robustness.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING INST OF ENVIRONMENTAL FEATURES
- Filing Date
- 2026-02-02
- Publication Date
- 2026-05-15
AI Technical Summary
In FPGA systems, when dual-cycle signals share a communication channel, signal requests may collide at specific times, causing communication channel blockage and affecting the long-term smoothness and robustness of the system's communication channel.
By continuously judging the communication channel status and delaying signal transmission to avoid signal collisions, a dual-cycle communication state machine transition method is adopted, including immediate transmission in idle state and delayed transmission in busy state. Combined with FPGA to implement communication receiving and transmitting modules, a fixed heartbeat signal and event valid signal are formed.
It effectively avoids signal transmission conflicts, ensuring long-term smooth communication channels and system robustness under extreme operating conditions.
Smart Images
Figure CN122053427A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of programmable gate array technology, and in particular to a method and apparatus for switching between two-cycle communication state machines. Background Technology
[0002] In Field-Programmable Gate Array (FPGA) systems, the state machine, as the control core, often needs to manage access to shared communication channels. A typical application scenario is that the system contains an important fixed-period signal, such as a "heartbeat" signal used to confirm whether the system is operating normally. This signal needs to occupy the communication channel periodically and without obstruction. Under normal circumstances, a single-period signal will not cause channel blockage. However, when the host computer injects specific traffic, it introduces another fixed and stable but phase-different periodic signal. At this point, a "dual-period signal sharing the communication channel" model is formed. Because the timing difference between the signal generated by the valid event of the host computer and the inherent heartbeat signal cannot be controlled, their requests will collide at certain specific points in time, inevitably causing blockage.
[0003] The core problem that this invention aims to solve is to fundamentally avoid the accumulation of blockages through a state machine transition method, thereby ensuring the long-term smooth operation of the communication channel and the robustness of the system under extreme conditions. Summary of the Invention
[0004] This invention provides a dual-cycle communication state machine transition method, apparatus, electronic device, and storage medium, which can avoid blocking when different signals are sent.
[0005] In a first aspect, embodiments of the present invention provide a two-cycle communication state machine transition method, including: The system continuously determines whether the communication channel is occupied in order to generate communication channel status information; the communication channel status information includes an idle state when no signal is being transmitted and a busy state when a signal is being transmitted. When a valid event signal is received from the host computer, the current state of the communication channel is determined to decide whether to send or wait to send the valid event signal. Specifically, the signal is sent when the channel is idle, delayed when the channel is busy, and sent immediately when the communication channel returns to an idle state. A fixed heartbeat signal is periodically generated to determine the current state of the communication channel and to decide whether to send or wait to send the fixed heartbeat signal. Specifically, it is sent when the communication channel is idle, delayed when the communication channel is busy, and sent immediately when the communication channel returns to an idle state.
[0006] One possible design also includes: According to the communication protocol, communication with the host computer is implemented based on FPGA, and control commands from the host computer are received.
[0007] In one possible design, the fixed heartbeat signal is formed in the following manner: A counter with a set period is configured through a register. When the value of the counter reaches the preset heartbeat period, the valid heartbeat signal will be pulled high for one clock cycle in the next clock cycle, and then automatically pulled low.
[0008] In one possible design, the valid event signal is generated as follows: When a valid event command is detected from the host computer, the valid event signal is pulled high for one clock cycle in the next clock cycle after the rising edge of the signal is detected, and then automatically pulled low.
[0009] Secondly, embodiments of the present invention also provide a dual-cycle communication state machine switching device for implementing the method described above, the device comprising a communication receiving part, a communication transmitting part, and an FPGA-based communication control part.
[0010] In one possible design, the communication control section of the FPGA includes the following modules: information packet assembly module, event judgment module, state machine transition control module, state machine logic module, and information buffer module; The working order of each module is as follows: The information packet assembly module acquires information transmitted by each subsystem and completes the information packet sending task. The event determination module completes event determination by receiving valid signals from the receiving section; The state machine transition control module controls the state to complete the transition operation based on the judgment result; The state machine logic module completes the state logic output based on the state transition results and signal state tracking. The information buffer module buffers the information to be sent based on the output of the state machine logic module.
[0011] In one possible design, the workflow of the communication receiving section is as follows: Receive control commands from the host computer according to the transmission protocol; The received instruction information is sent to the communication control section.
[0012] In one possible design, the workflow of the communication transmission section is as follows: Receive control commands and output information from the communication control unit; Establish channel status sensing signals; The channel status sensing signal is fed back to the communication control section.
[0013] Thirdly, embodiments of the present invention also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, it implements the method described in any embodiment of this specification.
[0014] Fourthly, embodiments of the present invention also provide a computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, causes the computer to perform the methods described in any embodiment of this specification.
[0015] Compared with the prior art, the present invention has at least the following beneficial effects: By judging the state of the communication channel, when signal transmission collisions occur, the later signals are delayed, thus ultimately resolving the signal transmission collision problem. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a flowchart of the method provided in this application. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0019] This invention provides a two-cycle communication state machine transition method, including: The system continuously determines whether the communication channel is occupied in order to generate communication channel status information; the communication channel status information includes an idle state when no signal is being transmitted and a busy state when a signal is being transmitted. When a valid event signal is received from the host computer, the current state of the communication channel is determined to decide whether to send or wait to send the valid event signal. Specifically, the signal is sent when the channel is idle, delayed when the channel is busy, and sent immediately when the communication channel returns to an idle state. A fixed heartbeat signal is periodically generated to determine the current state of the communication channel and to decide whether to send or wait to send the fixed heartbeat signal. Specifically, it is sent when the communication channel is idle, delayed when the communication channel is busy, and sent immediately when the communication channel returns to an idle state.
[0020] Specifically, please refer to Figure 1 The method provided in this application can be divided into the following steps in detail: Step 100: According to the communication protocol, implement communication with the host computer based on the FPGA and receive control commands from the host computer; Step 102, Information Packetization Module, summarizes the information to be uploaded by each lower-level subsystem and encodes and packages it according to the transmission protocol; Step 104: The event judgment module performs event validity judgment on the control commands received from the host computer according to the protocol and generates an event validity pulse signal. Generation of valid heartbeat signal: A counter with a one-cycle interval is set through a register. When the value of the counter reaches the preset heartbeat cycle, the valid heartbeat signal will be pulled high for one clock cycle in the next clock cycle, and then automatically pulled low. Event valid signal generation: When an event valid command is detected from the host computer, the event valid signal is pulled high for one clock cycle in the next clock cycle after the rising edge of the signal is detected, and then automatically pulled low. Step 106: The state transition control module controls the state machine to perform state transitions based on the valid event pulse signal and the state information fed back from the communication transmission part. Initially, the state machine is at state "S0"; When the event valid signal goes high, if the status perception signal of the sending part is "idle", the state jumps from "S0" to "S1"; when the status perception signal of the sending part changes from "idle" to "busy", the state jumps from "S1" to "S2"; when the status perception signal of the sending part changes from "busy" to "idle" and there are no other valid signals, the state jumps from "S2" to "S0"; when the status perception signal of the sending part is "busy", and a valid heartbeat signal is generated, the state jumps from "S2" to "S3"; when the status perception signal of the sending part changes from "busy" to "idle", the state jumps from "S3" to "S4"; when the status perception signal of the sending part changes from "busy" to "idle", the state jumps from "S4" to "S0". When the event valid signal goes high, if the status perception signal of the sending part is "busy", the state jumps from "S0" to "S5"; when the status perception signal of the sending part changes from "busy" to "idle", the state jumps from "S5" to "S6"; when the status perception signal of the sending part changes from "idle" to "busy", the state jumps from "S6" to "S7"; when the status perception signal of the sending part changes from "busy" to "idle", the state jumps from "S7" to "S0". Step 108: The state machine logic module, based on the state transition results and signal tracking, implements the logic output of the corresponding state. S0: Buffer module initialization; In the first clock cycle of the valid heartbeat signal, the summary information checksum is calculated; In the second clock cycle, the transmission information is loaded; In the third clock cycle, the buffer module write enable is pulled high; In the fourth clock cycle, the buffer module write enable is pulled low and the read enable is pulled high; In the fifth clock cycle, the buffer module read enable is pulled low and the valid transmission signal is pulled high; In the sixth clock cycle, the valid transmission signal is pulled low. S1: In the first clock cycle of the valid event signal, the checksum of the feedback information is calculated and the buffer module is initialized; in the second clock cycle, the information to be sent is loaded; in the third clock cycle, the buffer module write enable is pulled high; in the fourth clock cycle, the buffer module write enable is pulled low and the read enable is pulled high; in the fifth clock cycle, the buffer module read enable is pulled low and the valid send signal is pulled high; in the sixth clock cycle, the valid send signal is pulled low. S2: Buffer module initialization; S3: No logical output; S4: In the first clock cycle of the falling edge of the state awareness signal (from "busy" to "idle"), the checksum of the summary information is calculated and the buffer module is initialized; in the second clock cycle, the information to be sent is loaded; in the third clock cycle, the buffer module write enable is pulled high; in the fourth clock cycle, the buffer module write enable is pulled low and the read enable is pulled high; in the fifth clock cycle, the buffer module read enable is pulled low and the transmit valid signal is pulled high; in the sixth clock cycle, the transmit valid signal is pulled low. S5: Buffer module initialization; S6: In the first clock cycle of the falling edge of the state awareness signal (from "busy" to "idle"), calculate the checksum of the feedback information and initialize the buffer module; in the second clock cycle, load the transmission information; in the third clock cycle, pull the buffer module write enable high; in the fourth clock cycle, pull the buffer module write enable low and read enable high; in the fifth clock cycle, pull the buffer module read enable low and pull the transmit valid signal high; in the sixth clock cycle, pull the transmit valid signal low. S7: Buffer module initialization; Step 110, the information buffer module, implements data buffering by controlling the read / write validity signal through logic output; Step 112, Communication Transmission Section: Establishes contact with the host computer according to the communication protocol, sends buffered data to the host computer according to the valid transmission signal output by the logic, and sets the channel status perception signal to be fed back to the status jump control module at the same time. When there is no sending task, the sending module is in an idle state. At this time, the "busy" signal is low and the "idle" signal is high, indicating that the channel is available. Upon receiving a transmission command, the transmitting module immediately pulls the "busy" signal high and the "idle" signal low in the next clock cycle. This indicates that the transmitting module has entered a "busy" state and has locked the right to use the communication channel. Once the data transmission is complete, the sending module immediately pulls the "busy" signal low and the "idle" signal high. This indicates that the transmission is finished, the communication channel is released, and it returns to an idle state where it can be used again.
[0021] This invention also provides a dual-cycle communication state machine switching device for implementing the method described above. The device includes a communication receiving part, a communication transmitting part, and an FPGA-based communication control part.
[0022] In some embodiments of the present invention, the communication control section of the FPGA includes the following modules: information packet assembly module, event judgment module, state machine transition control module, state machine logic module, and information buffer module; The working order of each module is as follows: The information packet assembly module acquires information transmitted by each subsystem and completes the information packet sending task. The event determination module completes event determination by receiving valid signals from the receiving section; The state machine transition control module controls the state to complete the transition operation based on the judgment result; The state machine logic module completes the state logic output based on the state transition results and signal state tracking. The information buffer module buffers the information to be sent based on the output of the state machine logic module.
[0023] In some embodiments of the present invention, the workflow of the communication receiving section is as follows: Receive control commands from the host computer according to the transmission protocol; The received instruction information is sent to the communication control section.
[0024] In some embodiments of the present invention, the workflow of the communication transmission section is as follows: Receive control commands and output information from the communication control unit; Establish channel status sensing signals; The channel status sensing signal is fed back to the communication control section.
[0025] It is understood that the structures illustrated in the embodiments of the present invention do not constitute a specific limitation on a two-cycle communication state machine transition device. In other embodiments of the present invention, a two-cycle communication state machine transition device may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.
[0026] The information interaction and execution process between the modules in the above-mentioned device are based on the same concept as the method embodiment of the present invention, and the specific details can be found in the description of the method embodiment of the present invention, and will not be repeated here.
[0027] This invention also provides an electronic device, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements a two-cycle communication state machine transition method according to any embodiment of this invention.
[0028] This invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to execute a two-cycle communication state machine transition method according to any embodiment of this invention.
[0029] Specifically, a system or apparatus equipped with a storage medium may be provided, on which software program code implementing the functions of any of the embodiments described above is stored, and the computer (or CPU or MPU) of the system or apparatus may read and execute the program code stored in the storage medium.
[0030] In this case, the program code read from the storage medium can itself implement the function of any of the above embodiments, and therefore the program code and the storage medium storing the program code constitute part of the present invention.
[0031] Storage media embodiments for providing program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, program code can be downloaded from a server computer via a communication network.
[0032] Furthermore, it should be clear that not only can the program code read by the computer be executed, but also the operating system or other components operating on the computer can be instructed based on the program code to perform some or all of the actual operations, thereby realizing the function of any of the embodiments described above.
[0033] Furthermore, it is understood that the program code read from the storage medium is written to the memory set in the expansion board inserted into the computer or to the memory set in the expansion module connected to the computer. Then, based on the instructions of the program code, the CPU or other components installed on the expansion board or expansion module execute some and all of the actual operations, thereby realizing the function of any of the above embodiments.
[0034] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0035] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as ROM, RAM, magnetic disk, or optical disk.
[0036] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A two-cycle communication state machine transition method, characterized in that, include: The system continuously determines whether the communication channel is occupied in order to generate communication channel status information; the communication channel status information includes an idle state when no signal is being transmitted and a busy state when a signal is being transmitted. When a valid event signal is received from the host computer, the current state of the communication channel is determined to decide whether to send or wait to send the valid event signal. Specifically, the signal is sent when the communication channel is idle, delayed when the communication channel is busy, and sent immediately when the communication channel returns to the idle state. A fixed heartbeat signal is periodically generated to determine the current state of the communication channel and to decide whether to send or wait to send the fixed heartbeat signal. Specifically, it is sent when the communication channel is idle, delayed when the communication channel is busy, and sent immediately when the communication channel returns to an idle state.
2. The method according to claim 1, characterized in that, Also includes: According to the communication protocol, communication with the host computer is implemented based on FPGA, and control commands from the host computer are received.
3. The method according to claim 1, characterized in that, The fixed heartbeat signal is generated in the following manner: A counter with a set period is configured through a register. When the value of the counter reaches the preset heartbeat period, the valid heartbeat signal will be pulled high for one clock cycle in the next clock cycle, and then automatically pulled low.
4. The method according to claim 1, characterized in that, The valid event signal is generated in the following manner: When a valid event command is detected from the host computer, the valid event signal is pulled high for one clock cycle in the next clock cycle after the rising edge of the signal is detected, and then automatically pulled low.
5. A dual-cycle communication state machine jump device, characterized in that, The apparatus for implementing the method as described in any one of claims 1-4 includes a communication receiving section, a communication transmitting section, and an FPGA-based communication control section.
6. The apparatus according to claim 5, characterized in that, The communication control section of the FPGA includes the following modules: information packet assembly module, event judgment module, state machine transition control module, state machine logic module, and information buffer module; The working order of each module is as follows: The information packet assembly module acquires information transmitted by each subsystem and completes the information packet sending task. The event determination module completes event determination by receiving valid signals from the receiving section; The state machine transition control module controls the state to complete the transition operation based on the judgment result; The state machine logic module completes the state logic output based on the state transition results and signal state tracking. The information buffer module buffers the information to be sent based on the output of the state machine logic module.
7. The apparatus according to claim 5, characterized in that, The workflow of the communication receiving section is as follows: Receive control commands from the host computer according to the transmission protocol; The received instruction information is sent to the communication control section.
8. The apparatus according to claim 5, characterized in that, The workflow of the communication transmission section is as follows: Receive control commands and output information from the communication control unit; Establish channel status sensing signals; The channel status sensing signal is fed back to the communication control section.
9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor, when executing the computer program, implements the method as described in any one of claims 1-4.
10. A computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, causes the computer to perform the method of any one of claims 1-4.