Audio device, method, device and medium based on dac module optimized delay difference

Abstract

The application relates to the field of audio compensation technology and provides an audio device, a method, equipment and a medium based on DAC module optimized delay difference. The audio device comprises a clock generation circuit which generates a reference clock signal; a clock distribution circuit which buffers the reference clock signal to obtain a first working clock to a DAC module and performs frequency division to obtain a second working clock to a digital audio processing circuit; the digital audio processing circuit processes a digital audio signal according to the second working clock, outputs an audio data stream and a synchronous reference clock signal; the DAC module detects a phase difference between the first working clock and the reference clock signal, generates a phase error signal and filters the phase error signal to obtain a phase adjustment value, adjusts the phase of the first working clock to generate a sampling clock according to the phase adjustment value, makes a sampling time point located in a data stable interval and compensates for a sampling deviation caused by the propagation delay of the first and second working clocks. The application eliminates clock delay mismatch and improves audio linearity and fidelity.

Description

Technical Field

[0001] This invention relates to the field of audio compensation technology, and in particular to an audio device, method, apparatus, and medium for optimizing delay differences based on a DAC module. Background Technology

[0002] In digital audio systems, the DAC module needs to work in conjunction with multiple modules such as the digital demodulation unit, MCU, and USB controller. Each module typically relies on a clock signal of a different frequency. To reduce costs and simplify the circuit, existing solutions generally use a single crystal oscillator combined with frequency divider and buffer circuits to allocate a synchronous clock to each module.

[0003] However, when the reference clock signal is transmitted to the DAC after multiple levels of buffering, frequency division and path allocation, there is a path delay mismatch. This causes the DAC sampling time to be unable to be precisely aligned with the data valid window, resulting in a decrease in the linearity of the audio signal and an increase in distortion, making it difficult to meet the performance requirements of high-resolution audio devices. Summary of the Invention

[0004] This invention provides a method, apparatus, device, medium, and program product for optimizing latency differences based on a DAC module, in order to solve the problem that the sampling time and the effective data window cannot be precisely aligned during audio sampling.

[0005] In a first aspect, embodiments of this application provide an audio device that optimizes latency differences based on a DAC module, comprising:

[0006] The clock generation circuit is configured to generate a reference clock signal;

[0007] The clock distribution circuit is configured to perform multi-level buffering processing on the reference clock signal to obtain a first working clock output to the DAC module, and to perform frequency division processing on the reference clock signal to obtain a second working clock output to the digital audio processing circuit.

[0008] The digital audio processing circuit is configured to process digital audio signals according to the second operating clock to output an audio data stream to the DAC module, and a reference clock signal synchronized with the audio data stream.

[0009] The DAC module is configured as follows:

[0010] The phase difference between the first working clock and the reference clock signal is detected, a phase error signal is generated, and the phase error signal is filtered to generate a phase adjustment value;

[0011] The phase of the first working clock is adjusted according to the phase adjustment value to generate a sampling clock that is synchronized with the first working clock and whose phase can be offset.

[0012] The audio data stream is sampled according to the sampling clock, so that the sampling time is within the data stability range represented by the reference clock signal, in order to compensate for the difference in signal propagation delay between the first working clock and the second working clock.

[0013] Secondly, embodiments of this application provide a method for optimizing delay differences based on a DAC module, applied to an audio device. The audio device includes a clock generation circuit, a clock distribution circuit, a digital audio processing circuit, and a DAC module. The method includes:

[0014] A reference clock signal is generated by the clock generation circuit.

[0015] The reference clock signal is buffered in multiple stages by the clock distribution circuit to obtain the first working clock output to the DAC module, and the reference clock signal is divided to obtain the second working clock output to the digital audio processing circuit.

[0016] The digital audio processing circuit processes the digital audio signal according to the second operating clock to output an audio data stream to the DAC module, as well as a reference clock signal synchronized with the audio data stream.

[0017] The DAC module detects the phase difference between the first operating clock and the reference clock signal, generates a phase error signal, and filters the phase error signal to generate a phase adjustment value.

[0018] The DAC module adjusts the phase of the first working clock according to the phase adjustment value to generate a sampling clock that is synchronized with the first working clock and whose phase can be offset.

[0019] The DAC module samples the audio data stream according to the sampling clock, ensuring that the sampling time is within the stable data range represented by the reference clock signal, thereby compensating for the difference in signal propagation delay between the first and second operating clocks.

[0020] Thirdly, embodiments of this application provide a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the above-described method for optimizing latency differences based on a DAC module.

[0021] Fourthly, embodiments of this application provide a readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method described above for optimizing latency differences based on a DAC module.

[0022] This application provides an audio device for optimizing delay differences based on a DAC module, comprising: a clock generation circuit configured to generate a reference clock signal; a clock distribution circuit configured to perform multi-level buffering processing on the reference clock signal to obtain a first operating clock output to the DAC module, and to perform frequency division processing on the reference clock signal to obtain a second operating clock output to a digital audio processing circuit; a digital audio processing circuit configured to process digital audio signals according to the second operating clock to output an audio data stream to the DAC module, and a reference clock signal synchronized with the audio data stream; the DAC module configured to: detect the phase difference between the first operating clock and the reference clock signal, generate a phase error signal, and filter the phase error signal to generate a phase adjustment value; adjust the phase of the first operating clock according to the phase adjustment value to generate a sampling clock that is synchronized with the first operating clock and whose phase can be offset; and sample the audio data stream according to the sampling clock, so that the sampling time is within the data stability range represented by the reference clock signal to compensate for the signal propagation delay difference between the first and second operating clocks. In the aforementioned audio device that optimizes delay differences based on the DAC module, the DAC module detects the instantaneous phase difference between the first operating clock and the reference clock feedback signal, and dynamically adjusts the phase of the sampling trigger signal according to the detection result. This ensures that the sampling time of the audio data stream is precisely aligned with the first operating clock, eliminating signal propagation delay mismatch caused by differences in clock distribution path length, buffer levels, and frequency division circuits. It fundamentally avoids phase shift between the DAC sampling time and the data valid window, reducing sampling errors and aperture jitter, thereby improving the linearity of the audio signal and reducing total harmonic distortion plus noise (THD+N) to meet the requirements of high-resolution audio devices for clock synchronization accuracy and signal integrity. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of an audio device based on the DAC module to optimize latency differences in one embodiment of the present invention;

[0025] Figure 2 This is a flowchart illustrating a method for optimizing delay differences based on a DAC module in one embodiment of the present invention;

[0026] Figure 3 yes Figure 2 A schematic diagram of the implementation process of step S40;

[0027] Figure 4 yes Figure 2 A schematic diagram of the implementation process of step S50;

[0028] Figure 5 This is a schematic diagram of a clock generation circuit in one embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram of a device for optimizing delay differences based on a DAC module in one embodiment of the present invention;

[0030] Figure 7 This is a schematic diagram of the structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. It should also be understood that, as used in this specification and the appended claims, the term "and / or" refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0033] Furthermore, in the description of this invention and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0034] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of the invention include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0035] It should be understood that the sequence number of each step in the following embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0036] To illustrate the technical solution of the present invention, specific embodiments are described below.

[0037] In digital audio systems, the DAC module needs to work in conjunction with multiple modules such as the digital demodulation unit, MCU, and USB controller. Each module typically relies on a clock signal of a different frequency. To reduce costs and simplify the circuit, existing solutions generally use a single crystal oscillator combined with frequency divider and buffer circuits to allocate a synchronous clock to each module.

[0038] However, when the reference clock signal is transmitted to the DAC after multiple stages of buffering, frequency division, and path allocation, there is inconsistency in propagation path length, number of stages, etc., between it and the audio data stream output by the digital demodulation unit. Due to the aforementioned path delay mismatch, the DAC sampling time and the data valid window cannot be precisely aligned, resulting in decreased linearity and increased distortion of the audio signal, making it difficult to meet the performance requirements of high-resolution audio devices.

[0039] To address the aforementioned issues, this application proposes an audio device and method for optimizing delay differences based on a DAC module. The method involves detecting the instantaneous phase difference between the DAC module's operating clock and the reference clock fed back by the digital audio processing circuit, generating a digital phase error signal, filtering it to obtain a phase control word, and dynamically adjusting the phase of the DAC sampling trigger signal accordingly. This ensures that the sampling time of the audio data stream is precisely aligned with the DAC's operating clock, effectively eliminating signal propagation delay introduced by differences in clock distribution paths, significantly reducing sampling errors and aperture jitter, and improving the linearity and fidelity of the audio signal.

[0040] The audio device based on DAC module delay difference optimization provided in this embodiment of the invention can be applied to, for example... Figure 1 The system shown includes a clock generation circuit, a clock distribution circuit, a DAC module, and a digital audio processing circuit. These modules are connected via PCB traces or an internal bus.

[0041] In practical applications, the method proposed in this application detects the instantaneous phase difference between the DAC module's operating clock and the reference clock fed back by the digital audio processing circuit, generates a digital phase error signal, obtains a phase control word after filtering, and dynamically adjusts the phase of the DAC sampling trigger signal accordingly, so that the sampling time of the audio data stream is precisely aligned with the DAC operating clock, thereby effectively eliminating the signal propagation delay introduced by the difference in clock distribution path, significantly reducing sampling error and aperture jitter, and improving the linearity and fidelity of the audio signal.

[0042] The audio device can be an independent DAC decoder, audio interface, digital player, smartphone, tablet, or other electronic device with audio playback capabilities. The DAC module can be an external independent chip or an IP module integrated into a SoC.

[0043] In one embodiment, such as Figure 2 As shown, a method for optimizing delay differences based on DAC modules is provided, and this method is applied to... Figure 1 The following steps are used as an example to illustrate the process with the audio device shown:

[0044] S10: Generates a reference clock signal through a clock generation circuit.

[0045] S20: The reference clock signal is buffered in multiple stages through the clock distribution circuit to obtain the first working clock output to the DAC module, and the reference clock signal is divided to obtain the second working clock output to the digital audio processing circuit.

[0046] S30: The digital audio signal is processed by the digital audio processing circuit according to the second working clock to output an audio data stream to the DAC module, as well as a reference clock signal synchronized with the audio data stream.

[0047] S40: The phase difference between the first working clock and the reference clock signal is detected by the DAC module, a phase error signal is generated, and the phase error signal is filtered to generate a phase adjustment value.

[0048] S50: The DAC module adjusts the phase of the first working clock according to the phase adjustment value to generate a sampling clock that is synchronized with the first working clock and whose phase can be offset.

[0049] S60: The DAC module samples the audio data stream according to the sampling clock, so that the sampling time is within the data stability range represented by the reference clock signal, in order to compensate for the difference in signal propagation delay between the first working clock and the second working clock.

[0050] In this embodiment, by constructing a closed-loop phase detection and adjustment mechanism inside the DAC module, the DAC's sampling clock can dynamically track the phase of the data stream after being delayed by the digital audio processing circuit. This eliminates the need for additional external delay lines or phase-locked loops, enabling real-time compensation for path delay mismatch. This significantly reduces the difficulty and cost of system design while also significantly improving the signal-to-noise ratio and dynamic range of the audio signal.

[0051] In one embodiment, such as Figure 3 As shown, step S40 above, which detects the phase difference between the first operating clock and the reference clock signal and generates a phase error signal, specifically includes the following sub-steps:

[0052] S41: Input the first operating clock to the multi-phase delay chain to generate a set of delayed clock signals with different phase offsets. The multi-phase delay chain consists of multiple cascaded buffers or inverters, with the output of each cascaded node serving as a tap of the delay chain, and the total delay length of the multi-phase delay chain covering at least one complete cycle of the first operating clock.

[0053] S42: Using the reference clock signal as the sampling clock, the tap state of the multi-phase delay chain is latched in parallel.

[0054] S43: Encode and convert the latched tap state to generate a digital phase error signal.

[0055] In this embodiment, a multi-phase delay chain and parallel latch structure are used to achieve sub-gate resolution time-to-digital conversion. This can complete high-precision phase difference measurement within a single clock cycle, with fast conversion speed, high quantization accuracy, and easy implementation in digital logic within the DAC module. It does not require analog circuits and has significant advantages in power consumption and area.

[0056] In one embodiment, such as Figure 4 As shown, step S50 above adjusts the phase of the first working clock according to the phase adjustment value to generate a sampling clock, specifically including the following sub-steps:

[0057] S51: Input the first operating clock to the phase interpolator.

[0058] S52: The phase interpolator interpolates a sampling clock with a corresponding phase offset between adjacent clock edges of the first operating clock, based on the phase adjustment value. The phase adjustment step of the sampling clock is smaller than the period of the first operating clock, and the adjustment range covers 0° to 360°.

[0059] In this embodiment, a phase interpolator is used to achieve fine movement of the clock edge. The phase adjustment step size can reach the picosecond level, which can compensate for path delay differences with extremely high resolution and ensure that the sampling time is always at the optimal position of the data eye diagram, thereby maximizing the sampling margin and reducing the bit error rate.

[0060] In one embodiment, such as Figure 5 As shown, the clock generation circuit is a low-noise clock generation circuit, specifically a three-overtone crystal oscillator circuit, including: a first crystal X1, a first transistor Q131, a second inductor L2, a first resistor R300, a second resistor R301, a first capacitor C301, and a second capacitor C302. The clock generation circuit generates a reference clock signal with a frequency of 84MHz. This circuit obtains a high-frequency, low-phase-noise clock through overtone oscillation mode, effectively suppressing the phase noise degradation caused by integer multiples.

[0061] In some embodiments, the clock distribution circuit includes a clock buffer circuit and a clock divider circuit. The buffer circuit is configured to perform multi-stage buffering on the reference clock signal, generate a first operating clock, and output it to the DAC module. The clock divider circuit is configured to divide the reference clock signal to generate a second operating clock and output it to the digital audio processing circuit.

[0062] In some embodiments, the audio device that optimizes delay differences based on the DAC module further includes a microcontroller and a USB controller; the clock divider circuit is also configured to: perform frequency mixing on the reference clock signal to generate a third operating clock and output it to the microcontroller; and perform frequency division twice on the reference clock signal to generate a fourth operating clock and output it to the USB controller.

[0063] In one embodiment, such as Figure 5 As shown, the clock buffer circuit includes: a first-stage buffer Q132, corresponding peripheral components for the first-stage buffer Q132, and a second-stage buffer U2. The first operating clock is an 84MHz clock obtained after two-stage buffering via the first-stage buffer Q132 and the second-stage buffer U2. The two-stage buffer structure provides sufficient driving capability and further isolates the pulling effect of subsequent circuits on the oscillator, maintaining a steep clock edge.

[0064] In one embodiment, such as Figure 5 As shown, the clock divider circuit includes:

[0065] Mixer U10 is used to perform NAND gate mixing with the 84MHz reference clock and the feedback 12MHz clock to generate a 96MHz clock.

[0066] The first divider U7 is used to divide the 96MHz clock into a 48MHz clock by a second division.

[0067] The second divider U8 and the third divider U9 are used to divide the 48MHz clock into 24MHz and 12MHz clocks in sequence, with the 12MHz clock being provided as the second working clock to the digital audio processing circuit.

[0068] Buffer U3 is used to buffer the 12MHz clock and provide it as the third working clock to the main clock input of the MCU.

[0069] The fourth divider U1 is used to divide the 12MHz clock into a 6MHz clock as the fourth working clock and provide it to the master clock input of the USB controller.

[0070] This clock distribution network utilizes a single 84MHz crystal oscillator to generate multiple synchronous clocks required by each module through mixing and cascaded frequency division. This avoids the frequency deviation and cost increase caused by multi-crystal oscillator solutions. At the same time, the feedback mixing structure ensures the phase coherence between the clocks, providing a stable reference for DAC delay compensation.

[0071] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0072] In one embodiment, an apparatus for optimizing delay differences based on a DAC module is provided, which corresponds one-to-one with the method embodiments described above. For example... Figure 6 As shown, the device includes:

[0073] Clock generation module: used to generate a reference clock signal, corresponding to... Figure 1 The low-noise clock generation circuit in the middle.

[0074] Clock buffer module: used to buffer the reference clock signal in multiple stages and output the first working clock, corresponding to... Figure 1 The clock buffer circuit in the middle.

[0075] Clock division and synchronization module: Used to perform frequency division, mixing, and secondary frequency division processing on the reference clock signal to generate the second, third, and fourth working clocks, corresponding to... Figure 1 The clock divider circuit in the circuit.

[0076] Digital demodulation module: Used to demodulate the input digital audio signal based on the second operating clock, outputting an audio data stream and a reference clock signal, corresponding to... Figure 1 The digital audio processing circuit in the device.

[0077] DAC module: This refers to the DAC module, which integrates the following components:

[0078] Phase detection unit: used to detect the instantaneous phase difference between the first working clock and the reference clock signal, and generate a digital phase error signal.

[0079] Loop filtering unit: Used to filter the digital phase error signal to obtain the phase control word. Phase interpolation unit: Used to adjust the phase of the first operating clock according to the phase control word to generate the sampling clock.

[0080] Sample and hold unit: Used to sample the audio data stream under the control of the sampling clock.

[0081] The detailed implementation methods of each functional module are the same as the corresponding steps in the method embodiment, and will not be repeated here. This device embodiment implements the above method through hardware circuits or a combination of hardware and software, and can be integrated into audio devices to solve the clock path delay mismatch problem in a low-cost and low-power manner.

[0082] The embodiments described above are merely illustrative of the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention. It should be noted that the information interaction, execution process, etc., between the above-mentioned devices / units are based on the same concept as the method embodiments of this application, and their specific functions and technical effects can be found in the method embodiments section, and will not be repeated here.

[0083] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0084] This application also provides a computer device, such as... Figure 7 As shown, the computer device includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor. When the processor executes the computer program, it implements the steps in any of the above method embodiments, or when the processor executes the computer program, it implements the functions of each module / unit in the above device embodiments.

[0085] For example, the computer program may be divided into one or more modules / units, which are stored in the memory and executed by the processor to complete this application. The one or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in the computer device.

[0086] Those skilled in the art will understand that Figure 7 The computer device described is merely an example and does not constitute a limitation on the computer device. It may include more or fewer components than shown, or combine certain components, or different components. For example, the computer device may also include input / output devices, network access devices, buses, etc.

[0087] The aforementioned processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0088] The memory can be an internal storage unit of the computer device, such as a hard drive or RAM. The memory can also be an external storage device of the computer device, such as a plug-in hard drive, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. Furthermore, the memory can include both internal and external storage units of the computer device.

[0089] This application also provides a readable storage medium storing a computer program that, when executed by a processor, implements the steps described in the various method embodiments above.

[0090] This application provides a computer program product that, when run on an electronic device, enables the electronic device to perform the steps described in the various method embodiments above.

[0091] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a photographing device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0092] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0093] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0094] In the embodiments provided in this application, it should be understood that the disclosed apparatus / devices and methods can be implemented in other ways. For example, the apparatus / device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0095] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0096] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An audio device that optimizes latency differences based on a DAC module, characterized in that, include: The clock generation circuit is configured to generate a reference clock signal; The clock distribution circuit is configured to perform multi-level buffering processing on the reference clock signal to obtain a first working clock output to the DAC module, and to perform frequency division processing on the reference clock signal to obtain a second working clock output to the digital audio processing circuit. A digital audio processing circuit is configured to process a digital audio signal according to a second operating clock to output an audio data stream to the DAC module, and a reference clock signal synchronized with the audio data stream. The DAC module is configured as follows: The phase difference between the first working clock and the reference clock signal is detected, a phase error signal is generated, and the phase error signal is filtered to generate a phase adjustment value; The phase of the first working clock is adjusted according to the phase adjustment value to generate a sampling clock that is synchronized with the first working clock and whose phase can be offset. The audio data stream is sampled according to the sampling clock, so that the sampling time is within the data stability range represented by the reference clock signal, in order to compensate for the difference in signal propagation delay between the first working clock and the second working clock.

2. The audio device based on DAC module-optimized delay difference according to claim 1, characterized in that, The clock distribution circuit includes: The clock buffer circuit is configured to perform multi-level buffering on the reference clock signal, generate the first working clock, and output it to the DAC module. The clock divider circuit is configured to divide the reference clock signal to generate the second operating clock and output it to the digital audio processing circuit.

3. The audio device based on DAC module-optimized delay difference according to claim 2, characterized in that, The audio device based on DAC module-optimized delay difference also includes a microcontroller and a USB controller; the clock divider circuit is further configured as follows: The reference clock signal is mixed to generate a third working clock, which is then output to the microcontroller unit. The reference clock signal is divided twice to generate a fourth working clock, which is then output to the USB controller.

4. The audio device based on DAC module-optimized delay difference according to claim 1, characterized in that, The DAC module detects the phase difference between the first operating clock and the reference clock signal, and generates a phase error signal, specifically including: The first operating clock is input to a multi-phase delay chain to generate a set of delayed clock signals with different phase offsets. The total delay length of the multi-phase delay chain covers at least one complete cycle of the first operating clock. Using the reference clock signal as the sampling clock, the tap state of the multi-phase delay chain is latched in parallel. The latched tap state is encoded and converted to generate a digital phase error signal.

5. The audio device based on DAC module-optimized delay difference according to claim 1, characterized in that, The DAC module adjusts the phase of the first operating clock according to the phase adjustment value to generate a sampling clock, specifically including: The first operating clock is input to the phase interpolator; The phase interpolator interpolates the sampling clock with a corresponding phase offset between adjacent clock edges of the first working clock according to the phase adjustment value, wherein the phase adjustment step of the sampling clock is smaller than the period of the first working clock.

6. The audio device based on DAC module-optimized delay difference according to claim 1, characterized in that, The clock generation circuit is a three-overtone crystal oscillator circuit, including a first crystal, a first transistor, an inductor, a resistor, and a capacitor, used to generate a reference clock signal with a frequency of 84MHz.

7. The audio device based on DAC module-optimized delay difference according to claim 3, characterized in that, The clock divider circuit includes: A mixer is used to mix an 84MHz reference clock with a feedback 12MHz clock to generate a 96MHz clock. The first frequency divider is used to divide the 96MHz clock into a 48MHz clock by a second frequency division; The second and third frequency dividers are used to divide the 48MHz clock into 24MHz and 12MHz clocks in sequence, with the 12MHz clock serving as the second working clock. A buffer is used to buffer the 12MHz clock and use it as the third working clock. The fourth frequency divider is used to divide the 12MHz clock into a 6MHz clock as the fourth working clock.

8. A method for optimizing delay differences based on a DAC module, applied to an audio device for optimizing delay differences based on a DAC module, wherein the audio device for optimizing delay differences based on a DAC module includes a clock generation circuit, a clock distribution circuit, a digital audio processing circuit, and a DAC module, characterized in that, The method includes: A reference clock signal is generated by the clock generation circuit. The reference clock signal is buffered in multiple stages by the clock distribution circuit to obtain the first working clock output to the DAC module, and the reference clock signal is divided to obtain the second working clock output to the digital audio processing circuit. The digital audio processing circuit processes the digital audio signal according to the second operating clock to output an audio data stream to the DAC module, as well as a reference clock signal synchronized with the audio data stream. The DAC module detects the phase difference between the first operating clock and the reference clock signal, generates a phase error signal, and filters the phase error signal to generate a phase adjustment value. The DAC module adjusts the phase of the first working clock according to the phase adjustment value to generate a sampling clock that is synchronized with the first working clock and whose phase can be offset. The DAC module samples the audio data stream according to the sampling clock, ensuring that the sampling time is within the stable data range represented by the reference clock signal, thereby compensating for the difference in signal propagation delay between the first and second operating clocks.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method for optimizing latency differences based on the DAC module as described in claim 8.

10. A readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the method for optimizing latency differences based on the DAC module as described in claim 8.

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