Semiconductor structure and preparation method thereof, storage system and electronic equipment

Abstract

The invention provides a semiconductor structure and a preparation method thereof, a storage system and electronic equipment, and relates to the technical field of semiconductor chips. The semiconductor structure includes a memory array and a recess. The storage array comprises a bit line, a transistor and a capacitor unit which are arranged in a stacked mode, the transistor is located between the bit line and the capacitor unit, and the transistor is connected with the bit line and the capacitor unit. The groove penetrates through the memory array along the stacking direction, and the bit line is exposed out of the groove. The semiconductor structure is applied to the dynamic random access memory so as to realize data reading and writing operation.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and its fabrication method, a storage system, and an electronic device. Background Technology

[0002] With advancements in process technology, circuit design, and manufacturing processes, dynamic random access memory (DRAM) has been scaled down to smaller sizes. However, as the feature size of memory cells within the memory approaches its lower limit, planar processes and manufacturing technologies become challenging and costly, causing memory cell density to approach its upper limit.

[0003] Therefore, how to further miniaturize DRAM has become a technical problem that is currently difficult for engineers to solve. Summary of the Invention

[0004] Embodiments of this disclosure provide a semiconductor structure and its fabrication method, a storage system, and an electronic device.

[0005] The embodiments of this disclosure adopt the following technical solutions:

[0006] In one aspect, embodiments of this disclosure provide a semiconductor structure. The semiconductor structure includes a memory array and a recess. The memory array includes stacked bit lines, transistors, and capacitor cells, with the transistors located between the bit lines and the capacitor cells, and connected to both the bit lines and the capacitor cells. The recess extends through the memory array along the stacking direction, and the recess exposes the bit lines.

[0007] In some embodiments, the recess includes a first strip groove and a second strip groove. The first strip groove extends through the memory array along the stacking direction and is spaced apart from bit lines. The second strip groove communicates with the first strip groove and exposes at least a portion of the bit lines.

[0008] In some embodiments, the second strip extends through the bit line along the stacking direction.

[0009] In some embodiments, the number of grooves is multiple, at least one of the multiple grooves is located on one side of the storage array perpendicular to the stacking direction, and at least one of the multiple grooves is located on the other side of the storage array perpendicular to the stacking direction.

[0010] In some embodiments, the semiconductor structure further includes an insulating filler portion located within a groove.

[0011] In some embodiments, the number of transistors is multiple, and the multiple transistors are arranged in an array, wherein the gate lines of a column of transistors are connected to form a word line, and the word line is located on one side of the transistors along a first direction. One of two adjacent word lines is located on one side of a column of transistors along the first direction, and the other word line is located on the other side of a column of transistors along the first direction. The first direction is perpendicular to the stacking direction.

[0012] In some embodiments, the transistor includes a channel structure that is columnar and extends along the stacking direction, and the channel structure is connected to both bit lines and capacitor cells.

[0013] In some embodiments, the memory array further includes an isolation section. An isolation section is provided alternately with word lines within the interval between any two adjacent columns of transistors.

[0014] In some embodiments, the semiconductor structure further includes an interconnect layer. The interconnect layer is located on one side of the memory array in the stacking direction, and includes a first interconnect structure, a second interconnect structure, and a third interconnect structure. The first interconnect structure is connected to a bit line, a portion of the second interconnect structure extends into the memory array and is connected to a word line, and a portion of the third interconnect structure extends into the memory array and is connected to a capacitor cell. Alternatively, the first interconnect structure is connected to a capacitor cell, a portion of the second interconnect structure extends into the memory array and is connected to a bit line, and a portion of the third interconnect structure extends into the memory array and is connected to a word line.

[0015] In some embodiments, the semiconductor structure further includes peripheral devices. The peripheral devices are stacked on the side of the interconnect layer opposite to the memory array and are coupled to the memory array through the interconnect layer.

[0016] On the other hand, embodiments of this disclosure provide a method for fabricating a semiconductor structure, the method comprising: forming a memory array, the memory array including stacked bit lines, transistors, and capacitor cells, the transistors being located between the bit lines and the capacitor cells, and the transistors being connected to both the bit lines and the capacitor cells; forming a conductive structure along the stacking direction on one side of the memory array, the conductive structure penetrating the memory array and being connected to the bit lines, the conductive structure being configured to be grounded; forming an interconnect layer on the side of the bit lines away from the transistors, the interconnect layer having a first connection structure and a second connection structure disposed therein, the first connection structure or the second connection structure being connected to the bit lines; and removing the conductive structure to form a groove.

[0017] In some embodiments, before forming a conductive structure on one side of the memory array along the stacking direction, the fabrication method further includes forming a ground layer on the side of the capacitor cell away from the bit line. Forming a conductive structure on one side of the memory array along the stacking direction includes the conductive structure extending through the ground layer along the stacking direction.

[0018] In some embodiments, forming a conductive structure on one side of the memory array along the stacking direction includes: forming a first stripe groove that extends through the memory array along the stacking direction and is spaced apart from bit lines, the first stripe groove exposing a ground layer; forming a first sub-conductive structure within the first stripe groove; forming a second stripe groove that exposes at least a portion of the first conductive structure and at least a portion of the bit lines; and forming a second sub-conductive structure within the second stripe groove, the first sub-conductive structure and the second sub-conductive structure constituting a conductive structure.

[0019] In some embodiments, the fabrication method further includes removing the grounding layer before removing the conductive structure.

[0020] In another aspect, embodiments of this disclosure provide a storage system including: a semiconductor structure and a controller as described above. The controller is coupled to the semiconductor structure to control the semiconductor structure to store data.

[0021] In another aspect, embodiments of this disclosure provide an electronic device, including a motherboard and a storage system as described above disposed on the motherboard. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0023] Figure 1 This is a structural block diagram of an electronic device provided in some embodiments of the present disclosure;

[0024] Figure 2 A structural block diagram of a memory provided in some embodiments of this disclosure;

[0025] Figure 3 This is a flowchart illustrating a method for fabricating a semiconductor structure according to some embodiments of the present disclosure;

[0026] Figure 4 This is a schematic diagram of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure;

[0027] Figure 5 To and Figure 4 A schematic diagram of a semiconductor structure corresponding to the preparation method described in the figure;

[0028] Figure 6 To and Figure 4A schematic diagram of another semiconductor structure corresponding to the preparation method described in the figure;

[0029] Figure 7 To and Figure 4 A schematic diagram of another semiconductor structure corresponding to the preparation method described above;

[0030] Figure 8 To and Figure 4 A schematic diagram of another semiconductor structure corresponding to the preparation method described above;

[0031] Figure 9 To and Figure 4 A schematic diagram of another semiconductor structure corresponding to the preparation method described above;

[0032] Figure 10 To and Figure 4 A schematic diagram of another semiconductor structure corresponding to the preparation method described above;

[0033] Figure 11 To and Figure 4 A schematic diagram of another semiconductor structure corresponding to the preparation method described above;

[0034] Figure 12 To and Figure 4 A schematic diagram of another semiconductor structure corresponding to the preparation method described above;

[0035] Figure 13 A flowchart illustrating a method for preparing a conductive structure according to some embodiments of this disclosure;

[0036] Figure 14 To and Figure 13 A schematic diagram of the film layer of a storage array corresponding to the preparation method described in the figure;

[0037] Figure 15 To and Figure 13 A schematic diagram of the film layer of another storage array corresponding to the preparation method described in the figure;

[0038] Figure 16 This is a schematic diagram of a semiconductor structure provided in some embodiments of the present disclosure;

[0039] Figure 17 This is a schematic diagram of another semiconductor structure provided in some embodiments of the present disclosure;

[0040] Figure 18 A schematic diagram of the film layers of a storage array provided for some embodiments of this disclosure;

[0041] Figure 19 This is a schematic diagram of another semiconductor structure provided in some embodiments of the present disclosure. Detailed Implementation

[0042] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0043] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0044] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0045] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0046] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0047] Figure 1 This is a structural block diagram of an electronic device 9000 provided for some embodiments of this disclosure. The electronic device 9000 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device (e.g., smartwatch, smart bracelet, smart glasses, etc.), smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0048] like Figure 1 As shown, the electronic device 9000 may include a storage system 910 and a host 920. The storage system 910 can be integrated into various types of storage devices, such as memory cards. These memory cards include any of the following: PC cards (PCMCIA, Personal Computer Memory Card International Association), compact flash (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), secure digital memory cards (SD cards), and universal flash storage (UFS). In other words, the storage system 910 can be applied to and packaged into different types of electronic products.

[0049] The host 920 may include a processor of the electronic device 9000, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 920 may be configured to send data to or receive data from memory.

[0050] In some embodiments, the storage system 910 may have one or more memories 911 and a controller 912. For example, the controller 912 may be configured to operate in a low duty cycle environment, such as with an SD card, CF card, universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. Alternatively, in other examples, the controller 912 is configured to operate in a high duty cycle environment with an SSD or eMMC, which is used as data storage in mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays. Or, in some examples, the controller 912 is coupled to the memory 911 and the host 920 and is configured to control data in the memory 911 while also being able to communicate with external devices (e.g., the host).

[0051] The number of memories 911 in the storage system 910 can be one or more. Figure 1The diagram illustrates three memories 911 as an example. Controller 912 manages the data stored in each memory 911 and communicates with host 920. Controller 912 can be configured to control the operation of each memory 911, such as read, write, and refresh operations. Controller 912 can also be configured to manage various functions related to data stored or to be stored in each memory 911, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some embodiments, controller 912 is also configured to determine the maximum memory capacity usable by the computer system, the number of memory banks, memory type and speed, memory particle data depth and data width, and other important parameters. Controller 912 may also perform any other suitable functions. Controller 912 can communicate with external devices (e.g., host 920) according to specific communication protocols. For example, the controller 912 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0052] Figure 2 This is a structural block diagram of a memory 911 provided in some embodiments of this disclosure. For example... Figure 2 As shown, memory 911 includes memory cell array 913 and peripheral circuitry 914 for controlling memory cell array 913. Peripheral circuitry 914 may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of memory cell array 913. For example, peripheral circuitry 914 may include page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuits), or one or more of any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0053] For example, the peripheral circuit 914 can use complementary metal-oxide-semiconductor (CMOS) technology, which can be implemented using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0054] The memory cell array 913 and the peripheral circuitry 914 can be arranged side-by-side in the same plane, for example, on the same wafer; that is, the memory cell array 913 and the peripheral circuitry 914 can be located in the same semiconductor structure. Alternatively, the memory cell array 913 and the peripheral circuitry 914 can be formed on different wafers and bonded together face-to-face. Figure 2 As shown, when the memory cell array 913 and the peripheral circuitry 914 are formed on different wafers and bonded together face-to-face, the memory 911 may include a first semiconductor structure 901 and a second semiconductor structure 902, as well as a bonding interface 903 between the first semiconductor structure 901 and the second semiconductor structure 902. The first semiconductor structure 901 may include the memory cell array 913, and the second semiconductor structure 902 may include the peripheral circuitry 914.

[0055] In some embodiments, the memory cell array 913 may be an array of memory cells that use vertical transistors as switching and selection devices. For example, the memory cell array 913 may be a dynamic random access memory cell array. For ease of description, a DRAM cell array may be used to describe an example of the memory cell array 913 in this disclosure. However, it should be understood that the memory cell array 913 is not limited to a DRAM cell array, and may include, for example, any other suitable type of memory cell array 913 that can use vertical transistors as switching and selection devices, such as a PCM cell array, a static random-access memory (SRAM) cell array, an FRAM cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, etc.

[0056] When the memory cell array 913 is a DRAM cell array, the memory cells therein are DRAM cells. A DRAM cell includes a capacitor for storing data bits as positive or negative charges, and one or more transistors for controlling (e.g., switching and selecting) access to the DRAM cell. In some embodiments, each DRAM cell is a 1T1C cell consisting of a transistor and a capacitor. According to some embodiments, the DRAM cell can be refreshed by peripheral circuitry 914 to retain data.

[0057] With the development of DRAM technology, the size of DRAM cell arrays has gradually decreased. For example, the size of DRAM cell arrays can be reduced from 8F. 2 Reduced to 6F 2 Along with this, the transistors in DRAM cells have undergone various structural transformations, including planar array transistors, recessed channel array transistors, and buried saddle-fin access transistors. To further reduce the size of the DRAM cell array to 4F... 2 Most related technologies use vertical transistors as the transistors in DRAM cells. However, when fabricating DRAM cells with vertical transistors using the commonly used methods in these technologies, some processes may damage the structure of the transistors and other devices, leading to problems such as increased transistor leakage current and reduced data retention time in the DRAM cells.

[0058] Based on this, the present disclosure provides a method for fabricating a semiconductor structure 100.

[0059] Figure 3 This is a flowchart illustrating a method for fabricating a semiconductor structure 100 according to some embodiments of the present disclosure.

[0060] like Figure 3 As shown, the method for fabricating the semiconductor structure 100 includes the following steps S1 to S4.

[0061] S1. A memory array is formed, which includes stacked bit lines, transistors and capacitor cells. The transistors are located between the bit lines and capacitor cells, and the transistors are connected to both the bit lines and capacitor cells.

[0062] In step S1, the memory array 110 can be formed on a substrate. The substrate can be a single-crystal silicon (Si) substrate, a single-crystal germanium (Ge) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc. The substrate material can also be a compound semiconductor. For example, the substrate can be a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, or a silicon carbide (SiC) substrate, etc. Alternatively, the substrate can be made of other semiconductor materials commonly used in the art; this disclosure does not limit the scope of the embodiments.

[0063] In step S1, the formation process of the memory array 110 may include the following steps S11-S15, wherein, in this embodiment, the substrate material includes single-crystal silicon as an example for description.

[0064] Figure 4 This is a schematic diagram of the structure corresponding to a method for fabricating a semiconductor structure 100 provided in some embodiments of this disclosure. Figure 5 To and Figure 4 A schematic diagram of a semiconductor structure 100 corresponding to the preparation method described in the figure. Figure 6 To and Figure 4 A schematic diagram of another semiconductor structure 100 corresponding to the preparation method described in the figure. Figure 7 To and Figure 4 The schematic diagram of another semiconductor structure 100 corresponding to the preparation method in the figure.

[0065] S11. A photoresist layer is formed on one side surface of the substrate, and the photoresist layer is patterned to obtain a first mask layer with multiple first openings.

[0066] In this step S11, the photoresist can be applied using a suitable method such as static spin coating or dynamic spray coating.

[0067] like Figure 4 As shown, the substrate is etched based on the first mask layer to form multiple silicon strips 210. Exemplarily, in this embodiment, a self-aligned double patterning (SADP) process can be used to etch the substrate to form multiple grooves, and silicon strips 210 are formed between adjacent grooves. The height of the silicon strips 210 in the stacking direction Z is lower than the height of the substrate in the stacking direction Z.

[0068] Each silicon strip 210 may extend along a first direction X, and multiple silicon strips 210 may be arranged at intervals along a second direction Y. In some examples, the multiple silicon strips 210 arranged at intervals along the second direction Y may be staggered to facilitate the extraction of device structures fabricated on the silicon strips 210 in subsequent fabrication processes (e.g., bonding processes).

[0069] An insulating material is deposited in a groove between two adjacent silicon strips 210 using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, to achieve isolation between the two adjacent silicon strips 210 and to provide a basis for the fabrication of subsequent structures. The insulating material may include one or more of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride), and oxynitride materials (e.g., silicon oxynitride).

[0070] S12. A photoresist layer is formed on one side surface of the plurality of silicon strips 210, and the photoresist layer is patterned to obtain a second mask layer with a plurality of second openings.

[0071] In step S12, the photoresist can be applied using a suitable method such as static spin coating or dynamic spray coating.

[0072] like Figure 5 As shown, the silicon strip 210 is etched based on the second mask layer to form multiple strip grooves 220. Exemplarily, in this embodiment, a self-aligned reverse patterning (SARP) process can be used to etch the silicon strip 210 to form multiple strip grooves 220, and the side of each silicon strip 210 facing away from the substrate is divided into multiple silicon pillars 230 by the multiple strip grooves 220. The multiple silicon pillars 230 on a single silicon strip 210 can serve as the channel structure for a row of transistors subsequently fabricated.

[0073] Each strip groove 220 extends along the second direction Y, and multiple strip grooves are arranged at intervals along the first direction X. The depth of each strip groove 220 in the stacking direction Z is lower than the height of the silicon strip 210 in the stacking direction Z.

[0074] like Figure 5 and Figure 6 As shown, a first conductive material and a second conductive material are alternately deposited in multiple strip grooves 220 to form multiple conductive lines 240 and isolation portions 115 spaced apart between the multiple conductive lines 240. The portion of a conductive line 240 that contacts a single transistor in a row of transistors can serve as the gate of that transistor.

[0075] The first conductive material and the second conductive material can be different conductive materials. For example, both the first conductive material and the second conductive material can be one or more of tungsten, cobalt, copper, aluminum, and metal silicides, or other suitable materials can be used.

[0076] like Figure 7 As shown, in one feasible implementation, an epitaxial growth process can be used to grow a first conductive material within the strip groove 220. The resulting conductive line 240 can be tightly attached to the sidewalls and bottom wall of the strip groove 220, thereby making the cross-section of the conductive line 240 in the first direction X U-shaped. Alternatively, in another feasible implementation, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof can be used to deposit the first and second conductive materials. This disclosure does not limit the scope of the embodiments.

[0077] Furthermore, in one feasible implementation, before alternately depositing the first and second conductive materials within the plurality of grooves 220 in the aforementioned steps, an insulating material can be deposited in the plurality of grooves 220 using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof thin film deposition processes. This allows the subsequently formed plurality of conductive lines 240 and isolation portions 115 to be isolated from the silicon pillars 230. The insulating material deposited between the conductive lines 240 and the silicon pillars 230 can serve as the gate dielectric layer of the transistor during subsequent transistor formation.

[0078] S13. A photoresist layer is formed on one side surface of multiple silicon strips 210, and the photoresist layer is patterned to obtain a third mask layer with multiple third openings.

[0079] The third mask layer is used to etch multiple conductive lines 240 to disconnect the connection between two sidewalls that are opposite each other in the first direction X on the same conductive line 240 in the strip groove 220.

[0080] This design facilitates the subsequent fabrication of word lines, as the bottom wall of the conductive line 240 can be etched to divide one conductive line 240 into two separate word lines, thereby simplifying the fabrication process of the memory array 110 and reducing the fabrication difficulty of the memory array 110.

[0081] In addition, in some examples, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof thin film deposition processes can be used to fill the multiple strip grooves 220 with insulating material, thereby achieving isolation between two sidewalls disposed opposite to each other in the first direction X on the conductive lines 240 within the strip grooves 220.

[0082] For example, the insulating material may include one or more of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride), and oxynitride materials (e.g., silicon oxynitride).

[0083] Figure 8 To and Figure 4 A schematic diagram of another semiconductor structure 100 corresponding to the preparation method described in the figure. Figure 9 To and Figure 4 A schematic diagram of another semiconductor structure 100 corresponding to the preparation method described in the figure. Figure 10 To and Figure 4 A schematic diagram of another semiconductor structure 100 corresponding to the preparation method described in the figure. Figure 11 To and Figure 4 The schematic diagram of another semiconductor structure 100 corresponding to the preparation method in the figure.

[0084] in, Figure 8 , Figure 9 and Figure 10 For illustrative purposes only, and may not actually reflect the actual device structure (e.g., interconnects).

[0085] S14. A capacitor unit 113 is formed on the side of the silicon pillar 230 away from the silicon strip 210.

[0086] like Figure 8 As shown, the formed memory array 110 may also include capacitor units 113. For example, there may be multiple capacitor units 113, and one end of each capacitor unit 113 is connected to the end of the silicon pillar 230 away from the silicon strip 210.

[0087] With this configuration, the capacitor unit 113 can be used to store the charge as binary information stored by the corresponding DRAM unit.

[0088] S15. The conductive line 240 is split into word lines 116, and bit lines 111 are formed on the side of the silicon strip 210 away from the silicon pillar 230.

[0089] Alternatively, chemical mechanical polishing (CMP) can be used to polish the side of the substrate away from the silicon pillar 230 to remove excess substrate and expose multiple silicon strips 210.

[0090] Please continue reading. Figure 8In step S15, a wet etching process can be used to remove the insulating material between two adjacent silicon strips 210 to obtain a fourth opening. The conductive line 240 is then etched through the fourth opening between the two adjacent silicon strips 210 to remove the bottom wall of the conductive line 240 and split the conductive line 240 into two word lines 116.

[0091] Conductive material can be deposited on the side of silicon strip 210 away from silicon pillar 230 using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof thin film deposition processes to form bit line 111.

[0092] For example, the conductive material may include, but is not limited to, germanium-silicon, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. In this embodiment, the material of the middle line 111 may include germanium-silicon.

[0093] With this configuration, the storage array 110 can, under the control of the peripheral circuit, use word lines 116 to turn on and off the transistors in the storage cells, and combine with bit lines 111 to send data to the capacitor cells 113 in the storage cells, or read data from the capacitor cells 113 in the storage cells.

[0094] S2. A conductive structure is formed on one side of the memory array along the stacking direction. The conductive structure penetrates the memory array and is connected to the bit line. The conductive structure is configured to be grounded.

[0095] In the actual fabrication process, in step S15 above, after polishing the surface of the substrate away from the silicon pillar 230 using CMP technology, multiple silicon strips 210 are exposed and will be in an ungrounded state. In this state, when subsequent etching processes, plasma-enhanced chemical vapor deposition processes, or any other charged processes are performed, the charges generated during the process will be transferred to the silicon strips 210, and even to the bit lines 111 subsequently fabricated based on the silicon strips 210, thereby increasing the voltage on the bit lines 111 and potentially damaging the transistors connected to them. For example, the aforementioned charges can cause interface degradation of the silicon pillars of the transistor, thereby increasing the transistor leakage current and decreasing the drive current, which in turn shortens the data retention time of the capacitor cells 113 connected to the transistor, reducing the overall data retention time of the semiconductor structure 100; or, due to the increased voltage on the bit lines 111, the transistor may be broken down, causing the semiconductor structure 100 to malfunction.

[0096] Therefore, as Figure 9As shown, in this step S2, a grounded conductive structure 300 can be formed in the memory array 110. The conductive structure 300 is connected to the bit line 111, so that the charge in the bit line 111 and the channel structure of the transistor connected to the bit line 111 can be transferred to the ground potential through the conductive structure 300, thereby reducing the leakage current of the transistor 112, improving the data retention time of the memory cell, and improving the stability and reliability of the entire semiconductor structure 100.

[0097] S3. An interconnect layer is formed on the side of the bit line away from the transistor. A first connection structure and a second connection structure are provided in the interconnect layer. The first connection structure or the second connection structure is connected to the bit line.

[0098] like Figure 10 As shown, in this step S3, by forming an interconnect layer 140 on the side of bit line 111 away from transistor 112, the word line 116, bit line 111 and capacitor cell 113 in the memory array 110 can be brought out, so that the word line 116, bit line 111 and capacitor cell 113 can transmit signals between other device structures.

[0099] The interconnect layer 140 may include at least one circuit structure and multiple connection structures, such as a first connection structure 141, a second connection structure 142, and a third connection structure 143. By forming the first connection structure 141, the second connection structure 142, and the third connection structure 143, the accuracy of leading out word lines 116, bit lines 111, and capacitor cells 113 within the memory array 110 can be improved, thereby enhancing the stability and reliability of the semiconductor structure 100.

[0100] like Figure 11 As shown, in some other examples, the interconnect layer 140 may also be formed on the side of the transistor 112 away from the bit line 111, which is not a limitation of this embodiment.

[0101] Figure 12 To and Figure 4 The schematic diagram of another semiconductor structure 100 corresponding to the preparation method in the figure.

[0102] S4. Remove the conductive structure to form a groove.

[0103] like Figure 11 and Figure 12 As shown, in step S4, any etching process, such as wet etching, can be used to remove the conductive structure 300, thereby forming the groove 120.

[0104] This configuration avoids the conductive structure 300 from interfering with the normal operation of the memory array 110, such as interfering with the control of the bit line 111 on the transistor 112, thereby improving the stability and reliability of the memory array 110 and the semiconductor structure 100.

[0105] Please continue reading. Figure 9 In some embodiments, prior to step S2 above, the method for fabricating the semiconductor structure 100 further includes the following step S20:

[0106] S20. A ground layer 400 is formed on the side of capacitor unit 113 away from bit line 111.

[0107] For example, the ground layer 400 may include any suitable structure such as a silicon substrate (e.g., a carrier wafer).

[0108] As a feasible implementation, the ground layer 400 can be bonded to the side of the capacitor cell 113 away from the bit line 111 using a hybrid bonding process. This allows for the separate fabrication of the wafer containing the memory array 110 and the ground layer 400, thereby reducing the fabrication complexity of both and improving the fabrication efficiency of the semiconductor structure 100. Furthermore, the bonding process helps reduce the height of the semiconductor structure 100 in the Z-direction of the stacking axis, which also facilitates further miniaturization of the semiconductor structure 100.

[0109] In step S20, before bonding the ground layer 400, N or P ions can be implanted into the side 110 of the ground layer 400 near the storage array using an ion implantation process. This reduces the contact resistance at the contact point between the conductive structure 300 and the ground layer 400, thereby ensuring that the charge in the fabrication process can be smoothly introduced into the ground layer 400.

[0110] In one feasible implementation, the area to be implanted with ions can be located near the contact between the conductive structure 300 and the ground layer 400, and can cover part of the surface of the ground layer 400; or, it can cover the entire surface of the ground layer 400 near the memory array; or, a suitable ion implantation area can be designed according to actual needs, which is not limited in this embodiment.

[0111] Please continue reading. Figure 9 In some embodiments, step S2 above includes the following step S21:

[0112] S21, the conductive structure 300 extends along the stacking direction Z to the ground layer 400.

[0113] In this step S21, by connecting the conductive structure 300 to the ground layer 400, the charge generated in the fabrication process can be transferred to the ground layer 400 via the conductive structure 300. This avoids the accumulation of charge on the bit line 111, which could lead to an increase in the voltage of the bit line 111 or even damage to the transistor (e.g., breakdown), thereby improving the stability and reliability of the semiconductor structure 100.

[0114] Figure 13 This is a flowchart illustrating a method for preparing a conductive structure 300 according to some embodiments of the present disclosure. Figure 14 To and Figure 13 The preparation method described in the figure corresponds to a schematic diagram of the film layer (layout) of a storage array 110. Figure 15 To and Figure 13 The preparation method in the diagram is a schematic diagram of the film layer of a storage array 110.

[0115] like Figure 13 As shown, step S2 above also includes the following steps S201 to S204:

[0116] S201. A first strip is formed, which penetrates the memory array along the stacking direction, and the first strip is spaced apart from the bit lines, exposing the ground layer.

[0117] like Figure 14 As shown, photoresist is applied to the surface of the memory array 110 near the bit line 111 to form a photoresist pattern. Then, the photoresist pattern is used to form an etching pattern on the memory array 110, and the memory array 110 is etched through the etching pattern to obtain the first strip groove that runs through the memory array 110.

[0118] For example, photoresist can be applied using suitable methods such as static spin coating or dynamic spray coating. Alternatively, the memory array 110 can be etched using any suitable etching method such as dry etching or wet etching.

[0119] In one feasible implementation, a gap exists between the formed first stripe and the bit line 111, and the voltage of the bit line 111 is prevented from being affected by charge during the etching process of the first stripe. This arrangement ensures that the bit line 111 is not affected by the charge during the etching process, thereby improving the stability and reliability of the transistor 112 and the entire memory array 110.

[0120] S202, A first sub-conductive structure is formed in the first strip groove.

[0121] Please continue reading. Figure 14In step S202, conductive material can be deposited in the first strip groove using CVD, PVD, ALD, or any combination thereof to form the first sub-conductive structure 510. Exemplary conductive materials include, but are not limited to, W, Co, Cu, Al, doped silicon, silicides, or any combination thereof.

[0122] The first sub-conductive structure 510 is connected to the ground layer, so that the charge in the subsequent manufacturing process can be transferred to the ground layer through the first sub-conductive structure 510.

[0123] S203, Form a second strip groove, the second strip groove exposing at least a portion of the first conductive structure and at least a portion of the bit line.

[0124] like Figure 15 As shown, photoresist is applied to the surface of the memory array 110 near the bit line 111 to form a photoresist pattern. Then, the photoresist pattern is used to form an etching pattern on the memory array 110, and the memory array 110 is etched through the etching pattern to obtain a second strip groove that runs through the memory array 110.

[0125] For example, photoresist can be applied using suitable methods such as static spin coating or dynamic spray coating. Alternatively, the memory array 110 can be etched using any suitable etching method such as dry etching or wet etching.

[0126] In one feasible implementation, the formed second strip can expose the first sub-conductive structure 510 and the bit line 111, thereby enabling the subsequent fabrication of a second sub-conductive structure based on the second strip to achieve the connection between the first sub-conductive structure 510 and the bit line 111.

[0127] S204. A second sub-conductive structure is formed in the second strip groove, and the first sub-conductive structure and the second sub-conductive structure constitute a conductive structure.

[0128] Please continue reading. Figure 15 In step S204, conductive material can be deposited in the second strip groove using CVD, PVD, ALD, or any combination thereof to form the second sub-conductive structure 610. Exemplary conductive materials include, but are not limited to, W, Co, Cu, Al, doped silicon, silicides, or any combination thereof.

[0129] The second sub-conductive structure 610 can be connected to the ground layer via the first sub-conductive structure 510, thereby transferring the charge in the subsequent fabrication process to the ground layer, thus improving the stability and reliability of the transistor and the memory array.

[0130] In some embodiments, prior to step S4 above, the method for fabricating the semiconductor structure 100 further includes the following step S40:

[0131] S40, Remove grounding layer 400.

[0132] Please continue reading. Figure 9 and Figure 10 For example, in step S40, the ground layer 400 can be removed using processes such as CMP to expose the memory array 110, thereby providing fabrication space for subsequent interconnect layers 140 and other structures.

[0133] In addition to providing grounding potential, the grounding layer 400 can also serve as a support structure for the memory array 110 during the fabrication process. In this way, when the surface of the substrate facing away from the silicon pillar 230 is polished in the aforementioned step S15, it provides support for the memory array 110 and protects the surface of the memory array 110 near the capacitor cell 113.

[0134] Based on the semiconductor structure 100 fabrication methods provided in the above embodiments, this disclosure also provides a semiconductor structure 100, which can be fabricated by the above-described semiconductor structure 100 fabrication methods.

[0135] Figure 16 This is a schematic diagram of a semiconductor structure 100 provided in some embodiments of the present disclosure. Figure 17 This is a schematic diagram of another semiconductor structure 100 provided in some embodiments of the present disclosure. Figure 18 This is a schematic diagram of the film layers of a storage array 110 provided for some embodiments of this disclosure.

[0136] like Figure 16 and Figure 17 As shown, in some embodiments, the semiconductor structure 100 includes a memory array 110 and a recess 120. The memory array 110 includes stacked bit lines 111, transistors 112, and capacitor cells 113. The transistors 112 are located between the bit lines 111 and the capacitor cells 113, and are connected to both the bit lines 111 and the capacitor cells 113. The recess 120 extends through the memory array 110 along the stacking direction Z, and exposes the bit lines 111.

[0137] in, Figure 16 and Figure 17 For illustrative purposes only, and need not actually reflect the actual device structure (e.g., interconnection), in some examples, the stacking direction Z may represent the direction in which bit lines 111, transistors 112 and capacitor cells 113 are stacked sequentially in semiconductor structure 100.

[0138] Based on the aforementioned method for fabricating the semiconductor structure 100, in this embodiment, by providing a groove 120 that exposes the bit line 111, the intermediate structure (e.g., Figure 9 The conductive structure 300 shown is filled to ground the bit line 111 using the intermediate structure. In the process of fabricating the semiconductor structure 100, the intermediate structure in the groove 120 can conduct the charge in the charged process (e.g., etching process) to avoid the charge generated in the fabrication process from affecting the bit line 111 and the transistor 112 and other structures, thereby improving the stability and reliability of the semiconductor structure 100.

[0139] In some examples, the number of bit lines 111 exposed by the recess 120 can be multiple. With this configuration, multiple bit lines 111 can be uniformly exposed through one recess 120, thereby simplifying the semiconductor structure 100 and reducing the layout area occupied by the recess 120 on the semiconductor structure 100, which is beneficial for further miniaturization of the semiconductor structure 100.

[0140] Please continue reading. Figure 18 In some embodiments, the recess 120 includes a first strip groove 121 and a second strip groove 122. The first strip groove 121 extends through the memory array 110 along the stacking direction Z and is spaced apart from the bit line 111. The second strip groove 122 communicates with the first strip groove 121 and exposes at least a portion of the bit line 111.

[0141] Based on the aforementioned method for fabricating the semiconductor structure 100, in this embodiment, by setting the first strip groove 121 and the second strip groove 122, the groove 120 can be fabricated through different fabrication processes in the fabrication process of the semiconductor structure 100.

[0142] In the example, by setting the first strip groove 121, grounding can be achieved in the semiconductor structure 100 fabrication process by using the intermediate structure filled in the first strip groove 121. This allows the charge generated during the subsequent fabrication of the second strip groove 122 to be promptly conducted away, thereby preventing charge from being transferred to the bit line 111 or transistor 112 during the fabrication of the second strip groove 122, which could affect the stability of transistor 112.

[0143] Furthermore, by setting the second strip groove 122, the intermediate structure filled in the second strip groove 122 can be used to connect the bit line 111 with the intermediate structure filled in the first strip groove 121, thereby avoiding the impact of the charge generated in subsequent fabrication processes on the bit line 111 and the device structure such as the transistor 112, thereby improving the stability and reliability of the semiconductor structure 100.

[0144] In some examples, the number of second grooves 122 can be one or more. For example, when there are multiple second grooves 122, one second groove 122 can expose at least a portion of a bit line 111, thereby enabling the connection of multiple bit lines 111 to the intermediate structure filled in the first groove 121 via the intermediate structure filled in the multiple second grooves 122 during the fabrication process. This allows the grounding of multiple bit lines 111 to be achieved using the intermediate structure filled in the first groove 121, thereby simplifying the semiconductor structure 100 and reducing the layout area occupied by the grooves 120 on the semiconductor structure 100, which is beneficial for further miniaturization of the semiconductor structure 100.

[0145] Furthermore, as a feasible implementation, the shape of the first strip groove 121 and the shape of the second strip groove 122 can be any suitable shape such as a cube or cuboid, and this embodiment of the present disclosure does not limit this.

[0146] Please continue reading. Figure 18 In some embodiments, the second strip 122 extends through the bit line 111 along the stacking direction Z.

[0147] This configuration can improve the alignment accuracy between the second strip 122 and the bit line 111, and increase the yield of the intermediate structure filled in the second strip 122 that can contact the bit line 111, thereby increasing the rate of charge removal generated in the fabrication process and improving the stability and reliability of the semiconductor structure 100.

[0148] In some examples, the second strip groove 122 penetrates part of the bit line 111 along the stacking direction Z, or it can completely penetrate the bit line 111 along the stacking direction Z, thereby increasing the area of ​​the intermediate structure filled in the second strip groove 122 that can contact the bit line 111, and thus increasing the rate of charge extraction.

[0149] Furthermore, in the first direction X, the second strip groove 122 may contact one end of the bit line 111, or the second strip groove 122 may cover part of the bit line 111, thereby improving the alignment accuracy between the second strip groove 122 and the bit line 111, and improving the yield of the subsequent intermediate structure filled in the second strip groove 122 contacting the bit line 111.

[0150] In other examples, there may be other suitable relative positions between the second strip 122 and the bit line 111, which are not specifically limited in this embodiment.

[0151] Please continue reading. Figure 18 In some embodiments, there are multiple grooves 120, at least one of the multiple grooves 120 is located on one side of the storage array 110 perpendicular to the stacking direction Z, and at least one of the multiple grooves 120 is located on the other side of the storage array 110 perpendicular to the stacking direction Z.

[0152] In this embodiment, multiple grooves 120 can be respectively disposed on both sides of the memory array 110 along the first direction X, thereby exposing multiple bit lines 111 using multiple grooves 120. In the fabrication process of the semiconductor structure 100, the intermediate structure filled in the multiple grooves 120 can be used to achieve unified protection of multiple bit lines 111, thereby avoiding the impact of charges generated in the fabrication process on multiple bit lines 111 and structures such as transistors 112 connected to each bit line 111, and improving the reliability and stability of the semiconductor structure 100.

[0153] Furthermore, in the case where multiple grooves 120 are disposed on both sides of the memory array 110 along the first direction X, the grooves 120 on both sides can be alternately connected to multiple bit lines 111, so that two adjacent bit lines 111 are connected to different grooves 120 respectively.

[0154] This configuration increases the operational space for connecting bit line 111 and groove 120, which in turn increases the preparation space for preparing the second strip groove 122, thereby reducing the preparation difficulty and improving the yield of the connection between the prepared second strip groove 122 and bit line 111.

[0155] In addition, in some examples, the number of grooves 120 on each side of bit line 111 can be multiple, and the multiple grooves 120 can be distributed at intervals along the second direction Y, or distributed on one side of bit line 111 in other suitable layouts.

[0156] In other examples, the plurality of grooves 120 may also be disposed on both sides of the storage array 110 along the second direction Y, or disposed on both sides of the storage array 110 along other directions perpendicular to the stacking direction Z. This disclosure does not limit the scope of the present invention.

[0157] Figure 19 This is a schematic diagram of another semiconductor structure 100 provided in some embodiments of the present disclosure.

[0158] like Figure 19As shown, in some embodiments, the semiconductor structure 100 further includes an insulating filler portion 130, which is located within the groove 120.

[0159] For example, in this embodiment, an insulating filling portion 130 may be provided in the groove 120 to provide support for the semiconductor structure 100, thereby improving the overall stability and reliability of the semiconductor structure 100 in other fabrication processes.

[0160] As one possible implementation, the material of the insulating filler 130 may include an insulating material. For example, the insulating material may include one or more of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride), and oxynitride materials (e.g., silicon oxynitride).

[0161] Please continue reading. Figure 16 and Figure 19 In some embodiments, there are multiple transistors 112 arranged in an array. The gates 114 of one column of transistors 112 are connected to form a word line 116, and the word line 116 is located on one side of the transistors 112 along a first direction X. One of two adjacent word lines 116 is located on one side of the column of transistors 112 along the first direction X, and the other word line 116 is located on the other side of the column of transistors 112 along the first direction X. The first direction X is perpendicular to the stacking direction Z.

[0162] In this embodiment, by setting the word line 116 on the same side as the corresponding column of transistors 112, the fabrication process of the word line 116 can be simplified, and the selection of a column of transistors 112 can be achieved by controlling one word line 116, thereby cooperating with the bit line 111 to control the turn-on and turn-off of the transistors 112.

[0163] Furthermore, based on the fabrication process of the semiconductor structure 100, by respectively placing two adjacent word lines 116 on one side of a column of transistors 112 in the first direction X and on the other side of another column of transistors 112 adjacent to that column of transistors 112 in the first direction X, the two adjacent word lines 116 can be located between two adjacent columns of transistors 112. This allows the two adjacent word lines 116 to be fabricated in the same fabrication process, thereby simplifying the fabrication process of the semiconductor structure 100, improving the fabrication efficiency of the semiconductor structure 100, and reducing the fabrication cost of the semiconductor structure 100.

[0164] Please continue reading. Figure 16 and Figure 19In some embodiments, transistor 112 includes a channel structure 117, which is columnar and extends along the stacking direction Z. The channel structure 117 is connected to bit line 111 and capacitor cell 113.

[0165] In this embodiment, the two ends of the channel structure 117 in the stacking direction Z are connected to the bit line 111 and the capacitor unit 113 respectively, thereby forming a 1T1C DRAM cell in combination with the aforementioned word line 116. With the cooperation of the bit line 111 and the word line 116, the transistor 112 is used to control the charging and discharging of the capacitor unit 113, thereby realizing the DRAM cell's data reading, writing or erasing operations.

[0166] For example, the channel structure 117 can be in any suitable shape, such as cylindrical or prismatic, and this embodiment of the present disclosure does not limit this.

[0167] Furthermore, in one feasible implementation, the end of the row channel structure 117 near the bit line 111 can be connected as a common drain, thereby providing fabrication space for subsequent fabrication of the bit line 111 and improving the alignment accuracy between the bit line 111 and the channel structure 117 of the row transistor 112, thereby reducing the leakage current of the transistor 112 and extending the data retention time of the semiconductor structure 100.

[0168] Additionally, by way of example, the material of the channel structure 117 may include semiconductor materials, such as single-crystal silicon (Si), single-crystal germanium (Ge), etc., or the channel structure 117 may also be made of other semiconductor materials commonly used in the art, which is not limited in this embodiment.

[0169] Please continue reading. Figure 16 and Figure 19 In some embodiments, the memory array 110 further includes an isolation section 115. An isolation section 115 is alternately disposed within the interval between any two adjacent columns of transistors 112 and word lines 116.

[0170] In this embodiment, by providing an isolation portion 115 in the interval between two adjacent columns of transistors 112, isolation between the channel structures 117 of the two adjacent columns of transistors 112 can be achieved, thereby improving the stability and reliability of the transistors 112.

[0171] Please continue reading. Figure 11 and Figure 12In some embodiments, the semiconductor structure 100 further includes an interconnect layer 140. The interconnect layer 140 is located on one side of the memory array 110 in the stacking direction Z, and includes a first interconnect structure 141, a second interconnect structure 142, and a third interconnect structure 143. The first interconnect structure 141 is connected to the bit line 111, a portion of the second interconnect structure 142 extends into the memory array 110 and is connected to the word line 116, and a portion of the third interconnect structure 143 extends into the memory array 110 and is connected to the capacitor cell 113. Alternatively, the first interconnect structure 141 is connected to the capacitor cell 113, a portion of the second interconnect structure 142 extends into the memory array 110 and is connected to the bit line 111, and a portion of the third interconnect structure 143 extends into the memory array 110 and is connected to the word line 116.

[0172] In this embodiment, by setting the interconnect layer 140, the memory array 110 can be brought out, thereby enabling signal transmission between the word lines 116, bit lines 111, capacitor cells 113 and other device structures within the memory array 110, thus enabling other device structures to control the memory cells (e.g., DRAM cells) within the memory array 110. The connection can include electrical connections or physical connections.

[0173] The interconnect layer 140 can be used to bring out the memory array 110 via the first connection structure 141, the second connection structure 142 and the third connection structure 143, thereby improving the accuracy of bringing out the word line 116, bit line 111 and capacitor cell 113 in the memory array 110.

[0174] In some examples, the first connection structure 141, the second connection structure 142, and the third connection structure 143 may all include through silicon contact (TSC), through silicon contact, etc. Furthermore, by way of example, the shapes of the first connection structure 141, the second connection structure 142, and the third connection structure 143 may be the same or different. Additionally, when there are multiple first connection structures 141, multiple second connection structures 142, and multiple third connection structures 143, the shapes of the multiple first connection structures 141 may be the same or different. The shapes of the multiple second connection structures 142 may be the same or different. Similarly, the shapes of the multiple third connection structures 143 may be the same or different; this disclosure does not limit the embodiments in this regard.

[0175] Furthermore, as a feasible implementation, the interconnect layer 140 may also include at least one circuit structure to bring out multiple first connection structures 141, multiple second connection structures 142, and multiple third connection structures 143 through its internal circuit structure (e.g., interconnects). The circuit layer may also include an interlayer dielectric to achieve isolation between the circuit structures. Exemplarily, the interlayer dielectric may be made of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-dielectric-constant dielectrics, or any combination thereof.

[0176] The first connection structure 141, the second connection structure 142, and the third connection structure 143 may each include a conductive material. For example, the conductive material includes, but is not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The conductive materials used in the first connection structure 141, the second connection structure 142, and the third connection structure 143 may be the same or different, and this disclosure does not impose specific limitations on this.

[0177] Please continue reading. Figure 12 In some embodiments, the semiconductor structure 100 further includes peripheral devices 150. The peripheral devices 150 are stacked on the side of the interconnect layer 140 away from the memory array 110 and are coupled to the memory array 110 through the interconnect layer 140.

[0178] In this embodiment, the peripheral device 150 may include a plurality of control transistors T. The peripheral device 150 and the memory array 110 can be coupled through the interconnect layer 140, and the plurality of control transistors T in the peripheral device 150 can be coupled to the transistors 112 in the memory array 110, thereby realizing the transmission of electrical signals between the control transistors T and the transistors 112, and thus controlling the memory array 110 to write, read and erase data.

[0179] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A memory array comprising stacked bit lines, transistors, and capacitor cells, wherein the transistors are located between the bit lines and the capacitor cells, and are connected to both the bit lines and the capacitor cells; A groove extends through the memory array along the stacking direction and exposes the bit lines.

2. The semiconductor structure according to claim 1, characterized in that, The groove includes a first strip groove and a second strip groove. The first strip groove extends through the memory array along the stacking direction and is spaced apart from the bit lines. The second strip groove communicates with the first strip groove and exposes at least a portion of the bit lines.

3. The semiconductor structure according to claim 2, characterized in that, The second strip extends through the bit line along the stacking direction.

4. The semiconductor structure according to claim 1, characterized in that, The number of grooves is multiple, at least one of the multiple grooves is located on one side of the storage array perpendicular to the stacking direction, and at least one of the multiple grooves is located on the other side of the storage array perpendicular to the stacking direction.

5. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: An insulating filling portion is located within the groove.

6. The semiconductor structure according to any one of claims 1-5, characterized in that, The transistors are multiple and arranged in an array, wherein the gate lines of a column of transistors are connected to form a word line, and the word line is located on one side of the transistors along a first direction; one of two adjacent word lines is located on one side of a column of transistors in the first direction, and the other word line is located on the other side of a column of transistors in the first direction; wherein the first direction is perpendicular to the stacking direction.

7. The semiconductor structure according to claim 6, characterized in that, The transistor includes a channel structure that is columnar and extends along the stacking direction, and the channel structure is connected to both the bit line and the capacitor cell.

8. The semiconductor structure according to claim 7, characterized in that, The storage array also includes: An isolation section is provided, in which there is a gap between any two adjacent columns of transistors, and the isolation section and the word line are alternately arranged in the gap.

9. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure also includes: An interconnect layer is located on one side of the storage array in the stacking direction, and the interconnect layer includes a first connection structure, a second connection structure, and a third connection structure; The first connection structure is connected to the bit line, a portion of the second connection structure extends into the memory array and is connected to the word line, and a portion of the third connection structure extends into the memory array and is connected to the capacitor cell; or, The first connection structure is connected to the capacitor unit, a portion of the second connection structure extends into the memory array and is connected to the bit line, and a portion of the third connection structure extends into the memory array and is connected to the word line.

10. The semiconductor structure according to claim 9, characterized in that, The semiconductor structure also includes: Peripheral devices are stacked on the side of the interconnect layer away from the memory array and coupled to the memory array through the interconnect layer.

11. A method for fabricating a semiconductor structure, characterized in that, include: A memory array is formed, the memory array including stacked bit lines, transistors and capacitor cells, the transistors being located between the bit lines and the capacitor cells, and the transistors being connected to both the bit lines and the capacitor cells; A conductive structure is formed on one side of the memory array along the stacking direction, the conductive structure penetrates the memory array, and the conductive structure is connected to the bit line. The conductive structure is configured to be grounded. An interconnect layer is formed on the side of the bit line away from the transistor. A first connection structure and a second connection structure are disposed in the interconnect layer. The first connection structure or the second connection structure is connected to the bit line. Remove the conductive structure to form a groove.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, Before forming a conductive structure on one side of the memory array along the stacking direction, the fabrication method further includes: A ground layer is formed on the side of the capacitor unit away from the bit line; The formation of a conductive structure on one side of the storage array along the stacking direction includes: the conductive structure extending through the ground layer along the stacking direction.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, The formation of a conductive structure on one side of the memory array along the stacking direction includes: A first strip is formed, the first strip extends through the memory array along the stacking direction, and the first strip is spaced apart from the bit lines, the first strip exposing the ground layer; A first sub-conductive structure is formed within the first strip groove; A second strip is formed, the second strip exposing at least a portion of the first conductive structure and at least a portion of the bit line; A second sub-conductive structure is formed within the second strip groove, and the first sub-conductive structure and the second sub-conductive structure constitute the conductive structure.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, Prior to removing the conductive structure, the preparation method further includes: Remove the grounding layer.

15. A storage system, characterized in that, include: The semiconductor structure as described in any one of claims 1-10; A controller is coupled to the semiconductor structure to control the semiconductor structure to store data.

16. An electronic device, characterized in that, Includes a motherboard and a storage system as described in claim 15 disposed on the motherboard.

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