Semiconductor memory and preparation method thereof

Abstract

The invention discloses a semiconductor memory and a preparation method, which can improve the factory yield of the semiconductor memory and prolong the service life of the semiconductor memory. The semiconductor memory includes: a substrate; the bit lines are arranged on the substrate in parallel; the virtual bit lines are parallel to the length direction of the bit lines, arranged on the substrate and located on the periphery of the bit lines, the width of the virtual bit lines in the first direction is larger than that of the bit lines in the first direction, and the first direction is perpendicular to the length direction of the bit lines and parallel to the surface of the substrate; the plurality of contact windows are arranged at the two ends of the bit lines and the virtual bit lines in the length direction in a staggered mode, each bit line and each virtual bit line obtain external potential through one contact window or lead the potential of the bit line and the virtual bit line to the outside, and the distance between any two adjacent contact windows in the first direction is equal.

Description

[0001] This application is a divisional application. The original application has the application number 202210871901.2 and the original application date is July 22, 2022. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor memory, specifically to semiconductor memory and its fabrication method. Background Technology

[0003] In the manufacturing process of semiconductor memories, the fabrication of bit lines is frequently involved. In existing technologies, virtual bit lines are typically reserved in the edge regions of the bit lines. These virtual bit lines usually have the same electrical properties as the normal bit lines within the memory cell region.

[0004] However, in existing technologies, virtual bit lines often experience short circuits, which can damage semiconductor memory devices, affect the lifespan of semiconductor memory, and reduce factory yield. Summary of the Invention

[0005] In view of this, this application provides a semiconductor memory and a method for manufacturing it, which can improve the factory yield of the semiconductor memory and extend its service life.

[0006] This application provides a semiconductor memory, comprising: a substrate; multiple bit lines disposed parallel to each other on the substrate; multiple virtual bit lines disposed on the substrate parallel to the length direction of the bit lines, located around the bit lines, and the width of the virtual bit lines in a first direction is greater than the width of the bit lines in the first direction, the first direction being perpendicular to the length direction of the bit lines and parallel to the surface of the substrate; and multiple contact windows disposed alternately at both ends of the bit lines and the virtual bit lines in the length direction, wherein each bit line and the virtual bit line obtains an external potential through a contact window or leads its own potential to the outside, and any two adjacent contact windows in the first direction are equidistant.

[0007] Optionally, it may also include: a partition formed on the virtual bit line for severing the electrical connection at both ends in the length direction of the virtual bit line.

[0008] Optionally, the slot extends through the virtual bit line in a direction perpendicular to the substrate surface and also extends through the virtual bit line in the first direction.

[0009] Optionally, the width of the virtual bit line in the first direction is greater than or equal to the distance between any two adjacent contact windows in the first direction.

[0010] Optionally, the virtual bit line is provided with a contact window at each end of its length direction, and the slot is located between the two contact windows.

[0011] Optionally, a first spacer layer is formed on the sidewall surface of the partition groove and the sidewall surface of the bit line stack structure, and a second spacer layer is formed on the sidewall surface of the bit line, wherein the first spacer layer and the second spacer layer have different thicknesses.

[0012] Optionally, the first spacer layer and the second spacer layer may use different materials.

[0013] Optionally, the first spacer layer includes at least two of silicon oxide, silicon dioxide, and silicon nitride, and the second spacer layer includes at least two of silicon oxide, silicon dioxide, and silicon nitride.

[0014] Optionally, the contact window is filled with a layer of conductive metal material to draw out the potential of the internal structure of the bit line or virtual bit line.

[0015] This application also provides a method for fabricating a semiconductor memory, comprising the following steps: providing a substrate; forming a virtual bit line and multiple bit lines within the substrate, the virtual bit line and multiple bit lines being parallel to each other and sequentially disposed on the substrate; the width of the virtual bit line in a first direction being greater than the width of the bit line in the first direction, and the first direction being perpendicular to the length direction of the bit line; forming contact windows on the bit lines and the virtual bit lines, with two adjacent contact windows staggered at both ends of the bit lines and the virtual bit lines in the length direction, each bit line and the virtual bit line obtaining an external potential through one of the contact windows, or leading its own potential to the outside.

[0016] Optionally, a slot is formed on the virtual bit line to cut off the electrical connection between the two ends of the virtual bit line in the length direction.

[0017] Optionally, after forming the contact window, the method further includes the following step: filling the contact window with a conductive metal material to draw out the potential of the internal structure of the bit line or virtual bit line.

[0018] Optionally, before fabricating the virtual bit lines and bit lines, the slot is formed, and forming the slot includes: providing a bit line stack structure; forming a first patterned mask on the upper surface of the bit line stack structure, the first patterned mask exposing the expected formation area of ​​the slot; anisotropically etching the bit line stack structure based on the area exposed by the first patterned mask until the insulating layer beneath the bit line stack structure is exposed, thereby forming the slot on the bit line stack structure; forming the bit lines and the virtual bit lines includes: forming a second patterned mask on the surface of the bit line stack structure, the second patterned mask covering the expected formation area of ​​the bit lines and virtual bit lines, and exposing the expected spacing area between adjacent bit lines and / or virtual bit lines; anisotropically etching the expected spacing area to form a bit line trench within the bit line stack structure, the bit line trench exposing the surface of the insulating layer beneath the bit line stack structure.

[0019] Optionally, the method may further include the following steps: forming a first spacer layer on the sidewall and / or bottom surface of the slot and on the sidewall of the bit line stack structure, and / or: forming a second spacer layer on the sidewall of the bit line trench after the bit line and the virtual bit line are formed.

[0020] The semiconductor memory and fabrication method of this application are provided with multiple contact windows, and the contact windows are staggered at both ends of the bit lines and the virtual bit lines in the length direction. Each bit line and the virtual bit line obtains an external potential through one of the contact windows, or leads its own potential to the outside. This avoids the situation where the potential of a virtual bit line is given through two contact windows, and avoids short circuits caused by multiple potentials of the virtual bit line. This is beneficial to optimizing the device yield and device stability of the semiconductor memory.

[0021] Furthermore, by setting slots on the virtual bit lines, the occurrence of the virtual bit lines passing through two contact windows can be further avoided, the distance between adjacent contact windows can be reduced, thereby reducing the spacing between the bit lines and the size of the semiconductor memory. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic flowchart of the semiconductor memory fabrication method described in the embodiments of this application;

[0024] Figure 2 These are top and side views of the bitline stacking structure described in one embodiment of this application.

[0025] Figure 3 These are top and side views of the bitline stack structure with slots formed in one embodiment of this application.

[0026] Figure 4 These are a top view and a side view of the bitline stack structure with slots formed in one embodiment of this application after the first spacer layer has been formed.

[0027] Figure 5 This is a top view of the semiconductor device after bit lines and virtual bit lines are formed in one embodiment of this application.

[0028] Figure 6 This is a top view of the semiconductor memory after the spacer and contact window have been formed in one embodiment of this application.

[0029] Figure 7 This is a top view of the semiconductor memory after the contact window has been formed in one embodiment of this application.

[0030] Figure 8 This is a side view of the substrate after a bit line stack structure has been formed in one embodiment of this application.

[0031] Figure 9 Based on one embodiment of this application Figure 8 The diagram shows the structure of the device after it has formed bit lines and virtual bit lines. Detailed Implementation

[0032] The semiconductor memory and its fabrication method are further described below with reference to the accompanying drawings and embodiments.

[0033] This application provides a semiconductor memory in a first aspect.

[0034] Please see Figure 7 , Figure 8 ,in Figure 7 This is a top view schematic diagram of the semiconductor memory after the contact window has been formed in one embodiment of this application. Figure 8 This is a side view of the substrate after a bit line stack structure has been formed in one embodiment of this application.

[0035] The semiconductor memory includes: a substrate 100; multiple bit lines 103, arranged parallel to each other on the substrate 100; multiple virtual bit lines 104, parallel to the length direction of the bit lines 103, arranged on the substrate 100, located around the bit lines 103, and the width of the virtual bit lines 104 in a first direction is greater than the width of the bit lines 103 in the first direction, the first direction being perpendicular to the length direction of the bit lines 103 and parallel to the surface of the substrate 100; and multiple contact windows 107, staggered at both ends of the bit lines 103 and the virtual bit lines 104 in the length direction, each bit line 103 and virtual bit line 104 obtaining an external potential through a contact window 107, or leading its own potential to the outside, and any two adjacent contact windows 107 in the first direction are equidistant.

[0036] In some embodiments, the semiconductor memory is provided with a plurality of contact windows 107, and each contact window 107 is staggered at both ends of the bit line 103 and the virtual bit line 104 in the length direction. Each bit line 103 and the virtual bit line 104 obtains an external potential through one of the contact windows 107, or leads its own potential to the outside. This avoids the situation where the potential of a virtual bit line 104 is given through two contact windows 107, and avoids short circuits caused by multiple potentials of the virtual bit line 104. This is beneficial to optimizing the device yield and device stability of the semiconductor memory.

[0037] In some embodiments, the substrate 100 includes various substrates such as silicon substrate, germanium substrate, silicon-on-insulator, and germanium-on-insulator, and those skilled in the art can select the desired substrate 100 as needed.

[0038] In some embodiments, an active region SD and an insulating region 102 are formed inside the substrate 100. The active region SD is doped with P-type or N-type ions, distributed in a blocky pattern, and has multiple active regions SD, which are separated by the insulating regions 102. A gate electrode is also formed in the active region, and the gate electrode comprises at least a conductive metal material and extends into the active region SD.

[0039] The substrate 100 has a groove that exposes the interior of the active region SD for forming contact plugs 801 that contact the source and / or drain. The source and drain are formed based on the active region SD. A capping layer 805 is also disposed above the contact plugs 801.

[0040] Both the bit line 103 and the virtual bit line 104 are formed based on a complete bit line stack structure 200. The bit line stack structure 200 is located above the substrate 100 and includes a conductive layer 802, a hard mask layer 803, etc., stacked sequentially upwards in a direction perpendicular to the surface of the substrate 100. The conductive layer is electrically connected to the contact plug 801, and an insulating layer 804 is formed between the conductive layer and the gate to isolate the direct connection between the conductive layer and the insulating layer 804.

[0041] In some embodiments, the conductive layer comprises a conductive film layer made of common metallic conductive materials, or a stack of conductive film layers made of these common metallic conductive materials.

[0042] The hard mask layer 803 includes a film layer made of common hard mask materials such as nitrides and oxynitrides, or a stack of film layers made of these common hard mask materials.

[0043] In the specific fabrication process, a first spacer layer 103 is first used to separate the bit line stack structure 200 from other regions. Specifically, common methods such as anisotropic etching can be used to form trenches in a predetermined area. These trenches expose the edge sidewalls of the bit line stack structure 200. Then, based on these trenches, the first spacer layer 103 is formed on the sidewalls and / or bottom surface of the trenches, thereby separating the bit line stack structure 200 from other regions.

[0044] In some embodiments, a patterned mask structure is first formed above the bit line stack structure 200 to expose the areas to be etched, and then anisotropic etching is performed on these exposed areas to form the trenches.

[0045] In some embodiments, the semiconductor memory further includes a spacer 102 formed on the virtual bit line 104 for severing the electrical connections at both ends of the virtual bit line 104 along its length. By providing the spacer 102 on the virtual bit line 104, the occurrence of the virtual bit line 104 passing through two contact windows 107 can be further avoided, the distance between adjacent contact windows 107 can be reduced, thereby reducing the spacing between the bit lines 103 and reducing the size of the semiconductor memory.

[0046] In some embodiments, the slot 102 is formed prior to the fabrication of the first spacer layer 103. Therefore, the first spacer layer 103 may also be formed onto the sidewall surface of the slot 102, dividing the area on the bitline stack structure 200 where the virtual bitline 104 is to be formed into two parts, see here. Figure 3 and Figure 4 ,in Figure 3The images show a top view (left) and a side view (right) of the bit line stack structure 200 with the partition groove 102 formed in one embodiment of this application. Figure 4 The images show a top view (left) and a side view (right) of the bitline stack structure 200 with the slot 102 formed in one embodiment of this application after the first spacer layer 103 has been formed.

[0047] In some embodiments, the slot 102 is formed at the top of the bit line stack structure 200 in a first direction and has at least a first width in the first direction, thereby enabling the cutting off of virtual bit lines 104 subsequently formed based on the bit line stack structure 200 thereon.

[0048] Please see Figure 3 As can be seen from the side view on the right, the groove 102 penetrates the bit line stacking structure 200, preventing the bottom of the groove 102 from retaining any adhesion of the bit line stacking structure 200. That is, the groove 102 can at least cut off the conductive layer 802 at the bottom of the bit line stacking structure 200.

[0049] The width of the partition 102 can be set according to actual needs. In some embodiments, in order to ensure that it has the technical effect of isolating the electrical connection between the two ends of the virtual bit line 104, the partition 102 has a width of at least 1 nm.

[0050] It is important to note that, Figure 4 In the middle, the side view on the right does not show the first spacer layer 103 around the bit line stack structure 200. It can be regarded as a cross-sectional view when the area between the opening and the bottom of the slot 102 is cut, i.e., CD view.

[0051] Please see Figure 5 This is a top view of the semiconductor device after bit line 103 and virtual bit line 104 are formed in one embodiment of this application.

[0052] In this embodiment, in order to arrange the bit lines 103 evenly along the first direction and in accordance with the arrangement of the transistors to be formed, the virtual bit line 104 is formed at the farthest end of the bit line stack structure 200 in the first direction, and the remaining areas are formed with evenly distributed bit lines 103.

[0053] When the slot 102 is not set, it is necessary to control the spacing of the bit lines 103, or the spacing of two adjacent contact windows 107 in the first direction, so as to configure one contact window 107 for each bit line 103 and virtual bit line 104.

[0054] exist Figure 5In the illustrated embodiment, the virtual bit line 104 is provided only at the farthest end of the bit line stack structure 200 in the first direction. In fact, the virtual bit line 104 can also be formed at the other end of the bit line stack structure 200. The virtual bit line 104 is formed at the farthest end of the bit line stack structure 200 in the direction opposite to the first direction, so as to meet the requirement that each bit line 103 in the middle region of the bit line stack structure 200 is evenly distributed following the arrangement of transistors.

[0055] When forming the bit line 103, the bit line 103 trench is first prepared by forming a further patterned mask above the hard mask layer 803 of the bit line stack structure 200 and etching the exposed area of ​​the patterned mask.

[0056] Specifically, common removal methods such as anisotropic etching can be used to remove the area exposed by the patterned mask to expose the insulating layer 804 on the surface of the substrate 100.

[0057] After the preparation of the bit line 103 trench is completed, a second spacer layer 105 is formed on the sidewall and / or bottom surface of the bit line 103 trench.

[0058] The first spacer layer 103 and the second spacer layer 105 can be films made of common spacer materials, or lateral stacked structures of films made of these common spacer materials. Here, "lateral" refers to the direction perpendicular to the sidewall of the trench of the bit line 103. Common spacer materials include, but are not limited to, silicon nitride, silicon oxide, and silicon oxynitride.

[0059] Since the first spacer layer 103 and the second spacer layer 105 are formed in different steps, the materials and thicknesses of the first spacer layer 103 and the second spacer layer 105 may be different. In practice, the materials and thicknesses of the first spacer layer 103 and the second spacer layer 105 can be set according to the actual situation.

[0060] exist Figure 6 , Figure 7 In the embodiment shown, the sidewalls of the bit line trench are also filled with another insulating material layer 106, thereby filling the bit line trench.

[0061] Please see Figure 6 This is a top view of the semiconductor memory after the partition 102 and contact window 107 have been formed in one embodiment of this application.

[0062] In this embodiment, each bit line 103 is provided with a contact window 107 to draw out the potential of the bit line 103 or to apply an electrical signal to the bit line 103. Each virtual bit line 104 is provided with at least one contact window 107 to expose the potential of the virtual bit line 104.

[0063] Furthermore, in Figure 6 In the embodiment shown, the virtual bit line 104 has two contact windows 107. The electrical connection between the exposed areas of the two contact windows 107 is cut off by the slot 102 to prevent the virtual bit line 104 from short-circuiting when the two contact windows 107 are simultaneously connected to an external electrical signal, which would lead to damage to the semiconductor memory.

[0064] In some embodiments, the partition 102 extends through the virtual bit line 104 in a direction perpendicular to the surface of the substrate 100 and also extends through the virtual bit line 104 in the first direction, thereby preventing the partition 102 from completely severing the electrical connection between the areas exposed by the contact windows 107 at both ends of the virtual bit line 104.

[0065] In some embodiments, the width of the virtual bit line 104 in the first direction is greater than or equal to the distance between any two adjacent contact windows 107 in the first direction. In this case, even if the virtual bit line 104 is exposed by two contact windows 107, it can still cut off the electrical connection between the areas exposed by the contact windows 107 at both ends of the virtual bit line 104 through the slot 102.

[0066] In some embodiments, the virtual bit line 104 is provided with a contact window 107 at each end of the length direction of the virtual bit line 104, and the slot 102 is located between the two contact windows 107.

[0067] In some embodiments, a first spacer layer 103 is formed on the sidewall surface of the partition groove 102 and the sidewall surface of the bit line stack structure 200, and a second spacer layer 105 is formed on the sidewall surface of the bit line 103, wherein the first spacer layer 103 and the second spacer layer 105 have different thicknesses.

[0068] Please see Figure 9 , for the basis Figure 8 The diagram shows the structure of the device after the bit lines and virtual bit lines are formed.

[0069] Because the first spacer layer 103 and the second spacer layer 105 are formed through different processes, they have different thicknesses and use different materials. In some other embodiments, the first spacer layer 103 and the second spacer layer 105 are made of the same material and have the same thickness. An insulating material layer 106 is also sandwiched between the sidewalls of the bit line trench, thereby filling the bit line trench and separating adjacent bit lines.

[0070] exist Figure 9 In the illustrated embodiment, the first spacer layer 103 includes at least two of a silicon oxide layer, a silicon dioxide layer, and a silicon nitride layer, and the second spacer layer 105 includes at least two of a silicon oxide layer, a silicon dioxide layer, and a silicon nitride layer.

[0071] In some embodiments, the contact window 107 is filled with a conductive metal material layer for drawing out the potential of the internal structure of the bit line 103 or the virtual bit line 104. The conductive metal material layer includes at least one of common conductive metal layers such as a tungsten layer, a copper layer, and a titanium nitride layer.

[0072] This application also provides a method for fabricating a semiconductor memory.

[0073] Please see Figure 1 , Figure 7 , Figure 8 , Figure 9 , wherein Figure 1 This is a schematic flowchart illustrating the steps of the semiconductor memory fabrication method described in the embodiments of this application.

[0074] In this embodiment, the fabrication method includes the following steps: Step S1: providing a substrate 100; Step S2: forming a virtual bit line 104 and multiple bit lines 103 within the substrate 100, the virtual bit line 104 and multiple bit lines 103 being parallel to each other and sequentially disposed on the substrate 100, and the width of the virtual bit line 104 in a first direction being greater than the width of the bit line 103 in the first direction, and the first direction being perpendicular to the length direction of the bit line 103; Step S3: forming contact windows 107 on the bit lines 103 and virtual bit lines 104, two adjacent contact windows 107 being staggered at both ends of the bit lines 103 and virtual bit lines 104 in the length direction, each bit line 103 and virtual bit line 104 obtaining an external potential through a contact window 107, or leading its own potential to the outside.

[0075] In some embodiments, the semiconductor memory is provided with a plurality of contact windows 107, and each contact window 107 is staggered at both ends of the bit line 103 and the virtual bit line 104 in the length direction. Each bit line 103 and the virtual bit line 104 obtains an external potential through one of the contact windows 107, or leads its own potential to the outside. This avoids the situation where the potential of a virtual bit line 104 is given through two contact windows 107, and avoids short circuits caused by multiple potentials of the virtual bit line 104. This is beneficial to optimizing the device yield and device stability of the semiconductor memory.

[0076] In some embodiments, a slot 102 is formed on the virtual bit line 104 to cut off the electrical connection between the two ends of the virtual bit line 104 in the length direction.

[0077] In some embodiments, after forming the contact window 107, the method further includes the step of filling the contact window 107 with a conductive metal material to draw out the potential of the internal structure of the bit line 103 or the virtual bit line 104.

[0078] In some embodiments, before fabricating the virtual bit lines 104 and bit lines 103, the slot 102 is formed, and forming the slot 102 includes: providing a bit line stack structure 200; forming a first patterned mask on the upper surface of the bit line stack structure 200, the first patterned mask exposing the expected formation area of ​​the slot 102; and anisotropically etching the bit line stack structure 200 based on the area exposed by the first patterned mask until the insulating layer 804 beneath the bit line stack structure 200 is exposed, thereby forming the slot 102 on the bit line stack structure 200.

[0079] The formation of the bit line 103 and the virtual bit line 104 includes the following steps: forming a second patterned mask on the surface of the bit line stack structure 200, the second patterned mask covering the expected formation areas of the bit line 103 and the virtual bit line 104, and exposing the expected spacing areas between adjacent bit lines 103 and / or virtual bit lines 104; performing anisotropic etching on the expected spacing areas to form a bit line 103 trench in the bit line stack structure 200, the bit line 103 trench exposing the surface of the insulating layer 804 below the bit line stack structure 200.

[0080] After forming the slot 102, the method further includes the following steps: forming a first spacer layer 103 on the sidewalls and / or bottom surface of the slot 102, and on the sidewalls of the bit line stack structure 200. After forming the bit line 103 and the virtual bit line 104, forming a second spacer layer 105 on the sidewalls of the slot of the bit line 103.

[0081] In some embodiments, since the first spacer layer 103 and the second spacer layer 105 are formed based on different steps, the materials used for the first spacer layer 103 and the second spacer layer 105 are different, and their thicknesses also have a certain difference.

[0082] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A semiconductor memory, characterized in that, include: Substrate; Multiple bit lines are disposed on the substrate; A virtual bit line is disposed on the substrate, located outside the bit line, and the width of the virtual bit line in a first direction is greater than the width of the bit line in the first direction, the first direction being perpendicular to the length direction of the bit line; Multiple contact windows are disposed on both sides of the long axis of the bit line; A first spacer layer is disposed on the sidewall of the bit line and the virtual bit line; At least one of the contact windows is disposed on the virtual bit line.

2. The semiconductor memory according to claim 1, characterized in that, Also includes: bit lines A stacked structure is located above the substrate; A slot is formed on the virtual bit line to cut off the electrical connection between the two ends of the virtual bit line along its length.

3. The semiconductor memory according to claim 2, characterized in that, The slot extends through the virtual bit line in a direction perpendicular to the substrate surface and also extends through the virtual bit line in the first direction.

4. The semiconductor memory according to claim 1, characterized in that, The width of the virtual bit line in the first direction is greater than or equal to the distance between any two adjacent contact windows in the first direction.

5. The semiconductor memory according to claim 2, characterized in that, The virtual bit line has a contact window at each end of its length direction, and the slot is located between the two contact windows.

6. The semiconductor memory according to claim 2, characterized in that, A first spacer layer is formed on the sidewall surface of the partition groove and the sidewall surface of the bit line stack structure, and a second spacer layer is formed on the sidewall surface of the bit line, wherein the first spacer layer and the second spacer layer have different thicknesses.

7. The semiconductor memory according to claim 6, characterized in that, The first spacer layer and the second spacer layer use different materials.

8. The semiconductor memory according to claim 6, characterized in that, The first spacer layer includes at least one of a silicon oxide layer and a silicon nitride layer, and the second spacer layer includes at least one of a silicon oxide layer and a silicon nitride layer.

9. The semiconductor memory according to claim 1, characterized in that, The contact window is filled with a layer of conductive metal material, which is used to draw out the potential of the internal structure of the bit line or virtual bit line.

10. A method for fabricating a semiconductor memory, characterized in that, Includes the following steps: Provide substrate; Virtual bit lines and multiple bit lines are formed on the substrate. The virtual bit lines are formed around the bit lines, and the width of the virtual bit lines in a first direction is greater than the width of the bit lines in the first direction. The first direction is perpendicular to the length direction of the bit lines. Multiple contact windows are formed on both sides of the long axis of the bit line, and at least one of the contact windows is disposed on the virtual bit line; A first spacer layer is formed on the sidewalls of the bit line and the virtual bit line.

11. The preparation method according to claim 10, characterized in that, A slot is formed on the virtual bit line to cut off the electrical connection between the two ends of the virtual bit line in the length direction.

12. The preparation method according to claim 11, characterized in that, Before fabricating the virtual bit line and the bit line, the slot is formed, and forming the slot includes: A bit line stack structure is provided; a first patterned mask is formed on the upper surface of the bit line stack structure, the first patterned mask exposing the expected formation area of ​​the slot; based on the area exposed by the first patterned mask, the bit line stack structure is anisotropically etched until the insulating layer under the bit line stack structure is exposed, thereby forming the slot on the bit line stack structure. Forming the bit line and the virtual bit line includes: A second patterned mask is formed on the surface of the bit line stack structure. The second patterned mask covers the expected formation areas of the bit lines and virtual bit lines, and exposes the expected spacing areas between adjacent bit lines and / or virtual bit lines. Anisotropic etching is performed on the expected spacing region to form bit line trenches within the bit line stack structure, the bit line trenches exposing the surface of the insulating layer beneath the bit line stack structure.

13. The preparation method according to claim 12, characterized in that, It also includes the following steps: A first spacer layer is formed on the sidewall and / or bottom surface of the slot, and on the sidewall of the bit line stack structure, and / or: After the bit lines and the virtual bit lines are formed, a second spacer layer is formed on the sidewall of the bit line trench.

14. The preparation method according to claim 10, characterized in that, After forming the contact window, the following steps are also included: The contact window is filled with a conductive metal material, thereby drawing out the potential of the internal structure of the bit line or virtual bit line.

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