Phase change memory

Abstract

The phase change memory comprises a substrate and a plurality of memory units, the memory units are arranged on the substrate in an array mode, each memory unit comprises a phase change memory layer and an electrode layer, the electrode layers are located on at least one side of the phase change memory layer in the first direction, and the first direction is perpendicular to the surface of the substrate. Wherein the electrode layer comprises a first sub-electrode layer and a second sub-electrode layer which are stacked in the first direction, the first sub-electrode layer is made of amorphous carbon, and the thermal conductivity of the second sub-electrode layer is smaller than that of the amorphous carbon. Therefore, compared with the mode that amorphous carbon is purely adopted as the electrode layer, the heat conductivity of the composite electrode layer adopted by the invention is reduced, so that diffusion of heat in the phase change storage layer to the electrode layer is reduced, heat or current density is focused to the phase change storage layer, heat diffusion loss can be reduced, heat efficiency can be improved, and RESET current is further reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a phase-change memory. Background Technology

[0002] Semiconductor memory is the foundation of information technology, with a global market worth hundreds of billions of dollars. As a candidate for the next generation of non-volatile semiconductor memory, phase-change random access memory (PCRAM) has attracted widespread attention due to its advantages such as high-speed read, high erasure and write cycles, non-volatility, small device size, low power consumption, and resistance to strong shocks and radiation.

[0003] Phase-change memory (PCM) is a semiconductor memory based on phase-change materials, which are materials that can electrically switch between amorphous and polycrystalline states. The basic principle of PCM is to use electrical pulse signals applied to the device cells to cause a reversible phase transition of the phase-change material between an amorphous and polycrystalline state. By distinguishing between the high resistance in the amorphous state and the low resistance in the polycrystalline state, the operations of writing, erasing, and reading information are achieved.

[0004] Since phase change materials (PCMs) undergo unit operations through melting / crystallization (Joule heating), the heat from the PCM tends to diffuse along the current direction. Therefore, a higher operating current is required to compensate for heat loss (increasing power consumption by 30%) in order for the PCM to reach its melting temperature. The current reset current of existing 3D PCMs (>120μA) results in high power consumption (>10 pJ / bit), which limits high-density integration. Summary of the Invention

[0005] This application provides a phase-change memory to reduce heat diffusion loss, improve thermal efficiency, and thus reduce RESET current.

[0006] This application provides a phase change memory, including: a substrate; a plurality of memory cells arrayed on the substrate, each memory cell including a phase change storage layer and an electrode layer, the electrode layer being located on at least one side of the phase change storage layer along a first direction, the first direction being perpendicular to the surface of the substrate; wherein, the electrode layer includes a first sub-electrode layer and a second sub-electrode layer stacked along the first direction, the material of the first sub-electrode layer including amorphous carbon, and the thermal conductivity of the second sub-electrode layer being less than the thermal conductivity of the amorphous carbon.

[0007] In some embodiments, the thermal conductivity of the second sub-electrode layer is less than or equal to 5 W / m·K, and the thermal conductivity of the amorphous carbon is 1 W / m·K to 10 W / m·K.

[0008] In some embodiments, the material of the second sub-electrode layer includes carbon fiber, the second sub-electrode layer has a surface facing away from the substrate, and the axial angle of the carbon fiber relative to the surface is 55° to 65°.

[0009] In some embodiments, the material of the second sub-electrode layer further includes titanium carbide.

[0010] In some embodiments, the second sub-electrode layer includes a titanium carbide layer and a carbon fiber layer, wherein the titanium carbide layer is located between the carbon fiber layer and the phase change storage layer.

[0011] In some embodiments, the first sub-electrode layer has a volume fraction of 60% to 80% in the electrode layer, and the second sub-electrode layer has a volume fraction of 20% to 40% in the electrode layer.

[0012] In some embodiments, the thickness of the first sub-electrode layer is 10 nm to 15 nm, the thickness of the carbon fiber layer is 3 nm to 5 nm, and the thickness of the titanium carbide layer is 1 nm to 3 nm.

[0013] In some embodiments, the electrode layer is located on the side of the phase change storage layer away from the substrate, and the second sub-electrode layer is located between the phase change storage layer and the first sub-electrode layer.

[0014] In some embodiments, the phase change storage layer includes a first phase change layer, a thermal resistance intercalation layer, and a second phase change layer stacked along the first direction, wherein the thermal resistance intercalation layer is located between the first phase change layer and the second phase change layer; the melting temperature of the thermal resistance intercalation layer is greater than the melting temperature of the first phase change layer and greater than the melting temperature of the second phase change layer.

[0015] In some embodiments, the material of the thermal resistance intercalation layer includes amorphous carbon.

[0016] In the phase-change memory (PCM) of this application embodiment, the electrode layer located on at least one side of the PCM adopts a stacked structure of a first sub-electrode layer and a second sub-electrode layer. The material of the first sub-electrode layer includes amorphous carbon, and the thermal conductivity of the second sub-electrode layer is lower than that of amorphous carbon. Therefore, compared with simply using amorphous carbon as the electrode layer, the composite electrode layer used in this application has a lower thermal conductivity, thereby reducing the diffusion of heat from the PCM layer to the electrode layer and focusing heat or current density to the PCM layer. This reduces heat diffusion loss, improves thermal efficiency, and consequently reduces the RESET current.

[0017] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0019] Figure 1 This is a three-dimensional structural schematic diagram of a phase-change memory provided in some embodiments of this application; Figure 2 This is a schematic cross-sectional view of the phase-change memory along the YZ direction provided in some embodiments of this application; Figure 3 This is a schematic cross-sectional view of the phase-change memory along the XZ direction provided in some embodiments of this application; Figure 4 This is a cross-sectional structural schematic diagram of a phase change unit provided in some embodiments of this application; Figure 5 This is a cross-sectional structural schematic diagram of a phase change unit provided in some embodiments of this application; Figure 6 This is a cross-sectional structural schematic diagram of a phase change unit provided in some embodiments of this application; Figure 7 This is a cross-sectional structural schematic diagram of a phase change unit provided in some embodiments of this application; Figure 8 This is a cross-sectional structural schematic diagram of a phase change unit provided in some embodiments of this application; Figure 9 This is a cross-sectional structural schematic diagram of a phase change unit provided in one embodiment of this application; Figure 10 yes Figure 9 Schematic diagram of temperature distribution in the middle phase change unit; Figure 11 yes Figure 8 Schematic diagram of temperature distribution in the middle phase change unit; Figure 12 yes Figure 8 and Figure 9 A schematic diagram of the current pulse in the corresponding memory cell during the RESET operation. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0021] Please see Figure 1 , Figure 1 This is a three-dimensional structural schematic diagram of a phase-change memory provided in some embodiments of this application.

[0022] The phase-change memory includes a substrate, a plurality of memory cells 10, a first conductive line 20, and a second conductive line 30. The plurality of memory cells 10 are arrayed on the substrate along a second direction X and a third direction Y. The first conductive line 20 extends along the second direction X, and the second conductive line 30 extends along the third direction Y. The memory cells 10 are located between the first conductive line 20 and the second conductive line 30, and are located at the intersection of the first conductive line 20 and the second conductive line 30. One of the first conductive line 20 and the second conductive line 30 is a bit line, and the other is a word line. The second direction X and the third direction Y are both parallel to the surface of the substrate, and the second direction X and the third direction Y intersect in opposite directions. For example, the second direction X and the third direction Y are perpendicular to each other, but this application is not limited to this. In this embodiment, the first direction Z is used to represent the direction perpendicular to the surface of the substrate.

[0023] The storage unit 10 includes a phase change unit 11 and a gating unit 12, wherein the gating unit 12 is located between the substrate and the phase change unit 11. The phase change unit 11 includes a phase change storage layer (see the figure below for details).

[0024] Analysis of the heat generation process and heat conduction path reveals that for the operated memory cell 10, the heat is mainly generated by the phase change storage layer in the phase change unit 11. The heat conduction path can be divided into the following directions: 1) conduction along the vertical direction to the lower first conductive line 20 (e.g., bit line BL); 2) conduction along the vertical direction to the upper second conductive line 30 (e.g., word line WL); 3) conduction along the direction of the first conductive line 20 to the adjacent memory cell 10; 4) conduction along the direction of the second conductive line 30 to the adjacent memory cell 10. The memory also includes sidewalls (i.e., protective layers) located on the sidewalls of the memory cell 10 and heat insulation layers located on the surface of the sidewalls to reduce heat diffusion between adjacent memory cells.

[0025] Therefore, heat in the phase change storage layer tends to diffuse along the current direction (i.e., the vertical direction), requiring a higher operating current to compensate for heat loss in order for the phase change storage layer to reach its melting temperature. Thus, this application aims to address the issue of reducing heat diffusion along the vertical direction.

[0026] Based on this, this application provides a phase change memory, including: a substrate; a plurality of memory cells arranged in an array on the substrate, each memory cell including a phase change storage layer and an electrode layer, the electrode layer being located on at least one side of the phase change storage layer along a first direction, the first direction being perpendicular to the surface of the substrate; wherein, the electrode layer includes a first sub-electrode layer and a second sub-electrode layer stacked along the first direction, the material of the first sub-electrode layer including amorphous carbon, and the thermal conductivity of the second sub-electrode layer being less than the thermal conductivity of the amorphous carbon.

[0027] In the phase-change memory (PCM) of this application embodiment, the electrode layer located on at least one side of the PCM adopts a stacked structure of a first sub-electrode layer and a second sub-electrode layer. The material of the first sub-electrode layer includes amorphous carbon, and the thermal conductivity of the second sub-electrode layer is lower than that of amorphous carbon. Therefore, compared with simply using amorphous carbon as the electrode layer, the composite electrode layer used in this application has a lower thermal conductivity, thereby reducing the diffusion of heat from the PCM layer to the electrode layer and focusing heat or current density to the PCM layer. This reduces heat diffusion loss, improves thermal efficiency, and consequently reduces the RESET current.

[0028] The phase-change memory provided in the embodiments of this application will be described below with reference to the accompanying drawings.

[0029] Please see Figure 2 and Figure 3 , Figure 2 This is a schematic cross-sectional view of the phase-change memory along the YZ direction provided in some embodiments of this application. Figure 3 This is a schematic cross-sectional view of the phase-change memory along the XZ direction provided in some embodiments of this application. The three-dimensional structure of this phase-change memory can be referred to... Figure 1 .

[0030] The phase-change memory 100 includes a substrate 40 and a plurality of memory cells 10, which are arrayed on the substrate 40. Each memory cell 10 includes a phase-change storage layer 111 and an electrode layer 112. The electrode layer 112 is located on at least one side of the phase-change storage layer 111 along a first direction Z, which is perpendicular to the surface of the substrate 40. The electrode layer 112 includes a first sub-electrode layer 1121 and a second sub-electrode layer 1122 stacked along the first direction Z. The first sub-electrode layer 1121 is made of amorphous carbon, and the thermal conductivity of the second sub-electrode layer 1122 is less than that of the amorphous carbon.

[0031] The substrate 40 may include a substrate and a control circuit layer, wherein the control circuit layer may include a complementary metal-oxide-semiconductor (CMOS). The substrate may be a semiconductor substrate, such as silicon (Si), germanium (Ge), SiGe, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). In other embodiments, the substrate may also be a semiconductor substrate comprising other elements, or it may be a stacked structure, such as Si / SiGe.

[0032] The storage cell 10 includes a phase change storage layer 111 and an electrode layer 112. The electrode layer 112 can be located on the side of the phase change storage layer 111 away from the substrate 40, or on the side of the phase change storage layer 111 close to the substrate 40, or simultaneously on both sides of the phase change storage layer 111 along the first direction Z.

[0033] exist Figure 2 and Figure 3 In this embodiment, the electrode layer 112 is located on the side of the phase change storage layer 111 facing away from the substrate 40, that is, only the electrode layer 112 at the top of the phase change storage layer 111 is a composite layer of a first sub-electrode layer 1121 and a second sub-electrode layer 1122. This electrode layer 112 can be referred to as the first electrode layer 112, which includes a first sub-electrode layer 1121 and a second sub-electrode layer 1122 stacked along the first direction Z. The material of the first sub-electrode layer 1121 includes amorphous carbon, and the thermal conductivity of the second sub-electrode layer 1122 is less than that of the amorphous carbon.

[0034] exist Figure 2 and Figure 3 In this embodiment, the second sub-electrode layer 1122 is located between the phase change memory layer 111 and the first sub-electrode layer 1121, which can improve thermal isolation, focus heat, and enhance interface thermal resistance. The amorphous carbon is located on the upper layer of the second sub-electrode layer 1122, and the amorphous carbon can protect the second sub-electrode layer 1122 during the etching process of fabricating the phase change memory 100.

[0035] The memory cell 10 may further include a second electrode layer 113, a third electrode layer 121, and a gate layer 122. The gate layer 122 is located between the phase change memory layer 111 and the substrate 40. The phase change memory layer 111 is located between the first electrode layer 112 and the second electrode layer 113, and the gate layer 122 is located between the second electrode layer 113 and the third electrode layer 121. The first electrode layer 112, the phase change memory layer 111, and the second electrode layer 113 can form a phase change cell 11, and the gate layer 122 and the third electrode layer 121 can form a gate cell 12.

[0036] It is understood that when the electrode layer 112 (referred to as the first electrode layer 112) is located on the side of the phase change storage layer 111 close to the substrate 40, the second electrode layer 113 is located on the side of the phase change storage layer 111 away from the substrate 40, and the third electrode layer 121 is located between the gate layer 122 and the substrate 40; when the electrode layer 112 (referred to as the first electrode layer 112) is located on both sides of the phase change storage layer 111 along the first direction Z, the third electrode layer 121 is located between the gate layer 122 and the substrate 40.

[0037] The materials of the second electrode layer 113 and the third electrode layer 121 are different from the material of the first electrode layer 112. The second electrode layer 113 and the third electrode layer 121 can be made of a single material, such as amorphous carbon.

[0038] The material of the gate layer 122 may include a first chalcogenide compound, which may include at least one of AsSeGe, SeGe, AsSe, InAsSeGe, SiAsSeGe, InSiAsSeGe, Ge-Te, B-Te, Ge-Te-As, Ge-S, Ga-S, and Ge-As-S. The material of the phase change memory layer 111 may include a second chalcogenide compound, which is different from the material of the first chalcogenide compound. The second chalcogenide compound may include at least one of germanium tellurium (Ge-Te), antimony tellurium (Sb-Te), germanium antimony tellurium (Ge-Sb-Te), silicon antimony tellurium (Si-Sb-Te), titanium antimony tellurium (Ti-Sb-Te), aluminum antimony tellurium (Al-Sb-Te), germanium antimony selenium (Ge-Sb-Se), germanium gallium selenium (Ge-Sb-Ga), and germanium bismuth selenium (Ge-Sb-Bi).

[0039] The phase change memory 100 may also include a heat insulation layer 60 located between adjacent memory cells 10.

[0040] The phase-change memory 100 may further include a first protective layer 71 and a second protective layer 72, both of which are located on the sidewall of the memory cell 10, with the first protective layer 71 situated between the sidewall of the memory cell 10 and the second protective layer 72. An exemplary material for the first protective layer 71 is silicon oxide, and an exemplary material for the second protective layer 72 is silicon nitride.

[0041] Because As in the material of the gate layer 122 is more volatile, and the voltage drop of the gate layer 122 is greater than that of the phase change storage layer 111 during the operation of the storage cell 10, the gate layer 122 is more affected by the electric field. Therefore, the material of the gate layer 122 is more prone to diffusion than the material of the phase change storage layer 111. In this embodiment, only the electrode layer 112 at the top of the phase change storage layer 111 uses a composite layer of the first sub-electrode layer 1121 and the second sub-electrode layer 1122. This not only reduces thermal diffusion but also avoids the reduced adhesion between the gate layer 122 and the first protective layer 71 caused by the structural change of the second electrode layer 113, thereby preventing elemental diffusion of the gate layer 122 material.

[0042] In some embodiments, the material of the second sub-electrode layer 1122 includes carbon fiber. Carbon fiber is a slender fibrous material with carbon as its main component, primarily composed of highly oriented graphitized / graphite-like carbon crystals (i.e., stacked layers of carbon atoms, similar to graphite sheets). It should be noted that the second sub-electrode layer 1122 in this application may also be made of other materials with thermal conductivity lower than amorphous carbon.

[0043] By adjusting the tilt angle of carbon fibers, the longitudinal thermal conductivity of the carbon fibers can be controlled, making the thermal conductivity of carbon fibers lower than that of amorphous silicon. Furthermore, using carbon fibers allows for achieving both low thermal conductivity and high electrical conductivity.

[0044] In some embodiments, the second sub-electrode layer 1122 has a surface 1122T on the side opposite to the substrate 40, and the axial direction of the carbon fiber (i.e. the length direction of the carbon fiber / the direction along which the fiber extends) is tilted at an angle of 55° to 65° relative to the surface 1122T.

[0045] This embodiment uses carbon fibers with an inclination angle of 55°~65°, which can reduce the vertical thermal conductivity and improve the longitudinal thermal insulation. The inclined carbon fibers form an inclined columnar / ordered porous structure, which interrupts the effective longitudinal (vertical) heat channels and increases the porosity, resulting in a significant reduction in vertical heat conduction. This suppresses heat dissipation from the phase change storage layer to the first sub-electrode layer and enhances the heat concentration effect. Due to the reduced vertical heat loss, more input energy is retained in the region of the phase change storage layer 111 (i.e., the phase change region), which is conducive to the focusing of current / heat to the phase change region. Therefore, the thermal utilization rate is improved, which is conducive to the formation of the required temperature in the phase change region, thus reducing the RESET current and energy consumption.

[0046] In some embodiments, the thermal conductivity of the second sub-electrode layer 1122 is less than or equal to 5 W / m·K, and the thermal conductivity of the amorphous carbon is 1 W / m·K to 10 W / m·K, so as to further improve the longitudinal thermal insulation performance.

[0047] Studies have shown that controlling the tilt angle to 55°~65° can form a second sub-electrode layer 1122 with a thermal conductivity of less than or equal to 5 W / m·K. Although controlling the tilt angle within this range will sacrifice some of the conductivity of the carbon fiber, since the conductivity of carbon fiber itself is much higher than that of amorphous silicon (10 S / m~1000 S / m), it does not have a negative impact on the overall conductivity of the electrode layer 112, and may even improve the conductivity of the electrode layer 112.

[0048] It is understandable that the closer the inclination angle of carbon fiber is to 90°, the greater the longitudinal thermal conductivity; the less than 90° the inclination angle, the lower the longitudinal thermal conductivity. Controlling the inclination angle of carbon fiber to be greater than or equal to 55° is to minimize the loss of electrical conductivity.

[0049] In some embodiments, the material of the second sub-electrode layer 1122 further includes titanium carbide (TiC), that is, the material of the second sub-electrode layer 1122 includes carbon fibers and titanium carbide. TiC is a conductive ceramic with good electrical conductivity, which can compensate for the conductivity loss caused by the inclination angle of the carbon fibers, and further improve the conductivity of the second sub-electrode layer 1122.

[0050] Please see Figure 4 , Figure 4 This is a cross-sectional structural schematic diagram of a phase change unit provided in some embodiments of this application. This embodiment is related to... Figure 2 and Figure 3 The difference in this embodiment is that the phase change unit 11 further includes an adhesive layer 13.

[0051] The phase change storage layer 111 includes a first surface 111a and a second surface 111b opposite to each other along the first direction Z. An adhesive layer 13 is located on the first surface 111a and the second surface 111b to improve the adhesion of the phase change storage layer 111 to the upper and lower film layers. The adhesive layer 13 also has a certain barrier property to block the diffusion of elements in the phase change storage layer 111 material.

[0052] An exemplary material for the adhesive layer 13 is tungsten. It should be noted that the adhesive layer 13 may also be made of other suitable materials, and this application does not limit this.

[0053] Please see Figure 5 , Figure 5 This is a cross-sectional structural schematic diagram of a phase change unit provided in some embodiments of this application. This embodiment is related to... Figure 4 The difference in the embodiment lies in the structure of the second sub-electrode layer 1122.

[0054] The second sub-electrode layer 1122 includes a carbon fiber layer 1122a and a titanium carbide layer 1122b, with the titanium carbide layer 1122b located between the carbon fiber layer 1122a and the phase change storage layer 111. The titanium carbide layer 1122b and the carbon fiber layer 1122a are combined, resulting in a conductivity of 1000 S / m to 10000 S / m for the second sub-electrode layer 1122d, while also exhibiting high-temperature resistance up to 1400°C.

[0055] The titanium carbide layer 1122b can be prepared by processes such as chemical vapor deposition (CVD), chemical vapor infiltration (CVI), hot isostatic pressing (HIP), or reaction injection molding (RIM). The carbon fiber layer 1122a can be prepared by processes such as carbonization and graphitization.

[0056] Adding a titanium carbide layer 1122b to the second sub-electrode layer 1122 has the following advantages.

[0057] First, TiC can form a continuous conductive interface layer (titanium carbide layer 1122b) in thin film form. As a nano-thin layer located between the carbon fiber layer 1122a and the phase change storage layer 111, the titanium carbide layer 1122b can improve the actual contact area and contact quality between the carbon fiber layer 1122a and the phase change storage layer 111, significantly reduce the interfacial contact resistance, thereby ensuring that the current enters the phase change region more uniformly and facilitating current focusing and controllable heating.

[0058] Secondly, the titanium carbide layer 1122b also acts as a diffusion / chemical barrier, enhancing interface stability and reliability. TiC is a stable carbide with a high melting point and chemical inertness. During high-temperature pulse heating or long-term cycling, it can prevent the interdiffusion or chemical reaction between elements (Ge, Sb, Te) in the phase change storage layer 111 (such as GST) and the carbon fiber layer 1122a or the upper first sub-electrode layer 1121, inhibiting the formation of interface compounds or brittle phases, thereby improving the device's cycle life, data retention, and consistency.

[0059] The titanium carbide layer 1122b can also improve interfacial adhesion and mechanical stability. Because TiC has good interfacial affinity with carbon-based materials and many phase change alloys, the nanoscale titanium carbide layer 1122b can improve the wetting and adhesion between the carbon fiber layer 1122a and the phase change storage layer 111, reducing the risk of interfacial peeling or contact degradation during cycling, thereby improving the mechanical and electrical stability of the device.

[0060] Furthermore, the titanium carbide layer 1122b has minimal impact on overall thermal isolation while ensuring electrical contact (which is beneficial for heat focusing). Although TiC itself does not have extremely low thermal conductivity, when the titanium carbide layer 1122b is made into an ultra-thin nanoscale layer, its impact on the overall vertical thermal channel can be dominated by the interfacial thermal resistance (TBR) and the porosity of the carbon fibers. Therefore, the titanium carbide layer 1122b can achieve good electrical connection without significantly reducing the overall thermal resistance of the electrode layer 112, balancing thermal isolation and electrical conductivity requirements, which is beneficial for focusing heat on the phase change layer and reducing the reset current.

[0061] In some embodiments, the first sub-electrode layer 1121 has a volume fraction of 60% to 80% in the electrode layer 112, and the second sub-electrode layer 1122 has a volume fraction of 20% to 40% in the electrode layer 112. The limited range of the volume fractions of the first sub-electrode layer 1121 and the second sub-electrode layer 1122 has the following advantages.

[0062] 1. A balance is struck between conductivity and thermal insulation. The first sub-electrode layer 1121 accounts for a relatively large proportion (60%~80%), ensuring that the overall electrode layer 112 has sufficient conductivity and low series resistance, ensuring that current can be effectively injected and focused into the phase transition region; the second sub-electrode layer 1122 accounts for 20%~40%, providing the necessary thermal resistance to suppress heat dissipation to the first sub-electrode layer 1121 side. This proportion avoids "excessive insulation" leading to excessively high contact resistance, and also avoids "insufficient insulation" leading to heat loss.

[0063] 2. Improve thermal efficiency and reduce RESET current. An appropriate amount of low thermal conductivity second sub-electrode layer 1122 (20%~40%) forms an effective interfacial thermal resistance near the phase change storage layer 111, reducing heat diffusion to the first sub-electrode layer 1121 side, allowing more energy to be used for phase change, thereby reducing RESET current and power consumption.

[0064] 3. Maintain good interface electrical contact and reliability. A thicker / larger first sub-electrode layer 1121 can ensure good electrical contact and mechanical support with external circuits.

[0065] 4. Balancing process tolerance and manufacturability. This volume fraction range is easily achievable through common thin film deposition and thickness control (thickness ratios are easier to control stably during manufacturing), while avoiding overly stringent requirements on the process, thus promoting consistency in batch manufacturing.

[0066] In some examples, the thickness of the first sub-electrode layer 1121 is greater than the thickness of the second sub-electrode layer 1122, and the thickness of the first sub-electrode layer 1121 is 10nm~15nm, the thickness of the carbon fiber layer 1122a is 3nm~5nm, and the thickness of the titanium carbide layer 1122b is 1nm~3nm.

[0067] The thickness of the first sub-electrode layer 1121 is 10nm~15nm, which can ensure good electrical conductivity and current transmission. The relatively large thickness of the first sub-electrode layer 1121 can provide low surface resistance and good electrical contact and mechanical integrity, ensuring that the current can be smoothly transmitted and effectively focused at the interface of electrode layer 112 / phase change storage layer 111, without affecting heating efficiency or causing uneven heating due to excessively high electrode series impedance.

[0068] The carbon fiber layer 1122a has a thickness of 3nm to 5nm, which enables efficient thermal isolation and thermal focusing. Although the carbon fiber layer 1122a is relatively thin, it is sufficient to form an ordered porous / oriented fiber structure, thereby significantly reducing the effective thermal conductivity in the vertical direction, increasing interface scattering and improving the TBR (interface thermal resistance), confining heat to the phase transition region, reducing heat dissipation to the first sub-electrode layer 1121, improving thermal utilization, and helping to reduce RESET current and energy consumption.

[0069] The titanium carbide layer 1122b has a thickness of 1nm to 3nm, which can achieve interfacial electrical and chemical stability. As an interface conditioning layer, the nanoscale titanium carbide layer 1122b can significantly reduce contact resistance, improve wetting and adhesion, and act as a diffusion / chemical barrier under high-temperature pulses to inhibit the interdiffusion or chemical reaction between phase change components such as GST and the carbon substrate (i.e., carbon fiber layer 1122a), thereby improving device reliability and cycle stability.

[0070] The thickness of the first sub-electrode layer 1121 is greater than that of the second sub-electrode layer 1122, which enables thermal-electric synergistic optimization (the effect of layer thickness ratio). The configuration of a thicker first sub-electrode layer 1121 and a thinner second sub-electrode layer 1122 maximizes the thermal resistance effect without sacrificing conductivity, i.e., maintaining a good current path (avoiding high voltage drop or local overheating due to an excessively thin conductive layer), while achieving effective thermal isolation through a thin and functional low thermal conductivity layer, thereby achieving thermal / electrical division of labor optimization, balancing write speed, thermal quenching, and power consumption.

[0071] Please see Figure 6 , Figure 6 This is a cross-sectional structural schematic diagram of a phase change unit provided in some embodiments of this application. This embodiment is related to... Figure 5 The difference in the embodiments lies in the relative positions of the first sub-electrode layer 1121 and the second sub-electrode layer 1122.

[0072] Electrode layer 112 is located on the side of phase change storage layer 111 facing away from substrate 40. The first sub-electrode layer 1121 is located between phase change storage layer 111 and second sub-electrode layer 1122, that is, amorphous carbon is located below the second sub-electrode layer 1122. Specifically, amorphous carbon is located between titanium carbide layer 1122b and phase change storage layer 111.

[0073] In this embodiment, the amorphous carbon is closer to the phase change storage layer 111, which can play a good role in preventing diffusion.

[0074] Please see Figure 7 , Figure 7 This is a cross-sectional structural schematic diagram of a phase change unit provided in some embodiments of this application. This embodiment is related to... Figure 5 The difference in the embodiments lies in the position of the electrode layer 112 (referred to as the first electrode layer 112).

[0075] The first electrode layer 112 is located on both sides of the phase change storage layer 111 along the first direction Z, and the second sub-electrode layers 1122 are both located between the first sub-electrode layer 1121 and the phase change storage layer 111. Specifically, the titanium carbide layer 1122b is located between the carbon fiber layer 1122a and the adhesive layer 13.

[0076] This embodiment has the following advantages: 1) More uniform heat focusing and improved thermal efficiency: The double-sided electrode layer 112 can constrain and reflect heat from two directions, reduce heat loss on one side, make heating more concentrated in the phase transition region, improve heating efficiency, and reduce the required write energy; 2) Reduced RESET current and energy consumption: The double-sided / double-ended injection current or heat source can reduce the current density required on one side, thereby reducing RESET current and overall energy consumption; 3) More uniform electric field / current distribution: The two-sided electrode layer 112 provides symmetrical electrical contact, and the electric field and current distribution are more uniform, reducing local overheating or hot spots, and improving write consistency and inter-cell differences.

[0077] Please see Figure 8 , Figure 8 This is a cross-sectional structural schematic diagram of a phase change unit provided in some embodiments of this application.

[0078] The phase change storage layer 111 includes a first phase change layer 1111, a thermal resistance intercalation layer 1112, and a second phase change layer 1113 stacked along the first direction Z. The thermal resistance intercalation layer 1112 is located between the first phase change layer 1111 and the second phase change layer 1113. The melting temperature of the thermal resistance intercalation layer 1112 is higher than that of the first phase change layer 1111 and also higher than that of the second phase change layer 1113. The higher melting temperature of the thermal resistance intercalation layer 1112 ensures that it does not affect the melting temperature of the phase change storage layer 111.

[0079] exist Figure 8In previous embodiments, the temperature at the upper and lower interfaces of the phase change storage layer 111 was higher, while the temperature in the middle region was lower. In this embodiment, a thermal resistance intercalation layer 1112 (TBR) is inserted in the middle of the phase change storage layer 111. Its main mechanism is to increase the interfacial thermal resistance and reduce the vertical thermal conductivity, thereby confining more heat within the phase change active region and improving heat distribution and thermal efficiency. As a result, under the same electrical pulse, the temperature in the phase change region is higher / more concentrated, and the current and energy required for RESET are significantly reduced.

[0080] In some embodiments, the distance from the thermal resistance intercalation layer 1112 to the first surface 111a is equal to the distance from the thermal resistance intercalation layer 1112 to the second surface 111b, thereby enabling an increase in the temperature of the central region.

[0081] In some embodiments, the material of the thermal resistance intercalation layer 1112 includes amorphous carbon. Because amorphous carbon is stable and does not cause pollution, it can generate thermal resistance with the first phase change layer 1111 and the second phase change layer 1113 (chalcogenide compound), thereby improving heat distribution and increasing the intermediate temperature.

[0082] It should be noted that, in the embodiments of this application, other stable materials that can generate interfacial thermal resistance with the first phase change layer 1111 and the second phase change layer 1113 may also be used.

[0083] Please see Figure 9 and Figure 10 , Figure 9 This is a cross-sectional structural schematic diagram of a phase change unit provided in one embodiment of this application. Figure 10 yes Figure 9 A schematic diagram of the temperature distribution in the phase change unit. The difference between this embodiment and the previous embodiments is that the electrode is a single film layer made only of amorphous carbon, unlike the composite layer provided in the embodiments of this application.

[0084] See Figure 9 The phase change unit 11 includes a first electrode 11A, a second electrode 11B and a phase change storage layer 11C. The phase change storage layer 11C is located between the first electrode 11A and the second electrode 11B, and the materials of the first electrode 11A and the second electrode 11B are amorphous silicon.

[0085] Please see Figure 11 , Figure 11 yes Figure 8 Schematic diagram of temperature distribution in the middle phase change unit.

[0086] exist Figure 10 and Figure 11In the diagram, the horizontal axis represents the distance between each position and the top of the phase change unit 11, from the top to the bottom. For example, 0 represents the top of the phase change unit 11, and 750 Å represents a position 750 Å away from the top of the phase change unit 11. The vertical axis represents the temperature at the corresponding position, with the blue dashed line representing the melting temperature of the phase change storage layer 11C.

[0087] by Figure 8 For example, the top of the phase change unit 11 is the top surface of the first sub-electrode layer 1121, and the bottom of the phase change unit 11 is the bottom surface of the second electrode layer 113.

[0088] contrast Figure 10 and Figure 11 It is known that when the electrode layer 112 includes a first sub-electrode layer 1121 (amorphous carbon) and a second sub-electrode layer 1122 (including a titanium carbide layer 1122b and a carbon fiber layer 1122a), and the phase change storage layer 111 also includes a thermal resistance intercalation layer 1112, better thermal performance can be achieved (more convergent heat distribution and higher temperature), thereby reducing power consumption by nearly 40%.

[0089] Please see Figure 12 , Figure 12 yes Figure 8 and Figure 9 A schematic diagram of the current pulses in the corresponding memory cell during the RESET operation. Among them, Figure 9 In the storage unit 10 corresponding to the embodiment, the electrodes of the phase change unit 11 are made of amorphous silicon; Figure 8 In the corresponding storage unit 10 of the embodiment, the electrode layer 112 of the phase change unit 11 adopts a first sub-electrode layer 1121, a carbon fiber layer 1122a and a titanium carbide layer 1122b, and the phase change storage layer 111 also includes a thermal resistance intercalation layer 1112 (specifically amorphous carbon).

[0090] The RESET operation consists of a first pulse stage and a second pulse stage. The first pulse stage is used to enable gating layer 122, and the second pulse stage performs the RESET operation. Solid lines represent... Figure 8 The RESET current of the memory cell 10 corresponding to the embodiment is represented by the dashed line. Figure 9 The RESET current of the storage unit 10 corresponding to the embodiment. A comparison shows that the current application provides... Figure 8 In this example, the RESET current can be reduced by 40%.

[0091] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0092] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0093] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0094] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A phase-change memory, characterized in that, include: Substrate; Multiple memory cells are arranged in an array on the substrate. Each memory cell includes a phase change storage layer and an electrode layer. The electrode layer is located on at least one side of the phase change storage layer along a first direction, which is perpendicular to the surface of the substrate. The electrode layer includes a first sub-electrode layer and a second sub-electrode layer stacked along the first direction. The material of the first sub-electrode layer includes amorphous carbon, and the thermal conductivity of the second sub-electrode layer is less than that of the amorphous carbon.

2. The phase-change memory according to claim 1, characterized in that, The thermal conductivity of the second sub-electrode layer is less than or equal to 5 W / m·K, and the thermal conductivity of the amorphous carbon is 1 W / m·K to 10 W / m·K.

3. The phase-change memory according to claim 1, characterized in that, The material of the second sub-electrode layer includes carbon fiber, and the second sub-electrode layer has a surface facing away from the substrate, wherein the axial angle of the carbon fiber relative to the surface is 55° to 65°.

4. The phase-change memory according to claim 3, characterized in that, The material of the second sub-electrode layer also includes titanium carbide.

5. The phase-change memory according to claim 4, characterized in that, The second sub-electrode layer includes a titanium carbide layer and a carbon fiber layer, with the titanium carbide layer located between the carbon fiber layer and the phase change storage layer.

6. The phase-change memory according to claim 4 or 5, characterized in that, The first sub-electrode layer has a volume fraction of 60% to 80% in the electrode layer, and the second sub-electrode layer has a volume fraction of 20% to 40% in the electrode layer.

7. The phase-change memory according to claim 5, characterized in that, The thickness of the first sub-electrode layer is 10nm~15nm, the thickness of the carbon fiber layer is 3nm~5nm, and the thickness of the titanium carbide layer is 1nm~3nm.

8. The phase-change memory according to claim 1, characterized in that, The electrode layer is located on the side of the phase change storage layer away from the substrate, and the second sub-electrode layer is located between the phase change storage layer and the first sub-electrode layer.

9. The phase-change memory according to claim 1, characterized in that, The phase change storage layer includes a first phase change layer, a thermal resistance intercalation layer, and a second phase change layer stacked along the first direction, wherein the thermal resistance intercalation layer is located between the first phase change layer and the second phase change layer. The melting temperature of the thermal resistance intercalation layer is greater than that of the first phase change layer and also greater than that of the second phase change layer.

10. The phase-change memory according to claim 9, characterized in that, The material of the thermal resistance intercalation layer includes amorphous carbon.

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