MIM capacitor and preparation method thereof
By encapsulating diffusion suppression layers and insulating layers during the fabrication of MIM capacitors, the problem of weak sites in three-dimensional MIM capacitors is solved, thereby improving the reliability and electrical performance of the devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUA HONG SEMICON WUXI LTD
- Filing Date
- 2026-01-12
- Publication Date
- 2026-05-15
AI Technical Summary
Three-dimensional MIM capacitors have weak points at the top of the trench sidewalls, which leads to premature TDDB (Time-Delayed Breakdown) failure of the device, affecting the device's reliability and electrical performance.
In the process of fabricating MIM capacitors, a diffusion suppression layer is formed to cover the sidewalls and bottom wall of the trench, and the trench is filled by spin-coating a material layer. The excess part is removed by etching back, and an insulating layer is formed to wrap the top of the diffusion suppression layer to avoid subsequent grinding damage, thus forming a MIM capacitor.
This improves the reliability and electrical performance of the device, avoids accidental damage to weak points on the trench sidewalls, and enhances the overall performance of the MIM capacitor.
Smart Images
Figure CN122054610A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a MIM capacitor and its fabrication method. Background Technology
[0002] With the development of image sensor (CIS) technology, the demand for high dynamic range is increasing, and LOFIC (Lateral Overflow Capacitor) technology can effectively solve this problem. Currently, in traditional planar high dielectric constant (High K) MIM capacitors, using a metal oxide layer (such as aluminum oxide, hafnium oxide, etc.) deposited by atomic layer deposition (ALD) as the dielectric layer allows the capacitance density of the MIM capacitor to reach 3 fF / µm. 2 ~7fF / um 2 Those skilled in the art have found that the capacitance density performance of three-dimensional MIM capacitors (groove MIM capacitors) is 3 to 8 times higher than that of traditional planar High K MIM capacitors.
[0003] However, the weak points in the three-dimensional MIM capacitor process often occur at the interface of the trench sidewalls after the chemical mechanical polishing (CMP) process removes the excess upper metal electrode material layer (the CMP step of removing the excess upper metal electrode material layer occurs after the upper metal electrode material layer / body metal material layer is filled in the trench). The top of the lower metal electrode layer on the trench sidewall and the top of the metal ion barrier layer (e.g., TiN layer) on the trench sidewall are easily damaged by the chemical mechanical polishing process, causing the device's reliability TDDB (time breakdown) to fail prematurely at the weak points of the three-dimensional MIM capacitor, thus affecting the device's reliability and electrical performance. Summary of the Invention
[0004] This application provides a MIM capacitor and its fabrication method, which can solve the problem that traditional three-dimensional MIM capacitors have weak points at the top of the trench sidewall, causing the device's reliability TDDB (time breakdown) to fail prematurely at the weak points, thus affecting the device's reliability and electrical performance.
[0005] On one hand, embodiments of this application provide a method for fabricating a MIM capacitor, comprising: A semiconductor structure is provided, wherein metal interconnects are formed in the semiconductor structure, and a first barrier layer and a first interlayer dielectric layer covering the first barrier layer are sequentially formed on the semiconductor structure. The first interlayer dielectric layer and the first barrier layer are etched and stopped on the surface of the semiconductor structure to form a trench, wherein the trench exposes a portion of the metal interconnect; A diffusion inhibition layer is formed, which covers the sidewalls and bottomwalls of the trench and the first interlayer dielectric layer; A spin-coated material layer is formed, which fills the trench and covers the diffusion inhibition layer on the first interlayer dielectric layer; Remove the spin-coated material layer on the first interlayer dielectric layer and remove a portion of the spin-coated material layer in the trench; The diffusion inhibition layer on the first interlayer dielectric layer and the diffusion inhibition layer on the trench sidewall that are not covered by the spin-coated material layer are removed by etching back, so that the top of the diffusion inhibition layer on the trench sidewall does not exceed the top of the trench; Remove the remaining thickness of the spin-coated material layer in the trench; An insulating layer is formed, which covers the remaining diffusion suppression layer in the trench, the trench sidewalls not covered by the diffusion suppression layer, and the surface of the first interlayer dielectric layer; A main metal material layer is formed, which fills the trench and the insulating layer on the first interlayer dielectric layer; The main metal material layer extending beyond the upper surface of the insulating layer on the first interlayer dielectric layer and the main metal material layer extending beyond the top of the trench are removed by grinding, so that the upper surface of the main metal material layer in the trench is flush with the upper surface of the insulating layer on the first interlayer dielectric layer, wherein the diffusion suppression layer, the insulating layer and the main metal material layer constitute a MIM capacitor.
[0006] Optionally, in the method for fabricating the MIM capacitor, after the diffusion suppression layer on the first interlayer dielectric layer and the diffusion suppression layer on the trench sidewall that is not covered by the spin-coated material layer are removed by back etching, the height of the remaining diffusion suppression layer on the trench sidewall is 10% to 30% of the total trench depth.
[0007] Optionally, in the method for fabricating the MIM capacitor, the thickness of the diffusion suppression layer is 10 nm to 50 nm.
[0008] Optionally, in the method for fabricating the MIM capacitor, the diffusion suppression layer is made of TiN.
[0009] Optionally, in the method for fabricating the MIM capacitor, the insulating layer is formed using an atomic layer deposition process.
[0010] Optionally, in the method for preparing the MIM capacitor, the insulating layer is made of Al2O3, hafnium oxide, or zirconium oxide.
[0011] Optionally, in the method for preparing the MIM capacitor, the thickness of the insulating layer is 5 nm to 30 nm.
[0012] Optionally, in the method for preparing the MIM capacitor, the main metal material layer is made of copper.
[0013] Optionally, in the method for fabricating the MIM capacitor, after grinding away the main metal material layer extending beyond the upper surface of the insulating layer on the first interlayer dielectric layer and the main metal material layer extending beyond the top of the trench, the method for fabricating the MIM capacitor further includes: A second barrier layer is formed, which covers the insulating layer and the main metal material layer; A second interlayer dielectric layer is formed, which covers the second barrier layer; The second interlayer dielectric layer and the second barrier layer are etched and stopped on the surface of the main metal material layer in the trench to form a through hole; A conductive plug material layer is formed, which fills the through hole and contacts the main metal material layer in the trench.
[0014] On the other hand, embodiments of this application also provide a MIM capacitor, including: A semiconductor structure in which metal interconnects are formed, and a first barrier layer and a first interlayer dielectric layer covering the first barrier layer are sequentially formed on the semiconductor structure. A trench located between the first interlayer dielectric layer and the first barrier layer, wherein the trench exposes a portion of the metal interconnect; A diffusion inhibition layer covers the bottom wall and part of the sidewall of the trench, wherein the top of the diffusion inhibition layer on the sidewall of the trench does not exceed the top of the trench; An insulating layer that covers the diffusion suppression layer in the trench, the trench sidewalls not covered by the diffusion suppression layer, and the surface of the first interlayer dielectric layer; A main metal material layer fills the trench, wherein the upper surface of the main metal material layer in the trench is flush with the upper surface of the insulating layer on the first interlayer dielectric layer, and the diffusion suppression layer, the insulating layer and the main metal material layer constitute a MIM capacitor.
[0015] The technical solution of this application has at least the following advantages: In the method for fabricating a MIM capacitor provided in this application, after forming a diffusion suppression layer in the trench, a spin-coated material layer is coated on the surface of the diffusion suppression layer on the first interlayer dielectric layer and then the spin-coated material layer on the first interlayer dielectric layer is removed. Next, the spin-coated material layer on the first interlayer dielectric layer and a portion of the spin-coated material layer in the trench are removed. Then, the diffusion suppression layer on the first interlayer dielectric layer and the diffusion suppression layer on the trench sidewall not covered by the spin-coated material layer are etched back to remove them, ensuring that the top of the diffusion suppression layer does not exceed the top of the trench. Subsequently, an insulating layer is formed on the remaining diffusion suppression layer in the trench, the trench sidewall not covered by the diffusion suppression layer, and the surface of the first interlayer dielectric layer. This insulating layer can wrap around the top of the diffusion suppression layer, thus avoiding the situation where the top of the diffusion suppression layer (lower metal plate layer) on the trench sidewall is easily damaged by the grinding process when the main metal material layer on the first interlayer dielectric layer is removed during subsequent grinding. This eliminates the weak points at the top of the trench sidewall of the trench MIM capacitor, improving the reliability and electrical performance of the device. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0017] Figure 1 This is a flowchart of a method for preparing a MIM capacitor according to an embodiment of the present invention; Figures 2-12 This is a schematic diagram of the semiconductor structure in each process step of the fabrication of the MIM capacitor according to an embodiment of the present invention; The reference numerals in the attached figures are explained as follows: 10-Semiconductor structure, 11-Metal interconnect, 20-Intermediate dielectric layer, 21-Conductive plug, 30-First barrier layer, 40-First interlayer dielectric layer, 41-Trench, 50-Diffusion suppression layer, 60-Spin-coated material layer, 61-Spin-coated material layer of remaining thickness, 70-Insulating layer, 80-Main metal material layer, 91-Second barrier layer, 92-Second interlayer dielectric layer, 93-Conductive plug material layer. Detailed Implementation
[0018] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0019] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0020] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0021] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0022] This application provides a method for fabricating a MIM capacitor, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating a MIM capacitor according to an embodiment of the present invention. The method for fabricating a MIM capacitor includes: First, perform step S1: Refer to Figure 2 , Figure 2 This is a schematic diagram of a semiconductor structure after the formation of the first interlayer dielectric layer according to an embodiment of the present invention. A semiconductor structure 10 is provided, in which metal interconnects 11 are formed. An intermediate dielectric layer 20 is also formed on the surface of the semiconductor structure 10, and a conductive plug 21 is formed in the intermediate dielectric layer 20. The conductive plug 21 is connected to the metal interconnects 11. Further, a first barrier layer 30 and a first interlayer dielectric layer 40 covering the first barrier layer 30 are sequentially formed on the semiconductor structure 10 (intermediate dielectric layer 20).
[0023] In this embodiment, the metal interconnect 11 is made of copper; the intermediate dielectric layer 20 is made of silicon dioxide; the conductive plug 21 is made of copper; the first barrier layer 30 is made of nitrogen-doped silicon carbide (NDC); and the first interlayer dielectric layer 40 is made of silicon dioxide.
[0024] Then, proceed to step S2: (Refer to...) Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after the trench is formed according to an embodiment of the present invention. The first interlayer dielectric layer 40 and the first barrier layer 30 are etched and stopped on the surface of the intermediate dielectric layer 20 on the semiconductor structure 10 to form a trench 41, wherein the trench 41 exposes the conductive plug 21 connecting the metal interconnect 11.
[0025] Next, proceed to step S3: (Refer to...) Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after the formation of the diffusion suppression layer according to an embodiment of the present invention. The diffusion suppression layer 50 is formed, and the diffusion suppression layer 50 covers the sidewalls and bottom wall of the trench 41 and the first interlayer dielectric layer 40.
[0026] Preferably, the thickness of the diffusion inhibition layer 50 is 10nm~50nm.
[0027] In this embodiment, the diffusion suppression layer 50 is made of TiN.
[0028] Preferably, the diffusion inhibition layer 50 is formed using a physical vapor deposition (PVD) process or an atomic layer deposition (ALD) process.
[0029] Further, proceed to step S4: (Refer to...) Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after the formation of the spin-coated material layer according to an embodiment of the present invention. The spin-coated material layer 60 is formed, which fills the trench 41 and covers the diffusion suppression layer 50 on the first interlayer dielectric layer 40.
[0030] Preferably, the spin-coated material layer 60 is at least one of a spin-coated carbon layer (SOC) or a photoresist layer.
[0031] In this embodiment, the spin-coated material layer 60 is a spin-coated carbon layer (SOC).
[0032] In another embodiment, the spin-coated material layer 60 is a photoresist layer.
[0033] In two other embodiments, the spin-coated material layer 60 is a stacked spin-coated carbon layer (SOC) and a photoresist layer.
[0034] Next, proceed to step S5: (Refer to...) Figure 6 , Figure 6This is a schematic diagram of the semiconductor structure after removing the spin-coated material layer on the first interlayer dielectric layer and removing a portion of the spin-coated material layer in the trench according to an embodiment of the present invention. The spin-coated material layer 60 on the first interlayer dielectric layer 40 and the spin-coated material layer 60 with a portion of the thickness in the trench 41 are removed.
[0035] Preferably, an ashing process or a dry etching process is used to remove the spin-coated material layer 60 on the first interlayer dielectric layer 40 and to remove a portion of the thickness of the spin-coated material layer 60 in the trench 41.
[0036] Further, proceed to step S6: Refer to Figure 7 , Figure 7 This is a schematic diagram of the semiconductor structure after the back etching removes the diffusion suppression layer on the first interlayer dielectric layer and the diffusion suppression layer on the trench sidewall that is not covered by the spin-coating material layer, according to an embodiment of the present invention. The back etching removes the diffusion suppression layer 50 on the first interlayer dielectric layer 40 and the diffusion suppression layer 50 on the trench sidewall that is not covered by the remaining thickness of the spin-coating material layer 61, so that the top of the diffusion suppression layer 50 on the trench sidewall does not exceed the top of the trench 41.
[0037] Preferably, after the diffusion inhibition layer 50 on the first interlayer dielectric layer 40 and the diffusion inhibition layer 50 on the sidewall of the trench 41 that is not covered by the remaining thickness of the spin-coated material layer 61, the height of the remaining diffusion inhibition layer 50 on the sidewall of the trench 41 is 10% to 30% of the total depth of the trench 41.
[0038] Next, proceed to step S7: (Refer to...) Figure 8 , Figure 8 This is a schematic diagram of the semiconductor structure after removing the remaining thickness of the spin-coated material layer 61 in the trench 41 according to an embodiment of the present invention.
[0039] Preferably, the remaining thickness of the spin-coated material layer 61 in the trench 41 is removed by an ashing process or a dry etching process.
[0040] Further, proceed to step S8: (Refer to...) Figure 9 , Figure 9 This is a schematic diagram of the semiconductor structure after the formation of the insulating layer according to an embodiment of the present invention. An insulating layer 70 is formed, which covers the remaining diffusion suppression layer 50 in the trench 41, the sidewalls of the trench 41 not covered by the diffusion suppression layer 50, and the surface of the first interlayer dielectric layer 40.
[0041] Preferably, the insulating layer 70 is formed using an atomic layer deposition process.
[0042] Preferably, the insulating layer 70 is made of Al2O3, hafnium oxide, or zirconium oxide.
[0043] In this embodiment, the thickness of the insulating layer 70 is 5nm to 30nm.
[0044] Preferably, the insulating layer 70 covers the top of the remaining diffusion suppression layer 50 in the trench 41.
[0045] Next, proceed to step S9: (Refer to...) Figure 10 , Figure 10 This is a schematic diagram of the semiconductor structure after the formation of the main metal material layer according to an embodiment of the present invention. The main metal material layer 80 is formed, and the main metal material layer 80 fills the trench 41 and the insulating layer 70 on the first interlayer dielectric layer 40.
[0046] In this embodiment, the main metal material layer 80 is made of copper.
[0047] Preferably, the host metal material layer 80 is formed using a physical vapor deposition process.
[0048] Finally, proceed to step S10: (Refer to...) Figure 11 , Figure 11 This is a schematic diagram of the semiconductor structure after the main metal material layer extending beyond the upper surface of the insulating layer on the first interlayer dielectric layer and the main metal material layer extending beyond the top of the trench are removed by grinding according to an embodiment of the present invention. A chemical mechanical polishing (CMP) process is used to remove the main metal material layer 80 extending beyond the upper surface of the insulating layer 70 on the first interlayer dielectric layer 40 and the main metal material layer 80 extending beyond the top of the trench 41, so that the upper surface of the main metal material layer 80 in the trench 41 is flush with the upper surface of the insulating layer 70 on the first interlayer dielectric layer 40. The diffusion suppression layer 50, the insulating layer 70, and the main metal material layer 80 constitute a trench MIM capacitor. Specifically, the diffusion suppression layer 50 is the lower electrode of the trench MIM capacitor, the insulating layer 70 is the intermediate dielectric layer of the MIM capacitor, and the main metal material layer 80 is the upper electrode of the trench MIM capacitor.
[0049] In other embodiments, during the process of using chemical mechanical polishing (CMP) to remove the main metal material layer 80 extending beyond the upper surface of the insulating layer 70 on the first interlayer dielectric layer 40 and the main metal material layer 80 extending beyond the top of the trench 41, CMP can also be used to over-polish and remove the insulating layer 70 and a portion of the thickness of the first interlayer dielectric layer 40 on the first interlayer dielectric layer 40. However, it is necessary to ensure that the top of the diffusion suppression layer 50 and the insulating layer 70 at the top of the diffusion suppression layer 50 are not polished, so that the insulating layer 70 can cover the top of the diffusion suppression layer 50, thereby preventing the diffusion suppression layer 50 from being accidentally polished. This eliminates the weak points at the top of the trench sidewall of the subsequent trench MIM capacitor, improving the reliability and electrical performance of the device.
[0050] Further reference Figure 12 , Figure 12 This is a schematic diagram of the semiconductor structure after the formation of the conductive plug material layer according to an embodiment of the present invention. After grinding away the main metal material layer 80 extending beyond the upper surface of the insulating layer 70 on the first interlayer dielectric layer 40 and the main metal material layer 80 extending beyond the top of the trench 41, the method for fabricating the MIM capacitor may further include: Step S11: Form a second barrier layer 91, which covers the insulating layer 70 and the main metal material layer 80; Step S12: Form a second interlayer dielectric layer 92, which covers the second barrier layer 91; Step S13: Etch the second interlayer dielectric layer 92 and the second barrier layer 91 and stop at the surface of the main metal material layer 80 in the trench 41 to form a through hole; Step S14: Form a conductive plug material layer 93, which fills the through hole and contacts the main metal material layer 80 in the trench 41.
[0051] In this embodiment, the second barrier layer 91 is made of nitrogen-doped silicon carbide (NDC); the second interlayer dielectric layer 92 is made of silicon dioxide.
[0052] In this application, after forming a diffusion suppression layer in the trench, a spin-coated material layer is applied to the trench and the surface of the diffusion suppression layer on the first interlayer dielectric layer. Then, the spin-coated material layer on the first interlayer dielectric layer and a portion of the spin-coated material layer in the trench are removed. Next, the diffusion suppression layer on the first interlayer dielectric layer and the diffusion suppression layer on the trench sidewall not covered by the spin-coated material layer are etched back to remove the diffusion suppression layer, so that the top of the diffusion suppression layer does not exceed the top of the trench. Then, an insulating layer is formed on the remaining diffusion suppression layer in the trench, the trench sidewall not covered by the diffusion suppression layer, and the surface of the first interlayer dielectric layer. This insulating layer can cover the top of the diffusion suppression layer, thereby avoiding the situation where the top of the diffusion suppression layer (metal lower electrode layer) on the trench sidewall is easily damaged by the grinding process due to the subsequent grinding removal of the main metal material layer on the first interlayer dielectric layer. This eliminates the weak point at the top of the trench sidewall of the trench MIM capacitor, improving the reliability and electrical performance of the device.
[0053] Based on the same inventive concept, this application also provides a MIM capacitor, see reference. Figure 11 The MIM capacitor includes: A semiconductor structure 10, wherein a metal interconnect 11 is formed in the semiconductor structure 10, and a first barrier layer 30 and a first interlayer dielectric layer 40 covering the first barrier layer 30 are sequentially formed on the semiconductor structure 10. Trench 41, the trench 41 being located in the first interlayer dielectric layer 40 and the first barrier layer 30, wherein the trench 41 exposes a portion of the metal interconnect 11; A diffusion inhibition layer 50 covers the bottom wall and part of the sidewall of the trench 41, wherein the top end of the diffusion inhibition layer 50 on the sidewall of the trench 41 does not exceed the top end of the trench 41. An insulating layer 70 covers the diffusion suppression layer 50 in the trench 41, the sidewalls of the trench 41 not covered by the diffusion suppression layer 50, and the surface of the first interlayer dielectric layer 40. A main metal material layer 80 covers and fills the insulating layer 70 in the trench 41. The upper surface of the main metal material layer 80 in the trench 41 is flush with the upper surface of the insulating layer 70 on the first interlayer dielectric layer 40. At this time, the diffusion suppression layer 50, the insulating layer 70 and the main metal material layer 80 constitute a MIM capacitor. Specifically, the diffusion suppression layer 50 is the lower electrode of the trench MIM capacitor, the insulating layer 70 is the intermediate dielectric layer of the MIM capacitor, and the main metal material layer 80 is the upper electrode of the trench MIM capacitor.
[0054] In the MIM capacitor provided in this application, the top of the diffusion suppression layer does not exceed the top of the trench, so that the insulating layer can wrap the top of the diffusion suppression layer. This avoids the situation where the top of the diffusion suppression layer (lower metal plate layer) on the trench sidewall is accidentally damaged by the grinding process when the main metal material layer beyond the first interlayer dielectric layer is removed in the subsequent grinding process. This makes the weak point at the top of the trench sidewall of the trench MIM capacitor no longer exist, thus improving the reliability and electrical performance of the device.
[0055] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for fabricating a MIM capacitor, characterized in that, include: A semiconductor structure is provided, wherein metal interconnects are formed in the semiconductor structure, and a first barrier layer and a first interlayer dielectric layer covering the first barrier layer are sequentially formed on the semiconductor structure. The first interlayer dielectric layer and the first barrier layer are etched and stopped on the surface of the semiconductor structure to form a trench, wherein the trench exposes a portion of the metal interconnect; A diffusion inhibition layer is formed, which covers the sidewalls and bottomwalls of the trench and the first interlayer dielectric layer; A spin-coated material layer is formed, which fills the trench and covers the diffusion inhibition layer on the first interlayer dielectric layer; Remove the spin-coated material layer on the first interlayer dielectric layer and remove a portion of the spin-coated material layer in the trench; The diffusion inhibition layer on the first interlayer dielectric layer and the diffusion inhibition layer on the trench sidewall that are not covered by the spin-coated material layer are removed by etching back, so that the top of the diffusion inhibition layer on the trench sidewall does not exceed the top of the trench; Remove the remaining thickness of the spin-coated material layer in the trench; An insulating layer is formed, which covers the remaining diffusion suppression layer in the trench, the trench sidewalls not covered by the diffusion suppression layer, and the surface of the first interlayer dielectric layer; A main metal material layer is formed, which fills the trench and the insulating layer on the first interlayer dielectric layer; The main metal material layer extending beyond the upper surface of the insulating layer on the first interlayer dielectric layer and the main metal material layer extending beyond the top of the trench are removed by grinding, so that the upper surface of the main metal material layer in the trench is flush with the upper surface of the insulating layer on the first interlayer dielectric layer, wherein the diffusion suppression layer, the insulating layer and the main metal material layer constitute a MIM capacitor.
2. The method for preparing a MIM capacitor according to claim 1, characterized in that, After the diffusion inhibition layer on the first interlayer dielectric layer and the diffusion inhibition layer on the trench sidewall that are not covered by the spin-coated material layer are removed by back etching, the height of the remaining diffusion inhibition layer on the trench sidewall is 10% to 30% of the total trench depth.
3. The method for preparing a MIM capacitor according to claim 1, characterized in that, The thickness of the diffusion inhibition layer is 10nm~50nm.
4. The method for preparing a MIM capacitor according to claim 1, characterized in that, The diffusion inhibition layer is made of TiN.
5. The method for preparing a MIM capacitor according to claim 1, characterized in that, The insulating layer is formed using atomic layer deposition (ALD) technology.
6. The method for preparing a MIM capacitor according to claim 1, characterized in that, The insulating layer is made of Al2O3, hafnium oxide, or zirconium oxide.
7. The method for preparing a MIM capacitor according to claim 1, characterized in that, The thickness of the insulating layer is 5nm~30nm.
8. The method for preparing a MIM capacitor according to claim 1, characterized in that, The main metal material layer is made of copper.
9. The method for preparing a MIM capacitor according to claim 1, characterized in that, After grinding away the main metal material layer extending beyond the upper surface of the insulating layer on the first interlayer dielectric layer and the main metal material layer extending beyond the top of the trench, the method for fabricating the MIM capacitor further includes: A second barrier layer is formed, which covers the insulating layer and the main metal material layer; A second interlayer dielectric layer is formed, which covers the second barrier layer; The second interlayer dielectric layer and the second barrier layer are etched and stopped on the surface of the main metal material layer in the trench to form a through hole; A conductive plug material layer is formed, which fills the through hole and contacts the main metal material layer in the trench.
10. A MIM capacitor, characterized in that, include: A semiconductor structure in which metal interconnects are formed, and a first barrier layer and a first interlayer dielectric layer covering the first barrier layer are sequentially formed on the semiconductor structure. A trench located between the first interlayer dielectric layer and the first barrier layer, wherein the trench exposes a portion of the metal interconnect; A diffusion inhibition layer covers the bottom wall and part of the sidewall of the trench, wherein the top of the diffusion inhibition layer on the sidewall of the trench does not exceed the top of the trench; An insulating layer that covers the diffusion suppression layer in the trench, the trench sidewalls not covered by the diffusion suppression layer, and the surface of the first interlayer dielectric layer; A main metal material layer fills the trench, wherein the upper surface of the main metal material layer in the trench is flush with the upper surface of the insulating layer on the first interlayer dielectric layer, and the diffusion suppression layer, the insulating layer and the main metal material layer constitute a MIM capacitor.