Gallium nitride semiconductor device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor devices, and discloses a gallium nitride semiconductor device and a preparation method thereof. The gallium nitride semiconductor device includes a gallium nitride epitaxial layer, a regrowth layer, and a second strained layer. The gallium nitride epitaxial layer comprises a first barrier layer and a grid electrode which are sequentially stacked in the first direction; the grid electrode and the regrowth layer are arranged on the side, away from the channel layer, of the first barrier layer. The regrowth layer and the grid electrode are arranged at intervals to form a first gap; the second strain layer is arranged on the side, away from the barrier layer, of the regrowth layer, arranged on the side, away from the barrier layer, of the grid electrode and further arranged on the inner side face of the first gap. According to the invention, through the arrangement of the second strain layer, one side face, deviating from the first barrier layer, of the grid electrode, one side face, deviating from the first barrier layer, of the regrowth layer and the inner surface of the first gap are completely covered, the problem of incomplete coverage of the strain layer in a traditional process is solved, and the regulation and control capability of leakage current is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a gallium nitride semiconductor device and its fabrication method. Background Technology

[0002] Gallium nitride (GaN) semiconductor devices show broad application prospects in the field of power amplification. For example... Figure 1 As shown, the fabrication of this type of device typically follows this process: during the growth of gallium nitride (GaN) epitaxial layers, P-type gallium nitride is formed using a patterning process, followed by the growth of a first strain layer, typically made of aluminum nitride; then, an aluminum gallium nitride (AlGaN) regrowth region is defined using a patterning or sidewall process, and AlGaN epitaxial regrowth is performed; subsequently, a second strain layer, typically made of aluminum nitride, and a surface passivation layer are deposited; finally, the fabrication of the ohmic contact and field plate structure is completed.

[0003] However, existing device structures still face several challenges in fabrication. In the interface region between the P-type GaN gate and the regrown AlGaN layer, there is incomplete coverage of the aluminum nitride strain layer. This coverage defect leads to uneven electric field distribution at the interface, weakening the effective control of leakage current and affecting the device's static performance and reliability. The first strain layer is prone to crystallization transformation during subsequent high-temperature AlGaN regrowing. This process disrupts the originally uniform and dense P-GaN / AlN interface, introducing grain boundaries and defect states, increasing leakage current in the gate region. Excessive leakage current between the gate and source may cause false turn-on in applications, severely affecting the stability and safety of circuit operation. Furthermore, the crystallization of the first strain layer also leads to the degradation of its stress state and dielectric properties, further affecting the electrical stability and long-term reliability of the gate structure, and limiting the device's performance under high power and high frequency conditions. Summary of the Invention

[0004] This invention provides a gallium nitride semiconductor device and its fabrication method. The gallium nitride semiconductor device of this invention achieves complete coverage of the gate surface, the regenerated layer surface, and the inner surface of the first gap between them by forming a first gap between the gate and the regenerated layer and providing a second strain layer. This solves the problem of incomplete strain layer coverage in traditional processes, reduces leakage current in the drift region, makes the electric field distribution at the interface uniform, and improves the ability to control leakage current.

[0005] This invention provides a gallium nitride semiconductor device, comprising: A gallium nitride epitaxial layer includes a first barrier layer and a gate layer sequentially stacked along a first direction; the gate layer is disposed on one side of the first barrier layer. A regenerated layer is disposed on one side of the first barrier layer; the regenerated layer is spaced apart from the gate to form a first gap; The second strain layer is disposed on the side of the regenerated layer and the gate opposite to the first barrier layer, and is also disposed on the inner surface of the first gap.

[0006] The gallium nitride semiconductor device provided by the present invention further includes: A first dielectric layer is disposed on the side of the second strain layer opposite to the gallium nitride epitaxial layer, and the first gap is filled with the first dielectric layer.

[0007] The gallium nitride semiconductor device provided by the present invention further includes: The drain and source are provided, with one end of each being disposed on the side of the first dielectric layer away from the second strain layer; the other end of each being passes through the first dielectric layer, the second strain layer, and the regenerated layer and is electrically connected to the channel layer or the first barrier layer; the gate is disposed between the drain and the source.

[0008] The gallium nitride semiconductor device provided by the present invention further includes: The second dielectric layer is disposed on the side of the first dielectric layer opposite to the second strain layer; A field plate is disposed on the second dielectric layer.

[0009] According to the gallium nitride semiconductor device provided by the present invention, the material of the second strain layer includes at least one of aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum gallium nitride, indium aluminum nitride, and indium gallium nitride.

[0010] In the gallium nitride semiconductor device provided by the present invention, the material of the second strain layer is amorphous aluminum nitride.

[0011] In the gallium nitride semiconductor device provided by the present invention, the first gap is annular and arranged around the gate.

[0012] According to the gallium nitride semiconductor device provided by the present invention, the side of the gate facing the regenerated layer is an inclined surface and / or the side of the regenerated layer facing the gate is an inclined surface.

[0013] According to the gallium nitride semiconductor device provided by the present invention, the gallium nitride epitaxial layer further includes a substrate, a transition layer, a buffer layer and a channel layer stacked along the first direction; the channel layer is disposed on the side of the first barrier layer away from the gate, the buffer layer is disposed on the side of the channel layer away from the first barrier layer, the transition layer is disposed on the side of the buffer layer away from the channel layer, and the substrate is disposed on the side of the transition layer away from the buffer layer.

[0014] A second aspect of the present invention provides a method for fabricating a gallium nitride semiconductor device, for fabricating the gallium nitride semiconductor device described in any of the preceding claims, comprising: A gate is formed on one side of the first barrier layer of the gallium nitride epitaxial layer; A first strain layer is grown on one side of the first barrier layer and on the surface of the gate; A regrowth region is defined on one side of the first barrier layer, and the first strain layer and dielectric mask layer are stacked on the surface of the gate. A regeneration layer is grown in the regeneration region; Remove the first strain layer and the dielectric mask layer to form a first gap between the gate and the regenerated layer; A second strain layer is grown on the side of the regenerated layer opposite to the first barrier layer, the side of the gate opposite to the first barrier layer, and the inner surface of the first gap.

[0015] According to the method for fabricating a gallium nitride semiconductor device provided by the present invention, the step of "defining a regrowth region on one side of the first barrier layer" includes: A regrowth region is defined on one side of the first barrier layer using a patterning process or a sidewall process.

[0016] According to the method for fabricating a gallium nitride semiconductor device provided by the present invention, after the step of "growing a second strain layer on the side of the regenerated layer opposite to the first barrier layer, the side of the gate opposite to the first barrier layer, and the inner surface of the first gap", the method further includes: A first dielectric layer is grown on the side of the second strain layer that is opposite to the regenerated layer; A first dielectric layer is filled into the first gap.

[0017] The present invention provides a gallium nitride semiconductor device, which forms a first gap between the gate and the regenerated layer by setting a gate and a regenerated layer at intervals on the same side of a first barrier layer; by depositing a second strain layer on the side of the regenerated layer away from the barrier layer, the side of the gate away from the barrier layer, and the inner surface of the first gap, complete coverage of the interface between the gate and the regenerated layer is achieved, the electric field distribution in the drift region is improved, the problem of incomplete strain layer coverage in traditional processes is solved, the leakage current in the drift region is reduced, the electric field distribution at the interface is made uniform, the ability to control leakage current is improved, and thus the static performance and reliability of the device are improved.

[0018] The gallium nitride semiconductor device fabrication method provided by this invention involves applying a second strain layer after the high-temperature regeneration step. This avoids crystallization transformation of the strain layer, thereby preventing the introduction of grain boundaries and defect states due to crystallization. This reduces leakage current in the gate region and improves the stability of device operation. Simultaneously, the second strain layer seamlessly covers the side of the gate facing away from the first barrier layer, the side of the regenerated layer facing away from the first barrier layer, and the inner surface of the first gap, achieving complete coverage of the gate-regenerated layer interface. This improves the interface electric field distribution, enhances the ability to regulate leakage current, and ultimately improves the overall performance and reliability of the device. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is a flowchart of the fabrication process for existing gallium nitride semiconductor devices.

[0021] Figure 2 This is a schematic diagram of the gallium nitride epitaxial layer of the gallium nitride semiconductor device provided by the present invention.

[0022] Figure 3 This is one of the top view schematic diagrams of the gallium nitride semiconductor device provided by the present invention.

[0023] Figure 4 yes Figure 3 A schematic diagram of the structure of section AA.

[0024] Figure 5 This is the second top view schematic diagram of the gallium nitride semiconductor device provided by the present invention.

[0025] Figure 6 This is one of the structural schematic diagrams of the gallium nitride semiconductor device provided by the present invention.

[0026] Figure 7 This is the second schematic diagram of the structure of the gallium nitride semiconductor device provided by the present invention.

[0027] Figure 8 This is the third schematic diagram of the structure of the gallium nitride semiconductor device provided by the present invention.

[0028] Figure 9 This is the fourth schematic diagram of the structure of the gallium nitride semiconductor device provided by the present invention.

[0029] Figure 10This is the fifth schematic diagram of the gallium nitride semiconductor device provided by the present invention.

[0030] Figure 11 This is one of the schematic flowcharts of the method for fabricating gallium nitride semiconductor devices provided by the present invention.

[0031] Figure 12 This is the second schematic flowchart of the method for fabricating gallium nitride semiconductor devices provided by the present invention.

[0032] Figure label: 210. Gallium nitride epitaxial layer; 220. Regenerated layer; 230. Second strained layer; 240. First dielectric layer; 260. Second dielectric layer; 270. Field plate; 280. First strained layer; 290. Dielectric mask layer; 211. Substrate; 212. Transition layer; 213. Buffer layer; 214. Channel layer; 215. First barrier layer; 216. Gate; 217. First gap; 251. Source; 252. Drain. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0034] In the description of this specification, it should be noted that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are used only for the convenience of describing this specification. They do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this specification. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0035] In the description of this specification, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this invention based on the specific circumstances.

[0036] In this specification, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0037] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this specification. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0038] In the embodiments of this specification, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0039] like Figures 2 to 10 As shown, a specific embodiment of the first aspect of the present invention provides a gallium nitride semiconductor device. The gallium nitride semiconductor device includes a gallium nitride epitaxial layer 210, a regenerated layer 220, and a second strained layer 230.

[0040] The gallium nitride epitaxial layer 210 includes a first barrier layer 215 and a gate 216 sequentially stacked along a first direction; the gate 216 is disposed on one side of the first barrier layer 215. The first barrier layer 215 and the channel layer 214 form a heterojunction, inducing a high-concentration two-dimensional electron gas (2DEG) through polarization effect, thereby controlling the threshold and on-resistance of the device. The material of the first barrier layer 215 is typically one of aluminum gallium nitride (AlGaN), aluminum indium nitride (InAlN), and aluminum nitride (AlN). The gate 216 can be used to adjust the energy band and surface passivation. The material of the gate 216 is typically p-type gallium nitride (P-GaN) or aluminum gallium nitride (AlGaN).

[0041] The regenerated layer 220 and the gate 216 are disposed together on the same side of the first barrier layer 215; the regenerated layer 220 and the gate 216 are arranged at intervals to form a first gap 217; the second strain layer 230 is disposed on the side of the regenerated layer 220 and the gate 216 away from the first barrier layer 215, and is also disposed on the inner surface of the first gap 217.

[0042] In this embodiment, by setting a gate 216 and a regenerated layer 220 spaced apart on the same side of the first barrier layer 215, a first gap 217 is formed between the regenerated layer 220 and the gate 216. By laying a second strain layer 230 on the side of the regenerated layer 220 away from the first barrier layer 215, the side of the gate 216 away from the first barrier layer 215, and the inner surface of the first gap 217, complete coverage of the interface between the gate and the regenerated layer is achieved, improving the electric field distribution in the drift region, reducing the leakage current in the drift region, solving the problem of incomplete strain layer coverage in traditional processes, making the electric field distribution at the interface uniform, improving the ability to control leakage current, and thus improving the static performance and reliability of the device.

[0043] Furthermore, the second strain layer 230 is formed after the high-temperature aluminum gallium nitride regeneration step, which avoids the problem of crystallization transformation of the strain layer in the conventional process, thereby preventing the introduction of grain boundaries and defect states and reducing leakage current in the gate region.

[0044] Compared with the prior art, the gallium nitride semiconductor device of the present invention can reduce leakage current by 1 to 1.5 orders of magnitude, thereby avoiding accidental activation of the device in application and improving the stability and safety of circuit operation.

[0045] It should be noted that the inner surface of the first gap 217 includes the lower side of the first gap 217, the side of the gate 216 facing the regenerated layer 220, and the side of the regenerated layer 220 facing the gate 216.

[0046] Optionally, the material of the regrown layer 220 includes at least one of aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), and indium gallium nitride (InGaN). Preferably, the material of the regrown layer 220 is aluminum gallium nitride (AlGaN). It should be noted that the regrown layer refers to a single-crystal semiconductor thin film layer deposited and grown again in a specific local area on a semiconductor wafer that has completed some or all of the front-end processes (such as epitaxial growth, patterning, etching, dielectric deposition, etc.) using epitaxial growth technology.

[0047] Optionally, the thickness of the regenerated layer 220 can be less than, greater than, or equal to the thickness of the gate 216. In other words, the upper surface of the regenerated layer 220 can be lower than, higher than, or at the same height as the upper surface of the gate 216.

[0048] In some embodiments of the present invention, the material of the second strain layer 230 includes at least one selected from aluminum nitride (AlN), aluminum oxide (Al2O3), aluminum oxynitride (AION), aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), and indium gallium nitride (InGaN). Using existing commonly used materials to fabricate the second strain layer 230 avoids the development of new materials, reduces the material development cost of the device, and improves the versatility of the device.

[0049] Preferably, the second strain layer 230 is made of amorphous aluminum nitride. In the prior art, the aluminum nitride strain layer is prone to crystallization transformation during the subsequent high-temperature aluminum gallium nitride (AlGaN) regrowth process. This process disrupts the originally uniform and dense interface, introducing grain boundaries and defect states, thereby increasing the leakage current in the gate region. In the specific embodiment of the present invention, amorphous aluminum nitride is used as the second strain layer 230. Since it is formed after the high-temperature regrowth step, crystallization transformation can be avoided, thus maintaining the uniformity and density of the interface and preventing the introduction of grain boundaries and defect states. Avoiding crystallization also reduces the risk of degradation of the stress state and dielectric properties of this layer, further enhancing the electrical stability and long-term reliability of the gate structure, and ensuring the performance of the device under high power and high frequency conditions.

[0050] In some embodiments of the present invention, the thickness of the second strain layer 230 is 0.5 nm to 3 nm. Optionally, the thickness of the second strain layer 230 can be 0.5 nm, 1 nm, or 3 nm. Controlling the thickness of the second strain layer 230 within the range of 0.5 nm to 3 nm allows for the formation of a dense and complete film while ensuring process feasibility. This thickness is sufficient to effectively and uninterruptedly cover the gate 216, the regenerated layer 220, and the inner surface of the first gap 217 between them, ensuring a uniform electric field distribution at the interface. This improves the ability to regulate and suppress leakage current, thereby enhancing the static performance and long-term reliability of the device and balancing leakage current and dynamic resistance characteristics.

[0051] like Figure 3 , Figure 4 and Figure 5As shown, in some embodiments of the present invention, the first gap 217 is annular and arranged around the gate 216, which can ensure that the entire periphery of the gate 216 is effectively isolated from the regenerated layer 220. Thus, the subsequently deposited second strain layer 230 can completely cover and passivate all sidewalls of the gate 216, thereby forming a uniform electric field distribution around the entire gate 216, effectively suppressing leakage current generated from all directions, and comprehensively improving the symmetry and electrical performance stability of the device.

[0052] Optionally, the cross-sectional shape of the first gap 217 can be circular or polygonal. Polygons include, but are not limited to, quadrilaterals or pentagons. Using a circular cross-section can avoid the electric field concentration problem caused by sharp corner structures, making the electric field distribution more gradual, thereby helping to improve the breakdown voltage and long-term operational reliability of the device. Using polygonal shapes such as quadrilaterals or pentagons is easier to pattern using standard photolithography processes, and has better compatibility with existing semiconductor manufacturing processes.

[0053] like Figure 7 As shown, in some embodiments of the present invention, the side of the gate 216 facing the regenerated layer 220 is an inclined surface and / or the side of the regenerated layer 220 facing the gate 216 is an inclined surface. In other words, at least one of the two opposite sides of the first gap 217 is an inclined surface. The inclined surface design can improve the step coverage quality of subsequent thin film deposition, ensuring that the second strain layer 230 and the first dielectric layer 240 can form a uniform, dense and uninterrupted capping layer. A high-quality capping layer can effectively passivate the sidewall interface of the gate 216, reduce the interface defect state density in this region, reduce leakage paths, and control the gate leakage current of the device at a low level, which helps to improve the static power consumption and reliability of the device. A high-quality capping layer can also avoid the formation of voids or weak points at the bottom of the gap due to excessively steep sidewalls, thereby ensuring the integrity of the gate sidewall passivation and the reliability of the device structure, mitigating the electric field concentration effect in the corner region of the gate 216; it can also suppress the increase of dynamic on-resistance, ensuring the stability and efficiency of the device in high-frequency switching applications.

[0054] like Figure 7 As shown, optionally, the angle α formed between the side of the gate 216 facing the regenerated layer 220 and the upper side of the first barrier layer 215 is an acute angle. The angle β formed between the side of the regenerated layer 220 facing the gate 216 and the upper side of the first barrier layer 215 is also an acute angle. This non-perpendicular sidewall profile, by weakening the electric field concentration effect at the gate edge, can reduce the electrical stress on the dielectric layer, further reducing the generation of trapped states and charge injection caused by high electric fields. This not only reduces leakage current but also suppresses current collapse and improves dynamic performance.

[0055] In some embodiments of the present invention, the width of the first gap 217, i.e., the dimension of the first gap 217 in the direction perpendicular to the first direction, is 10 nanometers to 1 micrometer; in other words, the dimension of the first gap 217 in the left-right direction is 10 nanometers to 1 micrometer. This design not only ensures that the second strain layer 230 and the first dielectric layer 240 can fully enter and fill the first gap 217 in subsequent processes, thereby achieving complete coverage and effective passivation of the sidewalls of the gate 216, avoiding voids or defects caused by incomplete filling due to an excessively narrow first gap 217, thus ensuring the integrity of the device structure and the stability of its electrical performance, but also effectively controls the lateral dimensions of the device, avoiding unnecessary increases in the parasitic resistance and capacitance of the device due to an excessively wide gap.

[0056] Optionally, the width of the first gap 217 can be 10 nanometers, 100 nanometers, 300 nanometers, 600 nanometers, or 1 micrometer.

[0057] For example, a gallium nitride semiconductor device includes a gallium nitride epitaxial layer 210, a regenerated layer 220, and a second strain layer 230. The gallium nitride epitaxial layer 210 includes a channel layer 214, a first barrier layer 215, and a gate 216 sequentially stacked along a first direction; the first barrier layer 215 is disposed on one side of the channel layer 214, and the gate 216 is disposed on the side of the first barrier layer 215 opposite to the channel layer 214. The regenerated layer 220 is disposed on the side of the first barrier layer 215 opposite to the channel layer 214; the regenerated layer 220 and the gate 216 are spaced apart to form a first gap 217; the second strain layer 230 is disposed on the side of both the regenerated layer 220 and the gate 216 opposite to the first barrier layer 215, and is also disposed on the inner surface of the first gap 217. By reserving a first gap 217 between the gate 216 and the regenerated layer 220, and subsequently filling and covering it with a second strain layer 230, a complete and uninterrupted coverage of the surface of the gate 216 (and its sidewalls and top) can be ensured. This solves the problem of uneven electric field caused by incomplete strain layer coverage in traditional processes, and improves the ability to control leakage current. Optionally, the second strain layer 230 is made of amorphous aluminum nitride, and its thickness is 1 nanometer. Using amorphous aluminum nitride as the second strain layer 230 avoids crystallization transformation during high-temperature regeneration, thereby preventing an increase in gate leakage current caused by the introduction of grain boundaries and defect states. Compared with existing devices, the leakage current can be reduced by 1 to 1.5 orders of magnitude, which can prevent the device from turning on falsely and improve the stability and safety of circuit operation. Meanwhile, the thickness of 1 nanometer falls within the range of 0.5 nanometers to 3 nanometers, which not only ensures the formation of a dense and complete cover layer, but also effectively utilizes its stress and dielectric properties, further guaranteeing the electrical stability and long-term reliability of the gate structure.

[0058] like Figures 8 to 10 As shown, in some embodiments of the present invention, the gallium nitride semiconductor device further includes a first dielectric layer 240. Optionally, the material of the first dielectric layer 240 includes at least one of silicon oxide (SiO2), aluminum oxide (Al2O3), and silicon nitride (SiN). In other words, the gallium nitride semiconductor device includes a gallium nitride epitaxial layer 210, a regenerated layer 220, a second strain layer 230, and a first dielectric layer 240. The gallium nitride epitaxial layer 210 includes a first barrier layer 215 and a gate 216 sequentially stacked along a first direction; the gate 216 and the regenerated layer 220 are both disposed on one side of the first barrier layer 215. The regenerated layer 220 and the gate 216 are spaced apart to form a first gap 217; the second strain layer 230 is disposed on the side of the regenerated layer 220 and the gate 216 away from the first barrier layer 215, and is also disposed on the inner side of the first gap 217. The first dielectric layer 240 is disposed on the side of the second strain layer 230 away from the gallium nitride epitaxial layer 210.

[0059] In this embodiment, the first dielectric layer 240 serves as a surface passivation layer, reducing the defect state density on the device surface, thereby suppressing current collapse and further reducing surface leakage current, which helps improve the dynamic performance and long-term operational stability of the device. Simultaneously, the first dielectric layer 240 also provides a planarized surface for subsequent electrode fabrication (including source, drain, and gate), which improves the reliability and yield of subsequent processes (such as metal deposition), ensuring consistency in device structure and performance.

[0060] like Figure 9 and Figure 10As shown, in some embodiments of the present invention, the gallium nitride semiconductor device further includes a source 251 and a drain 252. In other words, the gallium nitride semiconductor device includes a gallium nitride epitaxial layer 210, a regenerated layer 220, a second strain layer 230, a first dielectric layer 240, a source 251, and a drain 252. The gallium nitride epitaxial layer 210 includes a first barrier layer 215 and a gate 216 sequentially stacked along a first direction; the gate 216 and the regenerated layer 220 are both disposed on the same side of the first barrier layer 215. The regenerated layer 220 and the gate 216 are spaced apart to form a first gap 217. The first dielectric layer 240 is disposed on the side of the second strain layer 230 opposite to the gallium nitride epitaxial layer 210, and the first gap 217 is filled with the first dielectric layer 240. One end of the drain 252 and the source 251 are both disposed on the side of the first dielectric layer 240 away from the second strain layer 230; the other ends of the drain 252 and the source 251 pass through the first dielectric layer 240, the second strain layer 230, and the regenerated layer 220 and are electrically connected to the channel layer 214 or the first barrier layer 215. By directly penetrating the upper structure and connecting to the channel layer 214 or the first barrier layer 215, a low-resistivity ohmic contact is formed, thereby reducing the on-resistance of the device, which helps to reduce power loss during device operation and improve the overall energy conversion efficiency. The gate 216 is disposed between the drain 252 and the source 251, and the gate 216 is used to control the switching of the channel current between the source 251 and the drain 252. Using P-type gallium nitride as the gate 216 can realize enhancement-mode (i.e., normally off) device characteristics. The device remains in the off state when no positive voltage is applied to the gate, which can prevent accidental conduction in power applications, thereby improving the reliability and safety of the entire circuit system.

[0061] It should be noted that the structure and materials of the source electrode 251 and drain electrode 252 in this embodiment of the invention are existing technologies and will not be described in detail here.

[0062] like Figure 10As shown, in some embodiments of the present invention, the gallium nitride semiconductor device further includes a second dielectric layer 260 and a field plate 270. The material of the second dielectric layer 260 includes at least one of silicon oxide (SiO2), aluminum oxide (Al2O3), and silicon nitride (SiN). In other words, the gallium nitride semiconductor device includes a gallium nitride epitaxial layer 210, a regenerated layer 220, a second strain layer 230, a first dielectric layer 240, a source 251, a drain 252, the second dielectric layer 260, and a field plate 270. The gallium nitride epitaxial layer 210 includes a first barrier layer 215 and a gate 216 sequentially stacked along a first direction; the gate 216 and the regenerated layer 220 are disposed on the same side of the first barrier layer 215. The regenerated layer 220 and the gate 216 are spaced apart to form a first gap 217. The second strain layer 230 is disposed on the side of the regenerated layer 220 opposite to the first barrier layer 215, on the side of the gate 216 opposite to the first barrier layer 215, and also on the inner surface of the first gap 217. The first dielectric layer 240 is disposed on the side of the second strain layer 230 opposite to the gallium nitride epitaxial layer 210, and the first gap 217 is filled with the first dielectric layer 240. The second dielectric layer 260 is disposed on the side of the first dielectric layer 240 opposite to the second strain layer 230; the field plate 270 is disposed on the second dielectric layer 260. The field plate 270 is insulated through the second dielectric layer 260, and plays a role in modulating the electric field on the surface of the device. It can reduce the peak electric field intensity in areas such as the gate edge, thereby improving the overall breakdown voltage of the device, enabling it to withstand higher operating voltages, and thus improving the power performance and long-term reliability of the device.

[0063] Optionally, there can be multiple field plates 270 and multiple second dielectric layers 260, with each second dielectric layer 260 corresponding to one of the multiple field plates 270. The multiple second dielectric layers 260 are stacked along a first direction, and the multiple field plates 270 are respectively disposed on their corresponding second dielectric layers 260. This multi-field-plate 270 structure, compared to a single field plate 270, enables hierarchical and stepped modulation of the surface electric field of the device. It can more effectively smooth the electric field distribution throughout the high-field region from the gate to the drain 252, avoiding electric field concentration in a single area. This can further improve the breakdown voltage of the device, allowing it to operate safely at higher voltages, thereby enhancing the device's power handling capability and reliability in high-voltage applications.

[0064] It should be noted that the gallium nitride semiconductor device provided by the present invention includes at least one of gallium nitride high electron mobility transistor (GaN HEMT), gallium nitride field-effect transistor (GaN FET) and gallium nitride Schottky diode (GaN SBD).

[0065] like Figure 2As shown, in some embodiments of the present invention, the gallium nitride epitaxial layer 210 includes a substrate 211, a transition layer 212, a buffer layer 213, a channel layer 214, a first barrier layer 215, and a gate 216 stacked along a first direction. The gate 216 is disposed on one side of the first barrier layer 215, and the channel layer 214 is disposed on the side of the first barrier layer 215 opposite to the gate 216; the buffer layer 213 is disposed on the side of the channel layer 214 opposite to the first barrier layer 215, the transition layer 212 is disposed on the side of the buffer layer 213 opposite to the channel layer 214, and the substrate 211 is disposed on the side of the transition layer 212 opposite to the buffer layer 213. The substrate 211 is located at the bottom layer of the semiconductor device and is the physical basis of the entire device structure, used to support the functional layers above. The substrate 211 is typically made of silicon (Si), silicon carbide (SiC), or sapphire (Al2O3). The transition layer 212 alleviates the difference in lattice constant and thermal expansion coefficient between the substrate 211 and the buffer layer 213, laying the foundation for the subsequent growth of a high-quality gallium nitride channel layer 214. The transition layer 212 is typically made of aluminum nitride (AlN) or aluminum gallium nitride (AlGaN). The buffer layer 213 suppresses the conductivity of the substrate 211, traps impurities and defects, increases the breakdown voltage, and reduces leakage current. The buffer layer 213 is typically made of high-resistivity gallium nitride (GaN), iron-doped gallium nitride or aluminum gallium nitride, carbon-doped gallium nitride, or aluminum gallium nitride. The channel layer 214 is where the two-dimensional electron gas (2DEG) is formed, where electrons move at high speed at the top interface of this layer (i.e., the interface in contact with the first barrier layer 215). The channel layer 214 is typically made of unintentionally doped (UID) gallium nitride (GaN).

[0066] like Figure 11 and Figure 12 As shown, a specific embodiment of the second aspect of the present invention provides a method for fabricating a gallium nitride semiconductor device. This method for fabricating a gallium nitride semiconductor device is used to fabricate gallium nitride semiconductors according to any of the above embodiments, and includes: S110, A gate 216 is formed on one side of the first barrier layer 215 of the gallium nitride epitaxial layer 210.

[0067] S120. A first strain layer 280 is grown on one side of the first barrier layer 215 and on the surface of the gate 216. The material of the first strain layer 280 typically includes at least one of aluminum nitride, aluminum gallium nitride, indium aluminum nitride, and indium gallium nitride.

[0068] S130, a regrowth region is defined on one side of the first barrier layer 215, and a first strain layer 280 and a dielectric mask layer 290 are stacked on the surface of the gate 216. In other words, after the regrowth region is defined on one side of the first barrier layer 215, the first strain layer 280 and the dielectric mask layer 290 are stacked on the top of the gate 216 and the sidewall of the gate 216.

[0069] S140, A regeneration layer 220 is grown in the regeneration zone.

[0070] S150, remove the first strain layer 280 and the dielectric mask layer 290 to form a first gap 217 between the gate 216 and the regenerated layer 220.

[0071] S160, a second strain layer 230 is grown on the side of the regenerated layer 220 away from the first barrier layer 215, the side of the gate 216 away from the first barrier layer 215, and the inner surface of the first gap 217.

[0072] In this embodiment, the second strain layer 230 is applied after the high-temperature regeneration step (S140) to prevent the strain layer from undergoing a crystallization transition. This prevents the introduction of grain boundaries and defect states due to crystallization, thereby reducing leakage current in the gate region and improving the stability of device operation. Simultaneously, the second strain layer 230 seamlessly covers all surfaces, including the inner surface of the first gap 217, achieving complete coverage of the interface between the gate 216 and the regenerated layer. This improves the interface electric field distribution, enhances the ability to regulate leakage current, and ultimately improves the overall performance and reliability of the device.

[0073] In some embodiments of the present invention, the step of defining a regrowth region on one side of the first barrier layer 215 includes: defining the regrowth region on one side of the first barrier layer 215 using a patterning process or a spacer process. Using a patterning process, such as through standard semiconductor manufacturing techniques like photolithography and etching, a precise mask can be formed on the first barrier layer 215. The shape, size, and position of the regrowth region can be precisely controlled according to device performance requirements, thereby flexibly optimizing the device layout design. Using a spacer process, the regrowth region is defined by depositing and etching back a layer of material on the sidewall of the formed gate 216. This method can form a narrow region with a controllable width that is self-aligned with the edge of the gate 216, which helps control the width of the final formed first gap 217 and ensures the consistency and repeatability of device structural parameters.

[0074] This embodiment employs existing mature and reliable micro-nano fabrication technologies (patterning or sidewall fabrication) to ensure that the regrowth region can be efficiently and reliably defined, providing process assurance for the subsequent construction of high-performance, high-reliability gallium nitride semiconductor devices.

[0075] In some embodiments of the present invention, after the step of growing a second strain layer 230 on the side of the regenerated layer 220 opposite to the first barrier layer 215, the side of the gate 216 opposite to the first barrier layer 215, and the inner surface of the first gap 217, the method further includes: A first dielectric layer 240 is grown on the side of the second strain layer 230 away from the regenerated layer 220. The first dielectric layer 240 provides surface passivation for the entire device surface, reducing surface defects and trapped states, thereby suppressing current collapse effects and improving the dynamic performance and long-term stability of the device. Simultaneously, the first dielectric layer 240 also provides an insulating foundation for the subsequent field plate 270. The first dielectric layer 240 is filled into the first gap 217, completely filling the gap 217 left after the formation of the second strain layer 230 with a dielectric material, eliminating air gaps (whose dielectric constant is much lower than that of semiconductor materials), and making the dielectric environment inside the device more uniform. This alleviates the electric field concentration effect at the edge of the gate 216, avoiding premature breakdown caused by electric field spikes, thereby improving the breakdown voltage and overall reliability and durability of the device.

[0076] like Figure 2 and Figure 8 As shown, by way of example, this embodiment provides a gallium nitride semiconductor device and a method for fabricating it. The gallium nitride semiconductor device includes a gallium nitride epitaxial layer 210, an aluminum gallium nitride regenerated layer 220, a second strain layer 230, and a first dielectric layer 240.

[0077] The gallium nitride epitaxial layer 210 includes a silicon substrate 211, an aluminum nitride transition layer, a high-resistivity gallium nitride buffer layer 213, an unintentionally doped (UID) gallium nitride channel layer 214, an aluminum gallium nitride first barrier layer 215, and a p-type gallium nitride gate 216 stacked along the vertical direction. An aluminum nitride transition layer 212 is disposed on the upper side of the silicon substrate 211. A high-resistivity gallium nitride buffer layer 213 is disposed on the upper side of the aluminum nitride transition layer 212. An unintentionally doped (UID) gallium nitride channel layer 214 is disposed on the upper side of the high-resistivity gallium nitride buffer layer 213. An aluminum gallium nitride first barrier layer 215 is disposed on the upper side of the aluminum gallium nitride first barrier layer 215. A p-type gallium nitride gate 216 and a regenerated layer 220 are disposed on the upper side of the aluminum gallium nitride first barrier layer 215. An aluminum gallium nitride (AGaN) regrown layer 220 and a p-type gallium nitride gate 216 are spaced apart on the upper side of the AGaN first barrier layer 215, forming a first gap 217 between the regrown layer 220 and the p-type gallium nitride gate 216. An aluminum nitride second strain layer 230 is disposed on the upper side of the regrown layer 220, the upper side of the p-type gallium nitride gate 216, and the inner surface of the first gap 217. An aluminum oxide first dielectric layer 240 is disposed on the upper side of the aluminum nitride second strain layer 230.

[0078] like Figure 11As shown, the fabrication method of the gallium nitride semiconductor device includes the following steps: During the growth of the gallium nitride epitaxial layer 210, a gate 216 is formed by a patterning process. A first strain layer 280 is grown on the upper side surface of the first barrier layer 215, the upper side surface of the gate 216, and the sidewalls. Then, a regeneration region is defined on the upper side surface of the first barrier layer 215 by a patterning process, so that the first strain layer 280 and the dielectric mask layer 290 are stacked on the top and sidewalls of the gate 216. An aluminum gallium nitride regeneration layer 220 is epitaxially grown in the regeneration region. Then, the first strain layer 280 and the dielectric mask layer 290 are removed by wet etching, so that a first gap 217 is formed between the gate 216 and the regeneration layer 220. Finally, a second strain layer 230 is grown on the upper side surface of the regeneration layer 220, the upper side surface of the gate 216, and the inner surface of the first gap 217; then, a first dielectric layer 240 is grown on the upper side surface of the second strain layer 230 and in the first gap 217.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A gallium nitride semiconductor device, characterized in that, include: The gallium nitride epitaxial layer (210) includes a first barrier layer (215) and a gate (216) stacked sequentially along a first direction; the gate (216) is disposed on one side of the first barrier layer (215); A regenerated layer (220) is disposed on one side of the first barrier layer (215); the regenerated layer (220) and the gate (216) are arranged at a distance to form a first gap (217). The second strain layer (230) is disposed on the side of the regenerated layer (220) and the gate (216) away from the first barrier layer (215), and is also disposed on the inner surface of the first gap (217).

2. The gallium nitride semiconductor device according to claim 1, characterized in that, Also includes: A first dielectric layer (240) is disposed on the side of the second strain layer (230) away from the gallium nitride epitaxial layer (210), and the first gap (217) is filled with the first dielectric layer (240).

3. The gallium nitride semiconductor device according to claim 2, characterized in that, Also includes: The drain (252) and source (251) are arranged at one end on the side of the first dielectric layer (240) away from the second strain layer (230); the other end of the drain (252) and source (251) passes through the first dielectric layer (240), the second strain layer (230) and the regeneration layer (220) and is electrically connected to the channel layer (214) or the first barrier layer (215); the gate (216) is arranged between the drain (252) and source (251).

4. The gallium nitride semiconductor device according to claim 2, characterized in that, Also includes: The second dielectric layer (260) is disposed on the side of the first dielectric layer (240) opposite to the second strain layer (230); A field plate (270) is disposed on the second dielectric layer (260).

5. The gallium nitride semiconductor device according to claim 1, characterized in that, The material of the second strain layer (230) includes at least one of aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum gallium nitride, indium aluminum nitride, and indium gallium nitride.

6. The gallium nitride semiconductor device according to claim 5, characterized in that, The second strain layer (230) is made of amorphous aluminum nitride.

7. The gallium nitride semiconductor device according to claim 1, characterized in that, The first gap (217) is annular and arranged around the gate (216).

8. The gallium nitride semiconductor device according to claim 1, characterized in that, The side of the gate (216) facing the regenerated layer (220) is an inclined surface and / or the side of the regenerated layer (220) facing the gate (216) is an inclined surface.

9. The gallium nitride semiconductor device according to any one of claims 1 to 8, characterized in that, The gallium nitride epitaxial layer (210) further includes a substrate (211), a transition layer (212), a buffer layer (213), and a channel layer (214) stacked along the first direction; the channel layer (214) is disposed on the side of the first barrier layer (215) away from the gate (216), the buffer layer (213) is disposed on the side of the channel layer (214) away from the first barrier layer (215), the transition layer (212) is disposed on the side of the buffer layer (213) away from the channel layer (214), and the substrate (211) is disposed on the side of the transition layer (212) away from the buffer layer (213).

10. A method for fabricating a gallium nitride semiconductor device, characterized in that, For fabricating the gallium nitride semiconductor device according to any one of claims 1 to 9, comprising: A gate (216) is formed on one side of the first barrier layer (215) of the gallium nitride epitaxial layer (210). A first strain layer (280) is grown on one side of the first barrier layer (215) and on the surface of the gate (216). A regrowth region is defined on one side of the first barrier layer (215), and the first strain layer (280) and dielectric mask layer (290) are stacked on the surface of the gate (216). A regeneration layer (220) is grown in the regeneration region; Remove the first strain layer (280) and the dielectric mask layer (290) to form a first gap (217) between the gate (216) and the regenerated layer (220). A second strain layer (230) is grown on the side of the regenerated layer (220) away from the first barrier layer (215), the side of the gate (216) away from the first barrier layer (215), and the inner surface of the first gap (217).

11. The method for fabricating a gallium nitride semiconductor device according to claim 10, characterized in that, The step of "defining a regrowth region on one side of the first barrier layer (215)" includes: A regrowth region is defined on one side of the first barrier layer (215) using a patterning process or a sidewall process.

12. The method for fabricating a gallium nitride semiconductor device according to claim 10, characterized in that, After the step of "growing a second strain layer (230) on the side of the regenerated layer (220) facing away from the first barrier layer (215), on the side of the gate (216) facing away from the first barrier layer (215), and on the inner surface of the first gap (217)," the method further includes: A first dielectric layer (240) is grown on the side of the second strain layer (230) away from the regenerated layer (220); The first dielectric layer (240) is filled in the first gap (217).

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