Semiconductor device and forming method thereof
By designing a "larger top and smaller bottom" gate structure and dielectric layer shielding in GaN devices, the problem of insufficient voltage withstand capability of GaN devices was solved, and the electric field distribution and voltage withstand capability were improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2026-03-27
- Publication Date
- 2026-05-15
AI Technical Summary
Existing GaN devices have poor voltage withstand performance and uneven electric field distribution.
The substrate surface epitaxial layer structure is adopted, and the bottom of the gate is embedded in the first dielectric layer. The bottom size of the gate is smaller than the top size, forming a "large at the top and small at the bottom" structure. Combined with the first dielectric layer, the electric field is shielded, the electric field is dispersed, and the withstand voltage is improved.
The electric field is more evenly distributed around the gate, avoiding electric field concentration, significantly improving the device's withstand voltage and breakdown voltage, and making it suitable for a wide range of applications.
Smart Images
Figure CN122054640A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for forming the same. Background Technology
[0002] Gallium nitride (GaN) semiconductor devices, especially gallium nitride high electron mobility transistors (GaNHEMTs), have attracted widespread attention in recent years due to their superior performance, including high breakdown voltage, high operating frequency, and low on-resistance. With the continuous maturation of the technology, GaN devices are playing an increasingly important role in cutting-edge fields such as fast chargers in consumer electronics, power systems in data centers, and electric drive and on-board charging systems for new energy vehicles.
[0003] Currently, GaN devices on the market mostly use gate metal field plates and source metal field plates to optimize the electric field distribution and improve the device's withstand voltage.
[0004] However, existing GaN devices have poor voltage withstand performance. Summary of the Invention
[0005] The technical problem solved by the present invention is to provide a semiconductor device and a method for forming the same, which can significantly improve the withstand voltage, make the electric field distribution more uniform, and have a wider range of applications.
[0006] To address the aforementioned problems, the present invention provides a semiconductor device comprising a substrate; an epitaxial layer structure located on the surface of the substrate; a first dielectric layer located on the surface of the epitaxial layer structure; and a gate embedded at the bottom in the first dielectric layer, wherein the bottom of the gate is in contact with the epitaxial layer structure, and the bottom dimension of the gate is smaller than the top dimension of the gate.
[0007] Optionally, the top surface of the gate is flush with the top surface of the first dielectric layer, or the top surface of the gate is higher than the top surface of the first dielectric layer.
[0008] Optionally, the cross-sectional shape of the gate is "T" shaped or inverted trapezoidal.
[0009] Optionally, it may further include: a second dielectric layer located on the surface of the first dielectric layer, the second dielectric layer covering the top surface of the gate.
[0010] Optionally, a conductive layer may also be included on the top surface of the gate.
[0011] Optionally, the epitaxial layer structure includes a buffer layer located on the surface of the substrate; a channel layer located on the surface of the buffer layer and a barrier layer located on the surface of the channel layer, wherein the first dielectric layer is located on the surface of the barrier layer.
[0012] Optionally, the channel layer is made of gallium nitride, and the barrier layer is made of aluminum gallium nitride.
[0013] Optionally, the gate material is P-type gallium nitride.
[0014] Optionally, it also includes a source and a drain, the source and the drain penetrating the second dielectric layer and the first dielectric layer and extending to the bottom into a portion of the epitaxial layer structure, with the gate located between the source and the drain.
[0015] The present invention also provides a method for forming a semiconductor device, comprising the steps of: providing a substrate; forming an epitaxial layer structure on the surface of the substrate; forming a first dielectric layer on the surface of the epitaxial layer structure; forming a gate in the first dielectric layer, wherein the bottom of the gate is in contact with the epitaxial layer structure, and the bottom dimension of the gate is smaller than the top dimension of the gate.
[0016] Optionally, the gate material is P-type gallium nitride.
[0017] Optionally, the cross-sectional shape of the gate is "T" shaped or inverted trapezoidal.
[0018] Optionally, the method for forming the gate includes: forming a first dielectric layer on the surface of the epitaxial layer structure; etching the first dielectric layer to form a gate opening that exposes a portion of the epitaxial layer structure; forming an initial gate layer in the gate opening and on the surface of the first dielectric layer; etching the initial gate layer to expose the surface of the first dielectric layer, and forming the gate in the gate opening.
[0019] Optionally, the top surface of the gate is flush with the top surface of the first dielectric layer, or the top surface of the gate is higher than the top surface of the first dielectric layer.
[0020] Optionally, a conductive layer may also be included on the top surface of the gate.
[0021] Optionally, the method for forming the conductive layer includes: forming an initial conductive layer on the surface of the first dielectric layer and the surface of the gate; etching the initial conductive layer to form the conductive layer on the top surface of the gate.
[0022] Optionally, the method for forming the epitaxial layer structure includes: forming a buffer layer on the surface of the substrate; forming a channel layer on the surface of the buffer layer; and forming a barrier layer on the surface of the channel layer.
[0023] Optionally, it also includes a source and a drain, the source and the drain penetrating the second dielectric layer and the first dielectric layer and extending to the bottom into a portion of the epitaxial layer structure, with the gate located between the source and the drain.
[0024] Optionally, the method for forming the source and the drain includes: forming a second dielectric layer on the surface of the first dielectric layer, the second dielectric layer covering the surface of the gate; etching the second dielectric layer, the first dielectric layer and the barrier layer to expose the corresponding channel layer to form a contact hole; and filling the contact hole with a conductive layer to form the source and the drain.
[0025] Optionally, before forming the conductive layer, an isolation region may be formed within the epitaxial layer structure.
[0026] Compared with the prior art, the technical solution of the present invention has the following advantages: In the semiconductor device of the present invention, the substrate has an epitaxial layer structure on its surface, a first dielectric layer is located on the surface of the epitaxial layer structure, the bottom of the gate is embedded in the first dielectric layer, the bottom of the gate is in contact with the surface of the epitaxial layer structure, and the bottom size of the gate is smaller than the top size of the gate. This "larger at the top and smaller at the bottom" gate can effectively disperse the electric field, making the electric field distribution more uniform around the gate and avoiding the concentration of the electric field at the edge of the gate, thereby improving the withstand voltage capability of the device. In addition, the bottom of the gate is embedded in the first dielectric layer, which can play the role of electric field shielding, reducing the concentration of the electric field in the contact area between the gate and the epitaxial layer structure, further improving the withstand voltage capability of the device. Attached Figure Description
[0027] Figures 1 to 11 This is a schematic diagram of the formation process of the semiconductor device according to the first embodiment of the present invention; Figure 12 This is a simulation diagram of the potential distribution and breakdown characteristics in the first embodiment of the present invention; Figures 13 to 14 This is a schematic diagram of the semiconductor device in the second embodiment of the present invention; Figure 15 This is a simulation diagram of the potential distribution and breakdown characteristics in the second embodiment of the present invention; Figure 16 This is the reverse breakdown characteristic curve. Detailed Implementation
[0028] The electrical performance of semiconductor devices in existing technologies still needs to be improved.
[0029] Based on this, the present invention provides a semiconductor device comprising: a substrate having an epitaxial layer structure on its surface, a first dielectric layer located on the surface of the epitaxial layer structure, a gate bottom embedded in the first dielectric layer, the gate bottom contacting the surface of the epitaxial layer structure, and the gate bottom dimension being smaller than the gate top dimension. This "larger at the top and smaller at the bottom" gate can effectively disperse the electric field, making the electric field distribution more uniform around the gate and avoiding the electric field concentration at the gate edge, thereby improving the device's withstand voltage capability. In addition, the gate bottom being embedded in the first dielectric layer can act as an electric field shield, reducing the concentration of the electric field in the contact area between the gate and the epitaxial layer structure, further improving the device's withstand voltage capability.
[0030] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0031] First Embodiment
[0032] First, please refer to Figure 1 Substrate 100 is provided.
[0033] In this embodiment, the substrate 100 is made of silicon.
[0034] In other embodiments, the substrate 100 may also be made of semiconductor materials such as silicon, germanium, etc.
[0035] Please continue to refer to this. Figure 1 An epitaxial layer structure 101 is formed on the surface of the substrate 100.
[0036] In this embodiment, the method for forming the epitaxial layer structure 101 includes: forming a buffer layer 101-1 on the surface of the substrate 100; forming a channel layer 101-2 on the surface of the buffer layer 101-1; and forming a barrier layer 101-3 on the surface of the channel layer 101-2.
[0037] In this embodiment, an aluminum nitride (AlN) nucleation layer is first grown on a silicon substrate 100 to alleviate the huge lattice mismatch and thermal mismatch problem between silicon and gallium nitride; then a stress-modulated buffer layer 101-1 composed of multiple layers of aluminum gallium nitride with different compositions is grown; next, a high-purity gallium nitride channel layer 101-2 is grown; and finally, a thin aluminum gallium nitride barrier layer 101-3 is grown.
[0038] Please refer to Figure 2 A first dielectric layer 102 is formed on the surface of the epitaxial layer structure 101.
[0039] In this embodiment, this layer primarily serves as surface passivation and electrical isolation, protecting the sensitive AlGaN barrier layer 101-3 surface beneath and isolating the subsequently formed gate metal from the source / drain regions. This step can be performed using plasma-enhanced chemical vapor deposition (PECVD), a method with lower temperatures that avoids damage to the already formed ohmic contacts. To obtain a denser dielectric layer with better coverage, high-density plasma-enhanced chemical vapor deposition (HDP-CVD) or atomic layer deposition (ALD) techniques can also be used.
[0040] In this embodiment, the material of the first dielectric layer 102 may be silicon nitride (SiN), which has excellent passivation effect and the ability to block water vapor and mobile ions; it may also be silicon oxide (SiO2); or a composite structure may be adopted, for example, first depositing a thin layer of silicon nitride as a passivation layer, and then depositing a thicker layer of silicon oxide as the main insulating layer.
[0041] A gate is formed within the first dielectric layer 102, the bottom of which contacts the epitaxial layer structure 101. The process of making the bottom dimension of the gate smaller than the top dimension of the gate is described in [reference needed]. Figures 3 to 5 .
[0042] Please refer to Figure 3 The first dielectric layer 102 is etched to form a gate opening 103 that exposes a portion of the epitaxial layer structure 101.
[0043] In this embodiment, the gate opening 103 is formed by wet etching.
[0044] In this embodiment, the top dimension of the gate opening 103 is larger than the bottom dimension of the gate opening 103.
[0045] In this embodiment, the gate opening 103 provides space for the formation of the gate.
[0046] Please refer to Figure 4 An initial gate layer 104 is formed within the gate opening 103 and on the surface of the first dielectric layer 102.
[0047] In this embodiment, the material of the initial gate layer 104 is P-type gallium nitride.
[0048] In this embodiment, the initial gate layer 104 is formed by metal-organic chemical vapor deposition.
[0049] Please refer to Figure 5 The initial gate layer 104 is etched to expose the surface of the first dielectric layer 102, and the gate 104-1 is formed in the gate opening 103.
[0050] In this embodiment, the top surface of the gate 104-1 is flush with the top surface of the first dielectric layer 102, and the bottom dimension of the gate 104-1 is smaller than the top dimension of the gate 104-1. Specifically, the cross-sectional shape of the gate 104-1 is an inverted trapezoid.
[0051] In this embodiment, the cross-section of the gate 104-1 is perpendicular to the surface of the substrate 100 and is located between the source and drain doped regions.
[0052] In this embodiment, the "larger at the top and smaller at the bottom" gate 104-1 can effectively disperse the electric field, making the electric field distribution more uniform around the gate 104-1 and avoiding the concentration of the electric field at the edge of the gate 104-1, thereby improving the device's withstand voltage capability. In addition, the bottom of the gate 104-1 is embedded in the first dielectric layer 102, which can act as an electric field shield, reducing the concentration of the electric field in the contact area between the gate 104-1 and the epitaxial layer structure 101, further improving the device's withstand voltage capability.
[0053] Please refer to Figure 6 An isolation region 105 is formed within the epitaxial layer structure 101.
[0054] In this embodiment, an isolation region 105 is formed in the epitaxial layer structure 101 by implanting ions. This implantation isolation step is used to form electrical isolation between different devices on the chip. Specifically, a mask can be formed by photolithography, and then inert ions such as nitrogen (N), argon (Ar) or fluorine (F) are implanted to destroy the lattice structure of the epitaxial layer structure 101 and form a high-resistance region, which effectively prevents current leakage and mutual interference between devices and ensures the normal function of the chip.
[0055] Please refer to Figure 7 An initial conductive layer 106 is formed on the surface of the first dielectric layer 102 and the surface of the gate 104-1.
[0056] In this embodiment, the material of the initial conductive layer 106 is titanium nitride.
[0057] In other embodiments, the material of the initial conductive layer 106 may also be tantalum nitride, hafnium oxide, palladium nitride, etc.
[0058] Please refer to Figure 8 The initial conductive layer 106 is etched to form the conductive layer 106-1 on the top surface of the gate 104-1.
[0059] In this embodiment, the conductive layer 106-1 is used to lead out the gate 104-1, thereby realizing the electrical connection between the gate 104-1 and the outside.
[0060] Please refer to Figure 9A second dielectric layer 107 is formed on the surface of the first dielectric layer 102, and the second dielectric layer 107 covers the surface of the gate 104-1.
[0061] In this embodiment, the material of the second dielectric layer 107 is silicon nitride.
[0062] Please refer to Figure 10 The second dielectric layer 107, the first dielectric layer 102, and the barrier layer 101-3 are etched to expose the corresponding channel layer 101-2, forming a contact hole 108.
[0063] Please refer to Figure 11 A conductive layer 106-1 is filled into the contact hole 108 to form the source electrode 109 and the drain electrode 110.
[0064] In this embodiment, the width dimensions of the source 109 and the drain 110 are Lsd, the bottom dimension of the gate 104-1 is Lg, the top dimension of the gate 104-1 is Lgm, the distance between the source 109 and the gate 104-1 is Lgs, and the distance between the drain 110 and the gate 104-1 is Lgd. The width dimensions of the source 109 and the drain 110, Ls / d, range from 0.5µm to 5.0µm. The bottom dimension of the gate 104-1, Lg, ranges from 0.5µm to 2.0µm. The distance between the source 109 and the gate 104-1, Lgs, ranges from 0.2µm to 5.0µm. The distance between the drain 110 and the gate 104-1, Lgd, ranges from 2µm to 25µm. The top dimension of the gate 104-1, Lgm, is greater than the bottom dimension of the gate 104-1, Lg.
[0065] In this embodiment, the bottom dimension of the gate 104-1 is smaller than the top dimension of the gate 104-1. This "larger at the top and smaller at the bottom" structure, when energized, forms a gate 104-1 field plate by extending the top of the gate 104-1 towards the source 109 and the drain 110. This extended gate 104-1 can disperse the electric field concentration at the edge of the gate 104-1, expand the depletion region, reduce the peak electric field strength, and improve the breakdown voltage of the device, thus having a wider range of applications.
[0066] Accordingly, the present invention also provides a semiconductor device, please refer to... Figure 11The device includes a substrate 100; an epitaxial layer structure 101 located on the surface of the substrate 100; a first dielectric layer 102 located on the surface of the epitaxial layer structure 101; and a gate 104-1 with its bottom embedded in the first dielectric layer 102, the bottom of the gate 104-1 being in contact with the epitaxial layer structure 101, and the bottom dimension of the gate 104-1 being smaller than the top dimension of the gate 104-1.
[0067] In this embodiment, the "larger at the top and smaller at the bottom" gate 104-1 can effectively disperse the electric field, making the electric field distribution more uniform around the gate 104-1 and avoiding the concentration of the electric field at the edge of the gate 104-1, thereby improving the device's withstand voltage capability. In addition, the bottom of the gate 104-1 is embedded in the first dielectric layer 102, which can act as an electric field shield, reducing the concentration of the electric field in the contact area between the gate 104-1 and the epitaxial layer structure 101, further improving the device's withstand voltage capability.
[0068] In this embodiment, the top surface of the gate 104-1 is flush with the top surface of the first dielectric layer 102.
[0069] In this embodiment, the cross-sectional shape of the gate 104-1 is an inverted trapezoid.
[0070] In this embodiment, a second dielectric layer 107 is also included, located on the surface of the first dielectric layer 102, the second dielectric layer 107 covering the top surface of the gate 104-1.
[0071] In this embodiment, a conductive layer 106-1 is also included on the top surface of the gate 104-1.
[0072] In this embodiment, the epitaxial layer structure 101 includes a buffer layer 101-1 located on the surface of the substrate 100; a channel layer 101-2 located on the surface of the buffer layer 101-1 and a barrier layer 101-3 located on the surface of the channel layer 101-2, and the first dielectric layer 102 is located on the surface of the barrier layer 101-3.
[0073] In this embodiment, the channel layer 101-2 is made of gallium nitride, and the barrier layer 101-3 is made of aluminum gallium nitride.
[0074] In this embodiment, the material of the gate 104-1 is P-type gallium nitride.
[0075] In this embodiment, a source 109 and a drain 110 are also included. The source 109 and the drain 110 penetrate the second dielectric layer 107 and the first dielectric layer 102 and extend to the bottom into a portion of the epitaxial layer structure 101. The gate 104-1 is located between the source 109 and the drain 110.
[0076] Second Embodiment
[0077] Please refer to the process from providing the substrate 100 to forming the opening 103 of the gate 104-1. Figures 1 to 3 .
[0078] Please refer to Figure 13 An initial gate layer 111 is formed within the gate opening 103 and on the surface of the first dielectric layer 102.
[0079] Please refer to Figure 14 The initial gate layer 111 is etched to expose the surface of the first dielectric layer 102, and the gate 111-1 is formed in the gate opening 103.
[0080] In this embodiment, the top surface of the gate 111-1 is higher than the top surface of the first dielectric layer 102.
[0081] For the process from forming the gate 111-1 to forming the source 109 and drain 110, please refer to [reference needed]. Figures 6 to 11 .
[0082] Accordingly, the present invention also provides a semiconductor device, including a substrate 100; an epitaxial layer structure 101 located on the surface of the substrate 100; a first dielectric layer 102 located on the surface of the epitaxial layer structure 101; and a gate 111-1 with its bottom embedded in the first dielectric layer 102, wherein the bottom of the gate 111-1 is in contact with the epitaxial layer structure 101, and the bottom dimension of the gate 111-1 is smaller than the top dimension of the gate 111-1.
[0083] In this embodiment, the top surface of the gate 111-1 is higher than the top surface of the first dielectric layer 102.
[0084] In this embodiment, the cross-sectional shape of the gate 111-1 is "T".
[0085] In this embodiment, a second dielectric layer 107 is also included, located on the surface of the first dielectric layer 102, the second dielectric layer 107 covering the top surface of the gate 111-1.
[0086] In this embodiment, a conductive layer 106-1 is also included on the top surface of the gate 111-1.
[0087] In this embodiment, the epitaxial layer structure 101 includes a buffer layer 101-1 located on the surface of the substrate 100; a channel layer 101-2 located on the surface of the buffer layer 101-1 and a barrier layer 101-3 located on the surface of the channel layer 101-2, and the first dielectric layer 102 is located on the surface of the barrier layer 101-3.
[0088] In this embodiment, the channel layer 101-2 is made of gallium nitride, and the barrier layer 101-3 is made of aluminum gallium nitride.
[0089] In this embodiment, the material of the gate 111-1 is P-type gallium nitride.
[0090] In this embodiment, a source 109 and a drain 110 are also included. The source 109 and the drain 110 penetrate the second dielectric layer 107 and the first dielectric layer 102 and extend to the bottom into a portion of the epitaxial layer structure 101. The gate 111-1 is located between the source 109 and the drain 110.
[0091] Now, a simulation comparison is performed on the comparative example, the first embodiment, and the second embodiment. The gate cross-section in the comparative example is rectangular or square. The dimensions of Lsd, Lg, Lgs, Lgd, and the gate in the comparative example, the first embodiment, and the second embodiment are shown in Table 1. Table 2 shows the simulation results.
[0092]
[0093] Table 1
[0094]
[0095] Table 2
[0096] Table 2 shows that, in terms of breakdown voltage (BV), the first embodiment is the best (561V), which is 3.3% higher than the comparative embodiment and 1.6% higher than the second embodiment, indicating that the first embodiment has a significant advantage in withstand voltage performance. In terms of off-state leakage current (Ioff), the first embodiment is the lowest (3.33E-13A), slightly better than the comparative embodiment (3.34E-13A), while the second embodiment is the highest (3.96E-13A), which is about 18.6% higher than the first embodiment and the comparative embodiment, indicating that the first embodiment and the comparative embodiment have better off-state leakage control, while the second embodiment has a larger leakage current. In terms of maximum drive current (Idmax), the comparative embodiment is the highest (0.966A), but the differences between the first embodiment, the second embodiment, and the comparative embodiment are very small (<1%), and the overall Idmax level is comparable, indicating that structural changes have no significant impact on the conduction current.
[0097] In summary, the first embodiment, the trapezoidal gate, offers the best overall performance: it achieves the highest breakdown voltage (561V) and the lowest off-state leakage current while maintaining almost the same drive current, making it suitable for high-voltage power device applications. The second embodiment, the T-gate structure, while having a higher breakdown voltage than the comparative example (BL), has a significantly higher off-state leakage current and may suffer from electric field concentration at the gate edge. The comparative example, the BL (planar gate) structure, is simple and has a slightly higher drive current, but its breakdown voltage is relatively weaker.
[0098] Combination Figure 12 and Figure 15 The trapezoidal gate (first embodiment) has the highest breakdown voltage (BV) and significantly better uniformity of electrostatic potential distribution. This is attributed to the trapezoidal ramp structure effectively reshaping the electric field at the gate edge, causing the equipotential lines to spread uniformly in a fan shape from the gate corner to the drift region, which alleviates the serious electric field concentration (dense aggregation of equipotential lines) problem at the right-angle edge of the T-type gate (second embodiment), thereby delaying the occurrence of avalanche breakdown.
[0099] Please refer to Figure 12 The trapezoidal gate (first embodiment) has the highest breakdown voltage (BV) and its electrostatic potential distribution uniformity is significantly better than that of the T-type gate. This is attributed to its ramp structure effectively reshaping the gate edge electric field through the Resurf effect, so that the equipotential lines spread out uniformly in a fan shape from the corner to the drift region, avoiding the severe electric field concentration caused by the right-angle structure. This structure disperses the high electric field region from the local cusp to a wider trapezoidal ramp, significantly reducing the peak electric field intensity and delaying the occurrence of avalanche breakdown. Therefore, it is particularly suitable for high-voltage power devices (>50V) and other applications with strict requirements for withstand voltage characteristics.
[0100] Please refer to Figure 15 The T-gate (second embodiment) achieves extremely low gate resistance (Rg) with its wide, laterally extended top structure, exhibiting superior noise figure and maximum oscillation frequency (fmax) in the millimeter-wave band. It combines the advantages of a short gate leg (below 100nm, increasing fT) and low parasitic resistance. At the same time, the T-gate process is simple and mature, requiring no complex steps such as tilting evaporation or CMP, resulting in low manufacturing cost and high yield. The top metal layer can also serve as an additional heat dissipation channel to reduce junction temperature, making it a preferred structure for high-frequency low-noise amplifiers (LNAs) and high-speed RF circuits.
[0101] Please refer to Figure 16The figure shows the reverse breakdown characteristics, indicating that the leakage current remains at a very low level (close to 0) under low bias voltage. When the voltage exceeds the critical value, the current rises sharply (avalanche breakdown). Among them, the breakdown point of the trapezoid-gate (first embodiment ①) is the far right and the breakdown voltage (BV) is the highest, while the breakdown voltage of the T-gate (second embodiment ②) is the lowest. This result is consistent with the optimal uniformity of the electric field of the trapezoid-gate in the potential distribution simulation.
[0102] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A semiconductor device, characterized in that, include: Substrate; The epitaxial layer structure located on the surface of the substrate; The first dielectric layer is located on the surface of the epitaxial layer structure; A gate is embedded in the first dielectric layer at the bottom, the bottom of the gate is in contact with the epitaxial layer structure, and the bottom dimension of the gate is smaller than the top dimension of the gate.
2. The semiconductor device according to claim 1, characterized in that, The top surface of the gate is flush with the top surface of the first dielectric layer, or the top surface of the gate is higher than the top surface of the first dielectric layer.
3. The semiconductor device according to claim 1, characterized in that, The cross-sectional shape of the gate is either "T" shaped or inverted trapezoidal.
4. The semiconductor device according to claim 1, characterized in that, Also includes: A second dielectric layer is located on the surface of the first dielectric layer, and the second dielectric layer covers the top surface of the gate.
5. The semiconductor device according to claim 1, characterized in that, It also includes a conductive layer located on the top surface of the gate.
6. The semiconductor device according to claim 1, characterized in that, The epitaxial layer structure includes a buffer layer located on the surface of the substrate; a channel layer located on the surface of the buffer layer and a barrier layer located on the surface of the channel layer, wherein the first dielectric layer is located on the surface of the barrier layer.
7. The semiconductor device according to claim 6, characterized in that, The channel layer is made of gallium nitride, and the barrier layer is made of aluminum gallium nitride.
8. The semiconductor device according to claim 1, characterized in that, The gate material is P-type gallium nitride.
9. The semiconductor device according to claim 4, characterized in that, It also includes a source and a drain, the source and the drain penetrating the second dielectric layer and the first dielectric layer and extending to the bottom into a portion of the epitaxial layer structure, and the gate is located between the source and the drain.
10. A method for forming a semiconductor device, characterized in that, Including the following steps: Provide substrate; An epitaxial layer structure is formed on the surface of the substrate; A first dielectric layer is formed on the surface of the epitaxial layer structure; A gate is formed within the first dielectric layer, the bottom of the gate being in contact with the epitaxial layer structure, and the bottom dimension of the gate being smaller than the top dimension of the gate.
11. The method for forming a semiconductor device according to claim 10, characterized in that, The gate material is P-type gallium nitride.
12. The method for forming a semiconductor device according to claim 10, characterized in that, The cross-sectional shape of the gate is either "T" shaped or inverted trapezoidal.
13. The method for forming a semiconductor device according to claim 10, characterized in that, The method for forming the gate includes: The first dielectric layer is formed on the surface of the epitaxial layer structure; The first dielectric layer is etched to form a gate opening that exposes a portion of the epitaxial layer structure; An initial gate layer is formed within the gate opening and on the surface of the first dielectric layer; The initial gate layer is etched to expose the surface of the first dielectric layer, and the gate is formed within the gate opening.
14. The method for forming a semiconductor device according to claim 13, characterized in that, The top surface of the gate is flush with the top surface of the first dielectric layer, or the top surface of the gate is higher than the top surface of the first dielectric layer.
15. The method for forming a semiconductor device according to claim 10, characterized in that, It also includes a conductive layer located on the top surface of the gate.
16. The method for forming a semiconductor device according to claim 15, characterized in that, The method for forming the conductive layer includes: An initial conductive layer is formed on the surface of the first dielectric layer and the surface of the gate; The initial conductive layer is etched to form the conductive layer on the top surface of the gate.
17. The method for forming a semiconductor device according to claim 10, characterized in that, The method for forming the epitaxial layer structure includes: A buffer layer is formed on the surface of the substrate; A channel layer is formed on the surface of the buffer layer; A barrier layer is formed on the surface of the channel layer.
18. The method for forming a semiconductor device according to claim 17, characterized in that, It also includes a source and a drain, the source and the drain extending through the first dielectric layer and extending to the bottom into a portion of the epitaxial layer structure, and the gate is located between the source and the drain.
19. The method for forming a semiconductor device according to claim 18, characterized in that, The method for forming the source and the drain includes: A second dielectric layer is formed on the surface of the first dielectric layer, and the second dielectric layer covers the surface of the gate. Etch the second dielectric layer, the first dielectric layer, and the barrier layer until the corresponding channel layer is exposed to form a contact hole; A conductive layer is filled into the contact hole to form the source and the drain.
20. The method for forming a semiconductor device according to claim 16, characterized in that, Before forming the conductive layer, an isolation region is also formed within the epitaxial layer structure.