Semiconductor device and preparation method thereof
By introducing a shielding portion into the junction field-effect transistor to form a new PN junction with the second doped region, the breakdown voltage and process complexity issues of the vertical junction field-effect transistor are solved, achieving higher breakdown voltage and lower process cost.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- PEKING UNIV
- Filing Date
- 2026-01-14
- Publication Date
- 2026-05-15
AI Technical Summary
Existing vertical junction field-effect transistors (VTFETs) exhibit high electric field accumulation near the source ohmic contact region during the turn-off breakdown voltage state, which affects the breakdown voltage and increases the complexity and cost of the manufacturing process.
In a junction field-effect transistor, a shielding region is introduced to form a new PN junction with a second doped region, modulating the electric field distribution in the channel region. The transistor is then formed by ion implantation using the same mask or in the same step, reducing process costs.
This improved the device's breakdown voltage, enhanced its electrical performance, and reduced process complexity and cost.
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Figure CN122054650A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and its fabrication method. Background Technology
[0002] Junction Field-Effect Transistor (JFET) is a relatively mature power electronic device that is used in high-temperature, high-power switching circuits.
[0003] Among junction field-effect transistors (JFETs), the vertical junction field-effect transistor (VJFET) is a widely used structure capable of achieving high power density. However, current VJFETs primarily utilize gate trench structures, resulting in higher cost and greater fabrication complexity. Furthermore, the breakdown voltage of VJFETs is affected by the accumulation of a high electric field near the source ohmic contact region during the device's turn-off breakdown state. Therefore, the electrical performance and fabrication methods of VJFETs still require further optimization. Summary of the Invention
[0004] This application provides a semiconductor device and its fabrication method, which can improve the breakdown voltage performance of junction field-effect transistors and has good process feasibility.
[0005] In a first aspect, embodiments of this application provide a semiconductor device including a substrate, a first doped region, a second doped region, and a shielding portion. An epitaxial layer is provided on one side of the substrate along its thickness direction. The first doped region extends toward the substrate along the surface of the epitaxial layer away from the substrate. The second doped region extends toward the substrate along the surface of the epitaxial layer away from the substrate. The second doped region has the opposite conductivity type to the first doped region. The first doped region and the second doped region are at least spaced apart along a first direction. The shielding portion is disposed on the side of the second doped region facing the substrate. The shielding portion has the opposite conductivity type to the second doped region. The orthographic projection of the second doped region on the substrate and the orthographic projection of the shielding portion on the substrate at least partially overlap.
[0006] In some alternative embodiments, the semiconductor device further includes a connection portion that has the same conductivity type as the shielding portion, and the shielding portion forms contact with the first doped region through the connection portion.
[0007] In some alternative embodiments, the shielding portion is continuously disposed along a second direction, which intersects with the first direction.
[0008] In some alternative embodiments, multiple connecting portions are spaced apart along the second direction.
[0009] In some alternative embodiments, the orthogonal projection of the shielding portion onto the substrate falls within the orthogonal projection range of the second doped region onto the substrate.
[0010] In some alternative embodiments, the size of the shield in the first direction is the same as the size of the second doped region in the first direction.
[0011] In some alternative embodiments, the connection is formed by extending the surface of the epitaxial layer away from the substrate toward the substrate.
[0012] Secondly, embodiments of this application provide a method for fabricating a semiconductor device, the method comprising: An epitaxial layer is grown on one side of the substrate along the thickness direction; Patterning is performed on the side of the epitaxial layer away from the substrate by first conductivity type ion implantation to form first doped regions spaced along a first direction, and a channel region is formed between two adjacent first doped regions; A first conductivity type ion implantation is performed on the side of the channel region away from the substrate to form a shielding region, and the shielding region and the first doped region are distributed alternately along a first direction; A first conductivity type ion implantation is performed on the side of the channel region away from the substrate to form a connection region. The shielding region has a connection region on at least one side along the first direction, and the shielding region forms contact with the first doped region through the connection region. At least one side of the shielding region away from the substrate is subjected to ion implantation of a second conductivity type to form a second doped region. The second doped region has the opposite conductivity type to the first doped region, and the size of the second doped region in the thickness direction is smaller than the size of the shielding region in the thickness direction.
[0013] In some optional embodiments, the first doped region, the shielding region, and the connecting region are formed simultaneously using a first mask, and the doping concentrations of the first doped region, the shielding region, and the connecting region are equal and their dimensions in the thickness direction are the same.
[0014] In some optional embodiments, the shielding region and the second doped region are formed sequentially using a second mask, and the orthogonal projection ranges of the shielding region and the second doped region on the substrate are the same.
[0015] The semiconductor device of this application embodiment adds a shielding portion to the side of the second doped region facing the substrate, which is used as a contact source. A new PN junction can be formed between the shielding portion and the second doped region. When the device is in the off-voltage state, this shielding portion modulates the depletion layer and electric field distribution inside the semiconductor device, alleviating the high electric field accumulation near the second doped region and improving the breakdown voltage of the device. Furthermore, since the shielding portion is located on the side of the second doped region facing the substrate, the shielding portion can be implanted and formed using the same mask as the second doped region, or it can be implanted and formed using a single ion implantation with the first doped region and the connection region, thereby reducing process costs and improving the process feasibility of the semiconductor device. Attached Figure Description
[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a top view schematic diagram of the semiconductor device according to some embodiments of this application; Figure 2 for Figure 1 A schematic diagram of a semiconductor device along section AA; Figure 3 for Figure 1 The diagram shows another structural schematic of the semiconductor device along section AA; Figure 4 for Figure 1 A schematic diagram of a semiconductor device along section BB; Figure 5 for Figure 1 Another schematic diagram of the semiconductor device shown along section AA; Figure 6 for Figure 1 Another schematic diagram of the semiconductor device shown along the BB section; Figure 7 for Figure 1 The diagram shows another structural schematic of the semiconductor device along section BB. Figure 8 This is a schematic diagram of the structure of a semiconductor device according to some embodiments of this application; Figure 9 for Figure 8 The diagram shows the structure of the semiconductor device along the CC section. Figures 10a to 10h This is a schematic diagram of the process structure of a semiconductor device fabrication method according to some embodiments of this application.
[0018] The accompanying drawings may not be drawn to scale.
[0019] The specific marking information in the attached diagram is as follows: 01. Source; 02. Drain; 03. Gate; 110. Substrate; 120. Epitaxial layer; 130. Current diffusion region; 200, First doped region; 210, Body region; 220, Gate contact region; 300, Second doped region; 410. Shielding part; 420. Connecting part; Thickness direction Z; First direction X; Second direction Y. Detailed Implementation
[0020] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.
[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.
[0022] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.
[0023] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0024] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.
[0025] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).
[0026] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.
[0027] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.
[0028] A junction field-effect transistor (JFET) is a voltage-controlled three-terminal unipolar semiconductor device whose channel width narrows or widens with changes in gate voltage to regulate the magnitude of source and drain current.
[0029] Junction field-effect transistors (JFETs) are widely used in radio frequency (RF) front-ends and various switching circuits due to their high input impedance, low noise, and low power consumption. JFET devices can be divided into two structural forms: planar and vertical. Vertical JFETs are more often used in high-power applications because they can withstand higher breakdown voltages.
[0030] However, the manufacturing process of vertical JFET devices is relatively difficult and costly; on the other hand, the electrical performance of vertical JFET devices still needs further optimization.
[0031] To address the problems of the prior art, this application provides a semiconductor device and its fabrication method, which can improve the breakdown voltage and stability of junction field-effect transistors and has good process feasibility. The semiconductor device provided in this application is described below.
[0032] Please see Figures 1 to 9 , Figure 1 This is a top view schematic diagram of the semiconductor device according to some embodiments of this application; Figure 2 for Figure 1 A schematic diagram of a semiconductor device along section AA; Figure 3 for Figure 1 The diagram shows another structural schematic of the semiconductor device along section AA; Figure 4 for Figure 1 A schematic diagram of a semiconductor device along section BB; Figure 5 for Figure 1 Another schematic diagram of the semiconductor device shown along section AA; Figure 6 for Figure 1 Another schematic diagram of the semiconductor device shown along the BB section; Figure 7 for Figure 1 The diagram shows another structural schematic of the semiconductor device along section BB. Figure 8 This is a schematic diagram of the structure of a semiconductor device according to some embodiments of this application; Figure 9 for Figure 8 The diagram shows the structure of the semiconductor device along the CC section.
[0033] In order to more clearly illustrate the structure of the semiconductor device provided in the embodiments of this application, Figure 1 and Figure 8 The top electrode, including the source and gate, has been omitted.
[0034] In a first aspect, embodiments of this application provide a semiconductor device including a substrate 110, a first doped region 200, a second doped region 300, and a shielding portion 410. An epitaxial layer 120 is provided on one side of the substrate 110 along the thickness direction Z. The first doped region 200 extends toward the substrate 110 along the surface of the epitaxial layer 120 away from the substrate 110. The second doped region 300 extends toward the substrate 110 along the surface of the epitaxial layer 120 away from the substrate 110. The second doped region 300 has an opposite conductivity type to the first doped region 200. The first doped region 200 and the second doped region 300 are at least spaced apart along a first direction X. The shielding portion 410 is disposed on the side of the second doped region 300 facing the substrate 110. The shielding portion 410 has an opposite conductivity type to the second doped region 300. The orthographic projection of the second doped region 300 on the substrate 110 and the orthographic projection of the shielding portion 410 on the substrate 110 at least partially overlap.
[0035] It is understood that the thickness direction Z refers to the thickness direction Z of the substrate 110. Specifically, the thickness direction Z is parallel to or overlaps with the stacking direction of the semiconductor device, and the thickness direction Z is perpendicular to the first direction X.
[0036] Optionally, the first doped region 200 and the shielding part 410 are P-type doped, and the second doped region 300 is N-type doped.
[0037] Optionally, the first doped region 200 and the shielding part 410 are N-type doped, and the second doped region 300 is P-type doped.
[0038] It is understood that the semiconductor device also includes a channel region located between the two first doped regions. Specifically, the first doped regions 200 with opposite conductivity types and the epitaxial layer 120 form depletion layers at the interface to both sides. The extent of the depletion layer changes with the change of the external voltage applied to the first doped region 200, thereby controlling the pinch-off or opening of the channel region and realizing the switching control function of the semiconductor device.
[0039] Optionally, the second doped region 300 has the same conductivity type as the epitaxial layer 120.
[0040] Further optionally, the ion doping concentration of the second doped region 300 is greater than the ion doping concentration of the epitaxial layer 120.
[0041] Optionally, the semiconductor device further includes a source 01, which is disposed on the side of the second doped region 300 facing away from the substrate 110. The source 01 and the second doped region 300 form an ohmic contact, and the orthogonal projection of the second doped region 300 on the substrate falls within the orthogonal projection range of the source 01 on the substrate 110.
[0042] Optionally, the semiconductor device further includes a gate 03, which is disposed on the side of the first doped region 200 facing away from the substrate 110. The gate 03 forms an ohmic contact with the first doped region 200, and the orthogonal projection of the gate 03 on the substrate 110 falls within the orthogonal projection range of the first doped region 200 on the substrate 110.
[0043] Optionally, the first doped region 200 includes a body region 210 and a gate contact region 220, with the gate contact region 220 disposed inside the body region 210, and the gate 03 forming an ohmic contact with at least the gate contact region 220.
[0044] Alternatively, the gate 03 may cover the gate contact region 220. Specifically, the orthogonal projection of the gate contact region 220 onto the substrate 110 falls within the orthogonal projection range of the gate 03 onto the substrate 110.
[0045] Alternatively, the ion doping concentration of the gate contact region 220 is greater than the ion doping concentration of the body region 210.
[0046] Alternatively, the size of the body region 210 in the thickness direction Z is larger than the size of the second doped region 300 in the thickness direction Z.
[0047] Optionally, the semiconductor device also includes a drain 02, which is disposed on the side of the substrate 110 away from the epitaxial layer 120.
[0048] According to the semiconductor device provided in the first aspect of this application, a new PN junction is introduced by adding a shielding portion 410 between the second doped region 300, which is used to form a contact with the source electrode 01, and the substrate 110. This modulates the off-state electric field of the channel region, suppresses the formation of electric field spikes, and improves the breakdown voltage of the semiconductor device. Furthermore, the shielding portion 410 located on the side of the second doped region 300 facing the substrate 110 can be implanted and formed using the same mask as the second doped region 300, or the shielding portion 410 can be implemented in the same ion implantation step as the body region 210 with the same conductivity type, thereby reducing process costs and improving the process feasibility of the semiconductor device.
[0049] According to some embodiments of the first aspect of this application, please refer to Figure 3 The semiconductor device also includes a current diffusion region 130, which has the same conductivity type as the epitaxial layer 120. The ion doping concentration of the current diffusion region 130 is higher than that of the epitaxial layer 120, and the ion doping concentration of the current diffusion region 130 is lower than that of the second doping region 300.
[0050] Specifically, the current diffusion region 130 is disposed between the second doped region 300 and the epitaxial layer 120 along the thickness direction Z. The current diffusion region 130 helps the current to be transmitted more evenly from the channel region to the entire epitaxial layer 120.
[0051] Optionally, the current diffusion region 130 is formed entirely on top of the epitaxial layer 120.
[0052] Optionally, the current diffusion region 130 is patterned on top of the epitaxial layer 120.
[0053] Further optionally, the orthogonal projection of the second doped region 300 on the substrate 110 falls within the orthogonal projection range of the current diffusion region 130 on the substrate 110, and the orthogonal projection of the current diffusion region 130 on the substrate 110 falls within the orthogonal projection range of the epitaxial layer 120 on the substrate 110.
[0054] Therefore, the current diffusion region 130 can alleviate the accumulation of on-state current in the region directly below the second doped region 300, thereby forming a wider carrier transport path and helping to reduce the on-resistance of the device.
[0055] According to some embodiments of the first aspect of this application, the orthographic projection of the second doped region 300 on the substrate 110 is axially symmetrical about the shielding portion 410 along the centerline of the first direction X.
[0056] Specifically, the centerline of the shielding part 410 along the first direction X refers to a virtual line that passes through the midpoint of the shielding part 410 in the first direction X and is perpendicular to the first direction X. This virtual line should be understood as extending infinitely.
[0057] As a result, the off-state electric field modulation effect of the shielding portion 410 on the channel region between the second doped region 300 and the substrate 110 is more uniform, and the improvement effect on the electrical performance of the semiconductor device is more stable.
[0058] According to some embodiments of the first aspect of this application, the semiconductor device further includes a connection portion 420 of the same conductivity type as the shielding portion 410, and the shielding portion 410 forms contact with the first doped region 200 through the connection portion 420.
[0059] Optionally, the connecting portion 420 is disposed on both sides of the shielding portion 410 along the first direction X.
[0060] Alternatively, the two connecting portions 420 located on both sides of the shielding portion 410 along the first direction X are arranged symmetrically about the shielding portion 410.
[0061] Optionally, the connecting portion 420 is disposed on one side of the shielding portion 410 along the first direction X, and the two ends of the connecting portion 420 along the first direction X are respectively connected to the shielding portion 410 and the body region 210 of the first doped region 200.
[0062] Thus, a new PN junction is formed between the shielding portion 410 and the second doped region 300 to modulate the electric field in the channel region. The shielding portion 410 can also form an electrical connection with the first doped region 200 through the connection portion 420 to transfer the net charge stored in the shielding portion 410 during the switching process in a timely manner, thereby avoiding the accumulation of net charge that causes the potential of the shielding portion 410 to drift, thereby improving the stability of the device.
[0063] According to some embodiments of the first aspect of this application, the shielding portion 410 is continuously disposed along the second direction Y, and the second direction Y intersects with the first direction X.
[0064] Optionally, the second direction Y is perpendicular to the first direction X and the second direction Y is perpendicular to the thickness direction Z.
[0065] Therefore, the shielding part 410 can form a uniform modulation effect along the second direction Y of the electric field of the entire semiconductor device, eliminate local electric field spikes, and improve the breakdown voltage of the semiconductor device.
[0066] According to some other embodiments of the first aspect of this application, the shielding portion 410 is provided with a plurality of portions spaced apart along the second direction Y.
[0067] Optionally, the shielding portion 410 is arranged at equal intervals along the second direction Y.
[0068] It is understandable that when the shielding parts 410 are spaced apart along the second direction Y, each shielding part 410 can make contact with the first doped region 200 through the connecting part 420.
[0069] According to some embodiments of the first aspect of this application, the connecting portion 420 is provided with a plurality of portions spaced apart along the second direction Y.
[0070] Optionally, multiple connection portions 420 are arranged at equal intervals along the second direction Y so that the off-state electric field in the channel region is uniformly distributed, and the net charge stored in the entire shield 410 during the switching process can be fully transferred to avoid the accumulation of net charge causing the potential of the shield to drift.
[0071] Optionally, each connecting part 420 has the same size in the second direction Y, or at least two connecting parts 420 have different sizes in the second direction Y.
[0072] Thus, the connection portion 420 can maintain the normal pinch-off or opening function of the channel region between the source and drain of the semiconductor device while maintaining the conductive contact between the shield portion 410 and the first doped region 200.
[0073] According to some embodiments of the first aspect of this application, along the thickness direction Z, the distance between the shielding portion 410 and the substrate 110 is greater than or equal to the distance between the first doped region 200 and the substrate 110.
[0074] Optionally, along the thickness direction Z, the minimum distance between the shielding portion 410 and the substrate 110 is greater than the maximum distance between the first doped region 200 and the substrate 110, so as to reduce the probability of the electric field accumulating at the bottom of the shielding portion 410 to form a new spike.
[0075] According to some embodiments of the first aspect of this application, the orthogonal projection of the shielding portion 410 on the substrate 110 falls within the orthogonal projection range of the second doped region 300 on the substrate 110.
[0076] Optionally, the size of the shielding portion 410 in the first direction X is the same as the size of the second doped region 300 in the first direction X.
[0077] Alternatively, the orthographic projection of the shielding portion 410 onto the substrate 110 is consistent with the orthographic projection range of the second doped region 300 onto the substrate 110. In other words, the shielding portion 410 and the second doped region 300 can be fabricated using the same mask, thereby reducing the process difficulty and manufacturing cost of semiconductor devices.
[0078] Thus, the size of the second doping region 300 in the first direction X covering the shielding portion 410 can, on the one hand, prevent the contact area between the second doping region 300 and the epitaxial layer 120 from being too small, resulting in too large on-resistance in the current path from the channel region to the second doping region 300; on the other hand, it can reduce the alignment accuracy requirements during the processing of the second doping region 300, contributing to controlling the production cost of semiconductor devices and optimizing the process feasibility of semiconductor devices.
[0079] According to some embodiments of the first aspect of the present application, the connecting portion 420 is formed by extending from the surface of the epitaxial layer 120 facing away from the substrate 110 towards the substrate 110, and the surface of the connecting portion 420 facing the substrate 110 is flush with the surface of the shielding portion 410 facing the substrate 110.
[0080] Optionally, the connecting portion 420 can be formed by the same ion implantation process as the shielding portion 410 to reduce the process complexity of the connecting portion 420 and the shielding portion 410.
[0081] Further optionally, the surface of the connecting portion 420 facing the substrate 110 is flush with the surface of the body region 210 facing the substrate 110, and the connecting portion 420 and the shielding portion 410 can be prepared simultaneously with the body region 210 to reduce the number of masks and further reduce the process cost and complexity.
[0082] Thus, it is convenient to form the connecting portion 420, further improving the process feasibility of semiconductor devices.
[0083] According to some other embodiments of the first aspect of the present application, please refer to Figure 7 , the connecting portion 420 is disposed inside the epitaxial layer 120. Specifically, the surface of the connecting portion 420 facing the substrate 110 is spaced apart from the substrate 110, and the surface of the connecting portion 420 facing away from the substrate 110 is spaced apart from the surface of the epitaxial layer 120 facing away from the substrate 110.
[0084] Please refer to Figure 8 and Figure 9 , according to some embodiments of the first aspect of the present application, the orthographic projection of the body region 210 of the semiconductor device on the substrate 110 is a closed figure, and the geometric center of the orthographic projection of the shielding portion 410 on the substrate 110 overlaps with the geometric center of the orthographic projection of the gate 03 on the substrate 110.
[0085] Optionally, there are multiple gate contact regions 220, and they are equally spaced along the circumferential direction of the body region 210.
[0086] Optionally, the orthographic projection of the body region 210 on the substrate 110 is a circular ring figure.
[0087] Optionally, the orthographic projection of the body region 210 on the substrate 110 is a "hui" character shape.
[0088] Optionally, the orthographic projection of the shielding portion 410 on the substrate 110 overlaps with the geometric center of the orthographic projection of the body region 210 on the substrate 110.
[0089] Optionally, the connecting portion 420 is sandwiched between the shielding portion 410 and the body region 210, along the direction from the geometric center of the orthogonal projection of the shielding portion 410 onto the substrate 110 to the body region 210.
[0090] Alternatively, multiple connecting portions 420 are provided, and the multiple connecting portions 420 are distributed at equal intervals along the circumference of the body region 210.
[0091] In one example, two connecting portions 420 are provided, which are respectively disposed on both sides of the shielding portion 410 along the first direction X, or the two connecting portions 420 are respectively disposed on both sides of the shielding portion 410 along the second direction Y.
[0092] In another example, four connection portions 420 are provided, with two connection portions 420 disposed on both sides of the shielding portion 410 along the first direction X, and the other two connection portions 420 disposed on both sides of the shielding portion 410 along the second direction Y. In other words, the four connection portions 420 are distributed in a cross shape between the shielding portion 410 and the first doped region 200.
[0093] Secondly, please refer to Figures 10a to 10h This application provides a method for fabricating a semiconductor device, the method comprising: S100, An epitaxial layer 120 is grown on one side of the substrate 110 along the thickness direction Z; S200: Patterning is performed on the side of the epitaxial layer 120 away from the substrate 110 by first conductivity type ion implantation to form a first doped region 200 spaced along the first direction X, and a channel region is formed between two adjacent first doped regions 200. S300, patterning is performed on the side of the channel region away from the substrate 110 by first conductivity type ion implantation to form a shielding region, and the shielding region and the first doped region 200 are staggered along the first direction X. S400, a first conductivity type ion implantation is performed on the side of the channel region away from the substrate 110 to form a connection region, and the shielding region is provided with a connection region on at least one side along the first direction, and the shielding region forms contact with the first doped region 200 through the connection region. S500, at least one side of the shielding region away from the substrate 110 is subjected to ion implantation of a second conductivity type to form a second doped region 300, the second doped region 300 having the opposite conductivity type to the first doped region 200.
[0094] Optionally, step S300 is performed before step S400.
[0095] Optionally, step S400 is performed before step S300.
[0096] Optionally, the shielding region is in contact with the first doped region 200 on one side along the first direction X through a connecting region.
[0097] Optionally, the shielding region is in contact with the first doped region 200 on both sides along the first direction X through the connecting region.
[0098] Optionally, multiple connection intervals are provided along the second direction Y.
[0099] Therefore, in the fabricated semiconductor device, the shielding region located below the second doped region 300 can modulate the off-state electric field in the semiconductor device, thereby improving the electrical performance of the semiconductor device, such as the breakdown voltage. Furthermore, the shielding region can form contact with the first doped region 200 through the connection region, promptly transferring the net charge stored in the shielding region during the switching process, preventing the accumulation of net charge from causing potential drift in the shielding region, and improving the stability of the device.
[0100] It is understood that the method for fabricating the semiconductor device provided in the second aspect of this application may also include source 01 metal deposition, gate 03 metal deposition, and drain 02 metal fabrication, etc., which will not be described in detail here.
[0101] According to some embodiments of the second aspect of this application, in step S500, ion implantation of a second conductivity type is performed on the side of the shielding region away from the substrate 110 to form a second doped region 300. The size of the second doped region 300 in the first direction X is the same as the size of the shielding region in the first direction X. The second doped region 300 can be fabricated using the mask of the shielding region in step S300 to reduce the process cost of semiconductor devices.
[0102] According to some embodiments of the second aspect of this application, in step S500, ion implantation of a second conductivity type is performed on the side of the shielding region away from the substrate 110 and the portion of the epitaxial layer 120 away from the substrate 110 to form a second doped region 300. The size of the second doped region 300 in the first direction X is larger than the size of the shielding region in the first direction X, and the second doped region 300 covers the shielding region.
[0103] According to some embodiments of the second aspect of this application, the preparation method further includes: S110. A current diffusion region 130 is formed on the side of the epitaxial layer 120 away from the substrate 110. The ion doping concentration of the current diffusion region 130 is higher than that of the epitaxial layer 120.
[0104] Specifically, the ion doping concentration of the current diffusion region 130 is less than that of the second doping region 300.
[0105] Optionally, in step S110, the current diffusion region 130 is formed entirely on top of the epitaxial layer 120 to reduce the difficulty of the process.
[0106] According to some embodiments of the second aspect of this application, steps S200, S300 and S400 are performed together.
[0107] Specifically, using a first mask, patterned first conductivity type ion implantation is performed on the side of the epitaxial layer away from the substrate to form a first doped region and a shielding region spaced apart along a first direction, and at least one connection region is formed between the first doped region and the shielding region.
[0108] It is understandable that, since the first doped region, the shielding region, and the connection region are formed simultaneously, their ion doping concentrations are equal. Furthermore, their dimensions in the thickness direction are the same; in other words, they are flush with the surface of the substrate.
[0109] According to some embodiments of the second aspect of this application, steps S300 and S500 are formed sequentially using the same photomask.
[0110] Optionally, step S300 is performed before step S500.
[0111] Specifically, both the shielding region and the second doped region are fabricated using a second mask, and the orthogonal projection range of the shielding region on the substrate is the same as the orthogonal projection range of the second doped region on the substrate.
[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.
Claims
1. A semiconductor device, characterized in that, include: A substrate, wherein an epitaxial layer is provided on one side of the substrate along the thickness direction; The first doped region extends toward the substrate along the surface of the epitaxial layer away from the substrate; The second doped region extends toward the substrate along the surface of the epitaxial layer away from the substrate. The second doped region has the opposite conductivity type to the first doped region. The first doped region and the second doped region are spaced apart at least along a first direction. A shielding portion is disposed on the side of the second doped region facing the substrate, and the conductivity type of the shielding portion is opposite to that of the second doped region; Wherein, the orthographic projection of the second doped region on the substrate and the orthographic projection of the shielding portion on the substrate at least partially overlap.
2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a connection portion, which has the same conductivity type as the shielding portion, and the shielding portion forms an electrical connection with the first doped region through the connection portion.
3. The semiconductor device according to claim 2, characterized in that, The shielding portion is continuously arranged along the second direction, which intersects with the first direction.
4. The semiconductor device according to claim 3, characterized in that, The connecting portion is provided at intervals along the second direction.
5. The semiconductor device according to claim 2, characterized in that, The orthogonal projection of the shielding portion onto the substrate falls within the orthogonal projection range of the second doped region onto the substrate.
6. The semiconductor device according to claim 5, characterized in that, The size of the shielding portion in the first direction is the same as the size of the second doped region in the first direction.
7. The semiconductor device according to claim 2, characterized in that, The connection portion is formed by extending the surface of the epitaxial layer away from the substrate toward the substrate.
8. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: An epitaxial layer is grown on one side of the substrate along the thickness direction; Patterning is performed on the side of the epitaxial layer away from the substrate by first conductivity type ion implantation to form first doped regions spaced along a first direction, and a channel region is formed between two adjacent first doped regions; A patterned first conductivity type ion implantation is performed on the side of the channel region away from the substrate to form a shielding region, the shielding region and the first doped region being distributed alternately along a first direction; A first conductivity type ion implantation is performed on the side of the channel region away from the substrate to form a connection region. The shielding region has the connection region on at least one side along a first direction. The shielding region forms contact with the first doped region through the connection region. At least one side of the shielding region away from the substrate is subjected to ion implantation of a second conductivity type to form a second doped region. The second doped region has the opposite conductivity type to the first doped region, and the size of the second doped region in the thickness direction is smaller than the size of the shielding region in the thickness direction.
9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The first doped region, the shielding region, and the connecting region are formed simultaneously using a first mask. The doping concentrations of the first doped region, the shielding region, and the connecting region are equal, and their dimensions in the thickness direction are the same.
10. The method for fabricating a semiconductor device according to claim 8, characterized in that, The shielding region and the second doped region are formed sequentially using a second mask, and the orthogonal projection ranges of the shielding region and the second doped region on the substrate are the same.