Semiconductor device

Abstract

The invention provides a semiconductor device. The semiconductor device comprises a substrate, an epitaxial layer, an isolation structure and a field oxide layer. The substrate has a first conductivity type. The epitaxial layer has a second conductivity type different from the first conductivity type, and is disposed on the substrate. The isolation structure has a first conductivity type and is disposed in the epitaxial layer. The isolation structure comprises a first well, a second well and a doped region arranged between the first well and the second well. The field oxide layer is disposed on the epitaxial layer. Wherein the field oxide layer exposes the top surface of the epitaxial layer between the first well and the doped region or exposes the top surface of the epitaxial layer between the second well and the doped region.

Description

Technical Field

[0001] This invention relates to semiconductor devices, and more particularly to semiconductor devices comprising a field oxide layer having a specific pattern. Background Technology

[0002] Current high-voltage integrated circuits (HVICs) can drive high-current devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), and are therefore frequently used in motor drives, power supply control, and other fields. Generally, an HVIC consists of a high-voltage circuit located in the high-voltage region and a low-voltage circuit located in the low-voltage region, connected by a level shifter. Furthermore, an isolation structure is included between the high-voltage circuit and the level shifter to separate the different voltages.

[0003] However, in HVICs, the doping profile of components affects the electrical isolation characteristics of the isolation structure, thus impacting the reliability of the HVIC. Therefore, although existing semiconductor devices have gradually met their intended applications, they are not yet completely satisfactory in all aspects. Consequently, some issues regarding semiconductor devices still need to be overcome. Summary of the Invention

[0004] The semiconductor device disclosed herein may include an isolation structure and a field oxide layer, wherein the isolation structure may include a first well, a second well, and a doped region located between the two. The field oxide layer may expose the top surface of the epitaxial layer located between the first well and the doped region, or expose the top surface of the epitaxial layer located between the second well and the doped region. Therefore, unnecessary diffusion of dopants can be avoided, which could lead to electrical degradation of the semiconductor device. Accordingly, the semiconductor device disclosed herein has an improved doping profile, thereby enhancing punch-through capability and / or reliability.

[0005] In some embodiments, this disclosure provides a semiconductor device. The semiconductor device includes a substrate, an epitaxial layer, an isolation structure, and a field oxide layer. The substrate has a first conductivity type. The epitaxial layer has a second conductivity type different from the first conductivity type and is disposed on the substrate. The isolation structure has a first conductivity type and is disposed in the epitaxial layer. The isolation structure includes a first well, a second well, and a doped region disposed between the first well and the second well. The field oxide layer is disposed on the epitaxial layer. The field oxide layer exposes either the top surface of the epitaxial layer located between the first well and the doped region or the top surface of the epitaxial layer located between the second well and the doped region.

[0006] The semiconductor device disclosed herein can be applied to various types of electronic devices and methods of forming thereof. To make the components and advantages of this disclosure more apparent and understandable, various embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0007] This disclosure will be more fully understood when read in conjunction with the drawings, as detailed in the following description. It is important to note that, in accordance with industry standard practice, the components are not drawn to scale. In fact, for clarity, the dimensions of the components may be arbitrarily enlarged or reduced.

[0008] Figure 1 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 3 This is a top view schematic diagram of a region of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 These are schematic cross-sectional views of a semiconductor device according to an embodiment of the present disclosure.

[0012] Symbol Explanation

[0013] 1,2,3,4,5,6: Semiconductor devices

[0014] 100:Substrate

[0015] 102, 104: First buried layer

[0016] 106, 108: Second burial layer

[0017] 110: Epitaxial layer

[0018] 112: Deep Trap

[0019] 114: High-pressure trap

[0020] 122: First Trap

[0021] 123: First Active Zone

[0022] 124: Second Trap

[0023] 125: Second Active Zone

[0024] 126: Doped region

[0025] 200, 200a, 200b, 200c, 200d, 200e, 200f: Field oxide layer

[0026] 210: Gate dielectric layer

[0027] 220: Gate electrode

[0028] 302, 304, 306, 308: Trap

[0029] 312, 314, 316: Doped regions

[0030] 400: First interlayer dielectric layer

[0031] 410: First metal layer

[0032] 500: Second interlayer dielectric layer

[0033] 510: Second metal layer

[0034] A-A': Line segment

[0035] D1: First Direction

[0036] D2: Second Direction

[0037] D3: Third direction

[0038] HS: High-end circuitry

[0039] HVJT: High Voltage Junction Terminal

[0040] ISO: Isolation Structure

[0041] NLS: Potentiometer

[0042] LS: Low-end circuit

[0043] R1: First Region Detailed Implementation

[0044] The semiconductor devices of various embodiments of this disclosure are described in detail below. It should be understood that the following description provides many different embodiments for implementing various forms of some embodiments of this disclosure. The specific elements and arrangements described below are merely for simple and clear description of some embodiments of this disclosure. Of course, these are only examples and not limitations of this disclosure. Furthermore, similar and / or corresponding element symbols may be used in different embodiments to identify similar and / or corresponding elements for clear description of this disclosure. However, the use of these similar and / or corresponding element symbols is only for simple and clear description of some embodiments of this disclosure and does not represent any association between the different embodiments and / or structures discussed.

[0045] It should be understood that relative terms, such as "lower," "bottom," "higher," or "top," may be used in various embodiments to describe the relative relationship of one element to another in the diagram. It is understood that if the arrangement in the diagram is flipped upside down, an element depicted on the "lower" side will become an element on the "higher" side. The embodiments disclosed herein should be understood in conjunction with the drawings, which are also considered part of the disclosure.

[0046] Furthermore, when it is stated that a first material layer is on or over a second material layer, this may include situations where the first material layer and the second material layer are in direct contact, or situations where the first material layer and the second material layer are not in direct contact, that is, situations where there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is directly on the second material layer, it indicates that the first material layer and the second material layer are in direct contact.

[0047] Furthermore, it should be understood that the ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify elements, are not intended to imply any prior ordinal number for the element (or the plurality of elements), nor to indicate the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another with the same name. The claims and specification may not use the same terminology; for example, a first element in the specification may be a second element in the claims.

[0048] In some embodiments disclosed herein, terms such as "connect," "interconnect," and "bond," unless specifically defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, with other structures disposed between them. Furthermore, these terms may include situations where both structures are movable or both structures are fixed. Additionally, the terms "electrical connection" or "electrical coupling" include any direct or indirect electrical connection means.

[0049] In this text, the terms "approximately," "about," and "substantially" typically indicate that a given value or range is within 10%, 5%, 3%, 2%, 1%, or 0.5%. The given quantity is an approximate quantity; that is, even without specific mention of "approximately," "about," or "substantially," the meaning of "approximately," "about," or "substantially" is implied. The phrases "the range is between the first value and the second value" or "the first value to the second value" indicate that the range includes the first value, the second value, and other values ​​in between. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies that there may be an error between the first and second values ​​within approximately 10%, 5%, 3%, 2%, 1%, or 0.5%.

[0050] Throughout this disclosure, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names. In the following description and claims, words such as "comprise" and "having" are open-ended terms and should therefore be interpreted as "including but not limited to...". Thus, when the terms "comprise" and / or "having" are used in the description of this disclosure, they specify the presence of the corresponding component, area, step, operation, and / or element, but do not exclude the presence of one or more of the corresponding component, area, step, operation, and / or element.

[0051] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art. It is understood that such terms, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0052] In this disclosure, the directions are not limited to the three axes of a Cartesian coordinate system such as the X, Y, and Z axes, and can be interpreted in a broader sense. For example, the X, Y, and Z axes may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of explanation, in the following text, the X-axis direction is the first direction D1 (width direction), the Y-axis direction is the second direction D2 (length direction), and the Z-axis direction is the third direction D3 (thickness / height direction). In some embodiments, the cross-sectional view described herein is a schematic diagram of viewing the XY plane, and the top view described herein is a schematic diagram of viewing the XY plane. In some embodiments, the normal direction of the substrate described herein is the third direction D3.

[0053] Reference Figure 1 This is a schematic cross-sectional view of a semiconductor device 1 according to an embodiment of the present disclosure. In some embodiments, a substrate 100 may be provided, and the substrate 100 may have a first conductivity type. In some embodiments, the substrate 100 may include a wafer, such as a silicon wafer. In some embodiments, the substrate 100 may include a bulk semiconductor or a semiconductor-on-insulator (SOI) substrate. Generally, an SOI substrate may include a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like, to provide an insulating layer on a silicon or glass substrate. In some embodiments, the substrate may include a multilayer substrate or a gradient substrate. In some embodiments, substrate 100 may include elemental semiconductors, including silicon, germanium, the like, or combinations thereof; substrate 100 may include compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, the like, or combinations thereof; substrate 100 may include alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, the like, or combinations thereof, but this disclosure is not limited thereto.

[0054] like Figure 1As shown, in some embodiments, first buried layers 102 and 104 may be formed in the substrate 100, and the first buried layers 102 and 104 may have a first conductivity type. In some embodiments, second buried layers 106 and 108 may be formed in the substrate 100, and the second buried layers 106 and 108 may have a second conductivity type different from the first conductivity type. In some embodiments, the first buried layers 102 and 104 and the second buried layers 106 and 108 may be formed by doping processes such as ion implantation, diffusion, drive-in, similar processes, or combinations thereof, but this disclosure is not limited thereto. In addition, the implanted dopants may be further activated by a rapid thermal annealing (RTA) process. In some embodiments, in the first direction D1, the first buried layers 102 and 104 may be disposed between the second buried layers 106 and 108.

[0055] In some embodiments, the first conductivity type and the second conductivity type can be adjusted according to electrical requirements. In some embodiments, the doping concentration, doping depth, and size of the doped region can also be adjusted according to electrical requirements. In some embodiments, the first conductivity type can be either P-type or N-type, and the second conductivity type can be either P-type or N-type. For ease of explanation, in the following text, the first conductivity type can be P-type, and the second conductivity type can be N-type, but this disclosure is not limited thereto. In other words, the substrate 100 and the first buried layers 102 and 104 can be P-type, and the second buried layers 106 and 108 can be N-type.

[0056] like Figure 1 As shown, in some embodiments, an epitaxial layer 110 may be formed on the substrate 100, and the epitaxial layer 110 may have a second conductivity type, i.e., N-type. In some embodiments, the epitaxial layer 110 may be formed on the first buried layers 102, 104 and the second buried layers 106, 108. In some embodiments, the doping concentration of the second buried layers 106, 108 may be greater than the doping concentration of the epitaxial layer 110. In some embodiments, the doping profile of the first buried layers 102, 104 and the second buried layers 106, 108 may be changed by performing the aforementioned diffusion process, thermal ingress process and / or rapid thermal annealing process. Therefore, the first buried layers 102, 104 and the second buried layers 106, 108 may be respectively disposed between the substrate 100 and the epitaxial layer 110.

[0057] like Figure 1As shown, in some embodiments, a deep well 112 having a second conductivity type, i.e., N-type, can be formed in the epitaxial layer 110. In some embodiments, the deep well 112 can be formed by performing the aforementioned doping process, but this disclosure is not limited thereto. In some embodiments, the doping concentration of the deep well 112 can be greater than the doping concentration of the epitaxial layer 110. In some embodiments, in the first direction D1, the deep well 112 can be disposed between the first buried layer 104 and the second buried layer 108. In some embodiments, the deep well 112 can directly contact the substrate 100. In some embodiments, a high-voltage well 114 having a first conductivity type, i.e., P-type, can be formed in the epitaxial layer 110. In some embodiments, the high-voltage well 114 can be formed by performing the aforementioned doping process, but this disclosure is not limited thereto. In some embodiments, in the first direction D1, the second buried layer 106 can be disposed between the high-voltage well 114 and the first buried layer 102. In some embodiments, the high-voltage well 114 can directly contact the substrate 100.

[0058] like Figure 1 As shown, in some embodiments, a first well 122 and a second well 124 having a first conductivity type, i.e., P-type, may be formed in the epitaxial layer 110. In some embodiments, the first well 122 and the second well 124 may be formed by performing the aforementioned doping process, but this disclosure is not limited thereto. In some embodiments, a first buried layer 102 may be disposed below the first well 122, and a first buried layer 104 may be disposed below the second well 124. In some embodiments, the projection range of the first buried layer 102 onto the substrate 100 may be substantially the same as the projection range of the first well 122 onto the substrate 100. In some embodiments, the projection range of the first buried layer 104 onto the substrate 100 may be substantially the same as the projection range of the second well 124 onto the substrate 100. In some embodiments, the doping concentration of the first well 122 and the second well 124 may be less than the doping concentration of the first buried layers 102 and 104. In some embodiments, the first well 122 and the first buried layer 102 can serve as a first P-type isolation ring, and the second well 124 and the first buried layer 104 can serve as a second P-type isolation ring. Therefore, the semiconductor device 1 can have a double-layer isolation ring. In other embodiments (not shown), the first buried layer 104 and the second well 124 can be omitted, resulting in a single-layer isolation ring for the semiconductor device. In other embodiments (not shown), additional buried layers and other wells can be provided, resulting in a multi-layer isolation ring with more than two layers for the semiconductor device.

[0059] like Figure 1As shown, in some embodiments, a doped region 126 having a first conductivity type, i.e., P-type, may be formed in the epitaxial layer 110. In some embodiments, in the first direction D1, the doped region 126 may be disposed between the first well 122 and the second well 124. In some embodiments, in the first direction D1, the doped region 126 may be spaced apart from the first well 122 by a distance, and the doped region 126 may be spaced apart from the second well 124 by a distance. In some embodiments, the first buried layers 102, 104, the first well 122, the second well 124, and the doped region 126 may be collectively referred to as the isolation structure ISO.

[0060] like Figure 1 As shown, in some embodiments, a field oxide layer 200 may be formed on the epitaxial layer 110. In some embodiments, the field oxide layer 200 may be formed by performing a thermal process, chemical vapor deposition (CVD), similar processes, or a combination thereof, but this disclosure is not limited thereto. In some embodiments, the field oxide layer 200 may include an oxide such as silicon oxide, but this disclosure is not limited thereto. In some embodiments, the field oxide layer 200 may at least partially expose the top surface of the epitaxial layer 110 located between the first well 122 and the doped region 126 and / or may at least partially expose the top surface of the epitaxial layer 110 located between the second well 124 and the doped region 126. For example, the field oxide layer 200 may at least partially or completely expose the top surface of the epitaxial layer 110 located between the first well 122 and the doped region 126. For example, the field oxide layer 200 may at least partially or completely expose the top surface of the epitaxial layer 110 located between the second well 124 and the doped region 126. In some embodiments, the term "at least partially exposed" means that the exposed area represents at least 10%, 25%, 50%, 75%, 99%, 100% of the total area, or any value or range of values ​​between the foregoing, but this disclosure is not limited thereto. For example, the field oxide layer 200 may at least partially expose 10%, 25%, 50%, 75%, 99%, or 100% of the top surface of the epitaxial layer 110 located between the first well 122 and the doped region 126 (i.e., the area exposed by the field oxide layer 200 / the area of ​​the top surface of the epitaxial layer 110 located between the first well 122 and the doped region 126).

[0061] like Figure 1As shown, in some embodiments, the right edge of the field oxide layer 200d may be flush with the right edge of the first well 122. In some embodiments, the projection range of the first well 122 onto the substrate 100 may be within the projection range of the field oxide layer 200d onto the substrate 100. In some embodiments, the left edge of the field oxide layer 200f may be flush with the left edge of the second well 124. In some embodiments, the projection range of the second well 124 onto the substrate 100 may be within the projection range of the field oxide layer 200f onto the substrate 100. In some embodiments, the right edge of the field oxide layer 200e may be flush with the right edge of the doped region 126, and the left edge of the field oxide layer 200e may be flush with the left edge of the doped region 126. In some embodiments, the field oxide layer 200e may cover the top surface of the doped region 126. In some embodiments, the projection range of the doped region 126 onto the substrate 100 may be substantially the same as the projection range of the field oxide layer 200e onto the substrate 100.

[0062] like Figure 1 As shown, in some embodiments, the epitaxial layer 110 on which the field oxide layer 200 is disposed can be defined as a non-active region, and the epitaxial layer 110 on which the field oxide layer 200 is not disposed can be defined as an active region. In other words, the first active region 123 may be located between the first well 122 and the doped region 126, and the second active region 125 may be located between the second well 124 and the doped region 126. Accordingly, this disclosure additionally provides active regions by adjusting the placement of the field oxide layer 200, thereby giving the semiconductor device an improved doping profile, thereby improving breakdown resistance and / or reliability.

[0063] Typically, at the silicon oxide-to-silicon interface, the dopants used in the doping process to form the first well 122, the second well 124, and / or the doped region 126 (e.g., P-type dopants, such as boron (B)) tend to diffuse more into the silicon oxide (i.e., away from the silicon surface), resulting in a relatively N-type silicon surface. Similarly, at the interface between the field oxide layer 200 and the epitaxial layer 110, boron tends to diffuse more into the field oxide layer 200 (and away from the top surface of the epitaxial layer 110), resulting in a relatively N-type top surface of the epitaxial layer 110. Therefore, relatively N-type regions may be generated at the silicon oxide-to-silicon interfaces (field oxide layer 200-epitaxy layer 110) between the first well 122 and the doped region 126 and / or between the second well 124 and the doped region 126. In other words, in the isolation structure ISO adjacent to the P-type region, an unnecessary N-type region may locally exist on the top surface of the epitaxial layer 110, which degrades the isolation characteristics of the P-type isolation structure ISO. This, in turn, reduces the breakdown capability of the semiconductor device 1.

[0064] However, since the field oxide layer 200 disclosed herein exposes (does not cover) the top surface of the epitaxial layer 110 between the first well 122 and the doped region 126 and / or between the second well 124 and the doped region 126, dopants such as boron can be prevented from migrating into the field oxide layer 200, thereby preventing the formation of local N-type regions on the top surface of the epitaxial layer 110 between the first well 122 and the doped region 126 and / or between the second well 124 and the doped region 126. Therefore, the adjacent isolation structure ISO can be substantially maintained as P-type, thereby improving the breakdown resistance and / or reliability of the semiconductor device 1.

[0065] like Figure 1 As shown, in some embodiments, a gate dielectric layer 210 may be formed on the high-voltage well 114. In some embodiments, the gate dielectric layer 210 may be formed by a chemical vapor deposition (CVD) process. In some embodiments, the gate dielectric layer 210 may include a dielectric material with a high dielectric constant. In some embodiments, the gate dielectric layer 210 may include an oxide such as silicon oxide, but this disclosure is not limited thereto. In some embodiments, a gate electrode 220 may be formed on the gate dielectric layer 210. In some embodiments, the gate electrode 220 may be formed by a sputtering process, a chemical vapor deposition (CVD) process, a resistance heating evaporation process, an electron beam evaporation process, a similar process, or a combination thereof, but this disclosure is not limited thereto. In some embodiments, the gate electrode 220 may include a conductive material. In some embodiments, the conductive material may include amorphous silicon, polysilicon, a metal, a metal nitride, a conductive metal oxide, the like, or a combination thereof, but this disclosure is not limited thereto. The metal may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), their analogues or combinations thereof, but this disclosure is not limited thereto.

[0066] like Figure 1As shown, in some embodiments, wells 302, 304, and 306 having a second conductivity type, i.e., N-type, can be formed. In some embodiments, wells 302, 304, and 306 can be formed by performing the aforementioned doping process, but this disclosure is not limited thereto. In some embodiments, well 302 can be disposed in a deep well 112, and the doping concentration of well 302 can be greater than the doping concentration of deep well 112. In some embodiments, well 304 can be located between wells 302 and well 306 in the first direction D1. In some embodiments, well 304 can be disposed in the epitaxial layer 110. In some embodiments, an isolation structure ISO can be disposed between wells 302 and well 304 in the first direction D1. In some embodiments, well 306 can be disposed in a high-voltage well 114. In some embodiments, well 308 having a first conductivity type, i.e., P-type, can be formed. In some embodiments, well 308 can be formed by performing the aforementioned doping process, but this disclosure is not limited thereto. In some embodiments, the trap 308 may be disposed in the high-pressure trap 114, and the trap 308 may be adjacent to and in contact with the trap 306.

[0067] like Figure 1 As shown, in some embodiments, doped regions 312 and 314 having a second conductivity type, i.e., N-type, can be formed. In some embodiments, doped regions 312 and 314 can be formed by performing the aforementioned doping process, but this disclosure is not limited thereto. In some embodiments, doped region 312 can be disposed in well 304, and the doping concentration of doped region 312 can be greater than the doping concentration of well 304. In some embodiments, doped region 314 can be disposed in well 306, and the doping concentration of doped region 314 can be greater than the doping concentration of well 306. In some embodiments, doped region 316 having a first conductivity type, i.e., P-type, can be formed. In some embodiments, doped region 316 can be formed by performing the aforementioned doping process, but this disclosure is not limited thereto. In some embodiments, doped region 316 can be disposed in well 308, and the doping concentration of doped region 316 can be greater than the doping concentration of well 308.

[0068] like Figure 1As shown, in some embodiments, a first interlayer dielectric layer 400 may be formed on the field oxide layer 200. In some embodiments, the first interlayer dielectric layer 400 may be formed by chemical vapor deposition (CVD), similar processes, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the first interlayer dielectric layer 400 may include oxides such as silicon oxide, nitrides such as silicon nitride, oxide oxynitrides such as silicon oxynitride, similar substances, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the first interlayer dielectric layer 400 may directly contact the top surface of the epitaxial layer 110 between the first well 122 and the doped region 126, and may directly contact the top surface of the epitaxial layer 110 between the second well 124 and the doped region 126. In some embodiments, the first interlayer dielectric layer 400 may directly contact the first active region 123 and the second active region 125.

[0069] like Figure 1 As shown, in some embodiments, a first metal layer 410 may be formed on and within the first interlayer dielectric layer 400. In some embodiments, the first metal layer 410 may include the aforementioned conductive material. In some embodiments, the first metal layer 410 may be electrically connected to doped regions 312, 314, and 316. Doped region 312 may serve as a drain doped region, and doped region 314 may serve as a source doped region.

[0070] like Figure 1 As shown, in some embodiments, a second interlayer dielectric layer 500 may be formed on the first metal layer 410 and the first interlayer dielectric layer 400. In some embodiments, the material and formation method of the second interlayer dielectric layer 500 may be the same as or different from the material and formation method of the first interlayer dielectric layer 400. In some embodiments, a second metal layer 510 may be formed on and within the second interlayer dielectric layer 500. In some embodiments, the material and formation method of the second metal layer 510 may be the same as or different from the material and formation method of the first metal layer 410. Thus, a semiconductor device 1 can be obtained. In some embodiments, the semiconductor device 1 may be a high voltage integrated circuit (HVIC), or further processes may be performed on the semiconductor device 1 to form an HVIC.

[0071] Reference Figure 2 This is a top view schematic diagram of a semiconductor device 1 according to an embodiment of the present disclosure. Figure 1 Show along Figure 2The diagram shows a cross-sectional view taken from line segment A-A'. In some embodiments, the semiconductor device 1 may include a high-side circuit HS and a low-side circuit LS. In some embodiments, the high-side circuit HS is floated at a high voltage potential, and the lowest potential of the low-side circuit LS is ground potential. In some embodiments, a high-voltage junction terminal HVJT may be disposed between the high-side circuit HS and the low-side circuit LS, and the high-voltage junction terminal HVJT may surround the high-side circuit HS, so that the floating high voltage potential of the high-side circuit HS can be reduced to ground potential through the high-voltage junction terminal HVJT. In some embodiments, a potential converter NLS may be disposed between the high-side circuit HS and the low-side circuit LS to realize the function of potential conversion. In some embodiments, the potential converter NLS may be disposed in the high-voltage junction terminal HVJT to integrate the potential converter NLS and the high-voltage junction terminal HVJT. In some embodiments, an isolation structure ISO may be disposed between the high-side circuit HS and the potential converter NLS to electrically isolate the potential converter NLS. Accordingly, this disclosure improves the electrical isolation characteristics of the isolation structure ISO by adjusting the placement position of the field oxide layer (i.e., the pattern of the field oxide layer) adjacent to the isolation structure ISO, thereby improving the breakdown resistance and / or reliability.

[0072] Reference Figure 3 This is a top view of a first region R1 of a semiconductor device 1 according to an embodiment of the present disclosure. In some embodiments, a first active region 123 may be located between a first well 122 and a doped region 126. In some embodiments, a second active region 125 may be located between a second well 124 and a doped region 126. The first active region 123 and the second active region 125 may correspond to locations where no field oxide layer 200 is disposed. In some embodiments, the shapes of the first active region 123 and the second active region 125 may correspond to the shape of an isolation structure ISO. In some embodiments, the first active region 123 and the second active region 125 may each have an inverted U-shaped shape.

[0073] Reference Figure 4 This is a cross-sectional schematic diagram of a semiconductor device 2 according to an embodiment of the present disclosure. In some embodiments, the field oxide layer 200 may expose the top surface of the epitaxial layer 110 between the first well 122 and the doped region 126, and may cover the top surface of the epitaxial layer 110 between the second well 124 and the doped region 126. In some embodiments, the right edge of the field oxide layer 200d may be flush with the right edge of the first well 122. In some embodiments, the left edge of the field oxide layer 200e may be flush with the left edge of the doped region 126.

[0074] Reference Figure 5This is a cross-sectional schematic diagram of a semiconductor device 3 according to an embodiment of the present disclosure. In some embodiments, the field oxide layer 200 may cover the top surface of the epitaxial layer 110 between the first well 122 and the doped region 126, and may expose the top surface of the epitaxial layer 110 between the second well 124 and the doped region 126. In some embodiments, the right edge of the field oxide layer 200d may be flush with the right edge of the doped region 126. In some embodiments, the left edge of the field oxide layer 200e may be flush with the left edge of the second well 124. Compared to semiconductor devices 2 and 3, semiconductor device 1 has a higher breakdown voltage and thus higher breakdown resistance.

[0075] Reference Figure 6 This is a cross-sectional schematic diagram of a semiconductor device 4 according to an embodiment of the present disclosure. In some embodiments, the field oxide layer 200 may expose the top surface of the epitaxial layer 110 between the first well 122 and the doped region 126, and may at least expose the top surface of the first well 122. For example, the field oxide layer 200 may expose at least 10%, 25%, 50%, 75%, 99%, 100%, or any value or range of values ​​between the aforementioned values ​​of the top surface of the first well 122, but the present disclosure is not limited thereto. The field oxide layer 200 may expose the top surface of the epitaxial layer 110 between the second well 124 and the doped region 126, and may cover the top surface of the second well 124. In other words, the field oxide layer 200 may expose the top surface of the first well 122 or the second well 124, and may cover the top surface of the second well 124 or the first well 122. In some embodiments, the right edge of the field oxide layer 200d may be flush with the left edge of the first well 122. In some embodiments, the left edge of the field oxide layer 200f may be flush with the left edge of the second well 124. In some embodiments, the right edge of the field oxide layer 200e may be flush with the right edge of the doped region 126, and the left edge of the field oxide layer 200e may be flush with the left edge of the doped region 126.

[0076] Reference Figure 7 This is a schematic cross-sectional view of a semiconductor device 5 according to an embodiment of the present disclosure. In some embodiments, the field oxide layer 200 may expose the top surface of the epitaxial layer 110 between the first well 122 and the doped region 126, and may cover the top surface of the first well 122. The field oxide layer 200 may expose the top surface of the epitaxial layer 110 between the second well 124 and the doped region 126, and may at least partially expose the top surface of the second well 124. For example, the field oxide layer 200 may expose at least 10%, 25%, 50%, 75%, 99%, 100%, or any value or range of values ​​between the foregoing values ​​for the top surface of the second well 124, but the present disclosure is not limited thereto.

[0077] Reference Figure 8This is a schematic cross-sectional view of a semiconductor device 6 according to an embodiment of the present disclosure. In some embodiments, the field oxide layer 200 may expose the top surface of the epitaxial layer 110 between the first well 122 and the doped region 126, and may at least partially expose the top surface of the first well 122. The field oxide layer 200 may expose the top surface of the epitaxial layer 110 between the second well 124 and the doped region 126, and may at least partially expose the top surface of the second well 124. Compared to semiconductor devices 4 and 5, semiconductor device 6 has a higher breakdown voltage and thus higher breakdown resistance.

[0078] Accordingly, the field oxide layer disclosed herein can expose the top surface of the epitaxial layer between the well (e.g., a first well or a second well) and the doped region to avoid the formation of local N-type regions at the top surface of the epitaxial layer. Furthermore, the field oxide layer disclosed herein can further expose a portion of the top surface of the isolation structure and cover the remaining portion of the top surface of the isolation structure to further refine the doping profile. Thus, the semiconductor device disclosed herein can improve its breakdown resistance and / or reliability.

[0079] It should be understood that, without departing from the spirit of this disclosure, components in multiple different embodiments can be replaced, reorganized, or combined to complete other embodiments. Components in each embodiment can be arbitrarily combined and used as long as they do not violate the spirit of the invention or conflict with it. The scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps in the specific embodiments described in the specification. Those skilled in the art can understand from the content of this disclosure that current or future developed processes, machines, manufacturing, material composition, apparatus, methods, and steps can be used according to this disclosure as long as they can perform substantially the same function or obtain substantially the same result in the embodiments described herein. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. No embodiment or claim of this disclosure needs to achieve all the purposes, advantages, and / or features described in this disclosure.

[0080] Several embodiments have been summarized above to enable those skilled in the art to better understand the viewpoints of the embodiments disclosed herein. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments disclosed herein to achieve the same purposes and / or advantages as the embodiments herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A substrate having a first conductivity type; An epitaxial layer having a second conductivity type different from the first conductivity type is disposed on the substrate; An isolation structure having the first conductivity type is disposed in the epitaxial layer and includes: The first trap; A second trap; and A doped region is disposed between the first well and the second well; and An oxide layer is disposed on the epitaxial layer. The field oxide layer is exposed on the top surface of the epitaxial layer located between the first well and the doped region, or exposed on the top surface of the epitaxial layer located between the second well and the doped region.

2. The semiconductor device as claimed in claim 1, characterized in that, The field oxide layer is disposed on the doped region.

3. The semiconductor device as claimed in claim 1, characterized in that, The field oxide layer exposes the top surface of the epitaxial layer located between the first well and the doped region, and the top surface of the epitaxial layer located between the second well and the doped region.

4. The semiconductor device as claimed in claim 1, characterized in that, The field oxide layer exposes either the top surface of the first well or the top surface of the second well.

5. The semiconductor device as claimed in claim 1, characterized in that, The field oxide layer exposes the top surface of the first well and the top surface of the second well.

6. The semiconductor device as claimed in claim 1, characterized in that, The isolation structure is positioned between a high-side circuit and a potential converter.

7. The semiconductor device as claimed in claim 1, characterized in that, Including: A first buried layer having the first conductivity type is disposed between the substrate and the epitaxial layer, and is disposed below the first well and the second well.

8. The semiconductor device as claimed in claim 7, characterized in that, Including: A second buried layer, having the second conductivity type, is disposed between the substrate and the epitaxial layer. The first buried layer is disposed between the second buried layers.

9. The semiconductor device as claimed in claim 8, characterized in that, Including: A deep well, having the second conductivity type, is disposed in the epitaxial layer and between the first buried layer and the second buried layer. A high-voltage trap, having the first conductivity type, is disposed in the epitaxial layer, wherein the second embedded layer is disposed between the high-voltage trap and the first embedded layer.

10. The semiconductor device as claimed in claim 9, characterized in that, Including: A gate dielectric layer is disposed on the high-voltage well; and A gate electrode is disposed on the gate dielectric layer.

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