Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes: an active region; an isolation region defining the active region; the barrier layer is located on the active region; the upper semiconductor layer is located on the barrier layer; and a gate structure covering an upper surface, a lower surface, and a side surface in the first direction of the upper semiconductor layer. The first direction is a direction parallel to an upper surface of the active region, and the barrier layer is disposed between the gate structure and the active region.

Description

[0001] This application is a divisional application of patent application No. 202010442515.2, filed on May 22, 2020, entitled "Semiconductor Device and Method of Forming the Same". Technical Field

[0002] Embodiments of the present invention relate to semiconductor devices. More specifically, embodiments of the present invention relate to semiconductor devices including a barrier layer located between an active region and a semiconductor layer. Other embodiments of the present invention relate to methods of manufacturing semiconductor devices. Background Technology

[0003] As the demand for high performance, high speed, and / or multifunctionality in semiconductor devices increases, so does the integration density of semiconductor devices. Higher integration density helps reduce the overall size of planar metal-oxide-semiconductor field-effect transistor (MOSFET) devices. To overcome certain limitations associated with the reduction in the size of MOSFET devices, design and fabrication efforts are underway to develop MOSFETs that include channels with three-dimensional structures. Summary of the Invention

[0004] On one hand, the present invention provides a semiconductor device with increased integration density. On the other hand, the present invention provides a semiconductor device with improved overall functionality. Furthermore, the present invention provides a method for manufacturing a semiconductor device with increased productivity.

[0005] According to one aspect of the present invention, a semiconductor device includes: an active region; an isolation region defining the active region; a barrier layer located on the active region; a first upper semiconductor layer located on the barrier layer; and a gate structure covering an upper surface, a lower surface, and a side surface of the first upper semiconductor layer in a first direction. The first direction is parallel to the upper surface of the active region, and the barrier layer is disposed between the gate structure and the active region.

[0006] According to another aspect of the present invention, a semiconductor device includes: an isolation region disposed on a substrate and defining an active region; a barrier layer located on the active region; a plurality of semiconductor layers disposed on the barrier layer and spaced apart from each other in a direction perpendicular to the upper surface of the active region; a gate structure filling the space between the plurality of semiconductor layers, disposed on the plurality of semiconductor layers, extending along a first direction and overlapping the isolation region; and a first source / drain region and a second source / drain region located on the active region. The active region extends in a second direction perpendicular to the first direction, and the side surface of the active region in the first direction is aligned with the side surface of the barrier layer in the first direction.

[0007] According to another aspect of the present invention, a semiconductor device includes: a well region; a barrier epitaxial material layer grown from an upper surface of the well region; a lower epitaxial semiconductor layer grown from the upper surface of the barrier epitaxial material layer; an upper epitaxial semiconductor layer disposed on the lower epitaxial semiconductor layer and spaced apart from the lower epitaxial semiconductor layer; and a gate structure disposed on the upper epitaxial semiconductor layer, simultaneously filling the space between the upper epitaxial semiconductor layer and the lower epitaxial semiconductor layer. The barrier epitaxial material layer includes a first epitaxial region and a second epitaxial region different from the first epitaxial region, the first epitaxial regions being spaced apart from each other in a direction perpendicular to the upper surface of the well region, and the second epitaxial regions being disposed between the first epitaxial regions.

[0008] According to another aspect of the present invention, a method of forming a semiconductor device includes: forming a well region comprising a well impurity element in a substrate by performing a well formation process; forming a first epitaxial layer grown from the well region and comprising a barrier impurity element by performing a first epitaxial growth process comprising in-situ doping; and forming a stacked structure comprising alternatingly stacked second and third layers by repeatedly performing a second epitaxial growth process and a third epitaxial growth process. Each second layer is configured as an undoped semiconductor layer, and each third layer is configured as a sacrificial semiconductor layer having etch selectivity relative to the second layer. Attached Figure Description

[0009] The above and other aspects, features and advantages of the present invention will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a top view showing a semiconductor device according to an example embodiment; Figure 2 This is a cross-sectional view showing a semiconductor device according to an example embodiment; Figure 3A This is a partially enlarged cross-sectional view illustrating an example of a semiconductor device according to an exemplary embodiment; Figure 3B This is a partially enlarged cross-sectional view showing a modified example of a semiconductor device according to an exemplary embodiment; Figure 4 This is a diagram showing the impurity concentration of a portion of a layer in a semiconductor device according to an example embodiment; Figure 5A This is a partially enlarged cross-sectional view showing a modified example of a semiconductor device according to an exemplary embodiment; Figure 5B This is a partially enlarged cross-sectional view showing a modified example of a semiconductor device according to an exemplary embodiment; Figure 6AThis is a partially enlarged cross-sectional view showing a modified example of a semiconductor device according to an exemplary embodiment; Figure 6B This is a partially enlarged cross-sectional view showing a modified example of a semiconductor device according to an exemplary embodiment; Figure 7 This is a cross-sectional view illustrating a modified example of a semiconductor device according to an exemplary embodiment; Figure 8 This is a cross-sectional view illustrating a modified example of a semiconductor device according to an exemplary embodiment; Figure 9 This is a cross-sectional view illustrating a modified example of a semiconductor device according to an exemplary embodiment; Figure 10 This is a cross-sectional view illustrating a modified example of a semiconductor device according to an exemplary embodiment; Figure 11A This is a cross-sectional view illustrating a modified example of a semiconductor device according to an exemplary embodiment; Figure 11B This is a cross-sectional view illustrating a modified example of a semiconductor device according to an exemplary embodiment; Figure 12 This is a process flow diagram illustrating a method for forming a semiconductor device according to an example embodiment; and Figures 13 to 19 This is a corresponding cross-sectional view illustrating an example of a method for forming a semiconductor device according to an exemplary embodiment. Detailed Implementation

[0010] Now refer to Figure 1 , Figure 2 and Figure 3A A semiconductor device 1 according to an embodiment of the present invention is described, wherein, Figure 1 This is a top view of semiconductor device 1. Figure 2 Including along Figure 1 The cross-sectional views of semiconductor device 1 taken by lines I-I' and II-II' are shown in the figure. Figure 3A yes Figure 2 A magnified partial view of part "A" in the image.

[0011] Common Reference Figure 1 , Figure 2 and Figure 3A The semiconductor device 1 includes an active region 50b, a barrier layer 16 located on the active region 50b, a plurality of semiconductor layers 30c and 33 located on the barrier layer 16, a gate structure 83, and a source / drain region 71. The semiconductor device 1 may also include a substrate 5 and an isolation region 52.

[0012] The substrate 5 may be a semiconductor substrate such as a silicon substrate, wherein an isolation region 52 may be disposed in a field trench 50a of the substrate 5 to define an active region 50b. The isolation region 52 may be formed of an insulating material such as silicon oxide.

[0013] The active region 50b may include a well region 10 with a well impurity element. The well region 10 may be an N-type or P-type well. For example, the well region 10 may include one or more N-type well impurity elements such as phosphorus (P) or arsenic (As), or the well region may include one or more P-type well impurity elements such as boron (B).

[0014] As an example, Figure 2 The well region 10 shown is disposed in the active region 50b and extends below the isolation region 52 to the substrate 5.

[0015] A barrier layer 16 may be disposed between the plurality of semiconductor layers 30c and 33 and the active region 50b. The barrier layer 16 may include a barrier layer to block impurity elements. Here, the barrier layer 16 is disposed to prevent (or significantly reduce) the diffusion of well impurity elements from the well region 10 into the plurality of semiconductor layers 30c and 33.

[0016] In one example, the barrier layer 16 may comprise an epitaxial crystal material layer grown from the active region 50b. Therefore, in some embodiments of the present invention, the barrier layer 16 may be referred to as a "barrier epitaxial material layer".

[0017] In one example, the active region 50b may be a crystalline silicon material layer, and the barrier layer 16 may include an epitaxial silicon material layer doped with one or more barrier impurity elements using an in-situ process while being epitaxially grown from the upper surface 50U of the active region 50b in the crystalline layer. The barrier impurity element of the barrier layer 16 may be different from the well impurity element of the well region 10. For example, oxygen (O) may be used as the barrier impurity element of the barrier layer 16 (e.g., the barrier layer 16 may be an oxygen-doped epitaxial silicon material layer). Optionally or additionally, carbon (C) may be used as the barrier impurity element of the barrier layer 16.

[0018] The barrier impurity element in the barrier layer 16 can be included at a concentration that can significantly reduce or prevent the diffusion of the well impurity element in the well region 10 into the multiple semiconductor layers 30c and 33, while the barrier layer 16 still remains in crystalline form. For example, when the barrier layer 16 is an oxygen-doped epitaxial silicon material layer, the oxygen concentration in the barrier layer 16 is in the range of (for example) about 1 × 10⁻⁶. 15 atoms / cm 3 To approximately 1×10 22 atoms / cm 3 .

[0019] Multiple semiconductor layers 30c and 33 may be stacked and spaced apart from each other in a vertical direction Z, which is perpendicular to the horizontal main extension direction of the upper surface 50U of the active region 50b. Here, the terms "vertical" and "horizontal" are merely relative spatial descriptive terms arbitrarily assigned for descriptive purposes.

[0020] In one example, the plurality of semiconductor layers 30c and 33 may include a lower semiconductor layer 30c and one or more upper semiconductor layers 33 disposed on and spaced apart from the lower semiconductor layer 30c. For example, one or more upper semiconductor layers 33 may be disposed on the lower semiconductor layer 30c.

[0021] At this point, one or more upper semiconductor layers 33 can be multiple upper semiconductor layers 34c, 38c and 42c.

[0022] The lower semiconductor layer 30c can be an epitaxial semiconductor layer grown from the upper surface of the barrier layer 16. For example, the lower semiconductor layer 30c can be an epitaxial silicon layer grown from the upper surface of the barrier layer 16. The lower semiconductor layer 30c can be in contact with the barrier layer 16. Here, the lower semiconductor layer 30c can be referred to as a "lower epitaxial semiconductor layer" or a "lower epitaxial silicon layer".

[0023] Multiple upper semiconductor layers 34c, 38c and 42c can be stacked in the vertical direction Z and spaced apart from each other.

[0024] In some embodiments of the present invention, the plurality of upper semiconductor layers 34c, 38c, and 42c may all be epitaxial semiconductor layers. For example, the plurality of upper semiconductor layers 34c, 38c, and 42c may all be epitaxial silicon layers. Here, the plurality of upper semiconductor layers 34c, 38c, and 42c may all be referred to as "upper epitaxial semiconductor layers" or "upper epitaxial silicon layers".

[0025] In one example, at least a portion of the semiconductor layers 30c and 33 may be undoped epitaxial silicon material layers.

[0026] In another example, at least a portion of the plurality of semiconductor layers 30c and 33 may include the same impurity elements as those used in the well impurity elements in the well region 10. For example, at least a portion of the plurality of semiconductor layers 30c and 33 (e.g., the lower semiconductor layer 30c) may include the same impurity elements as the well impurity elements in the well region 10, and the concentration of the impurity elements in the lower semiconductor layer 30c may be less than the concentration of the well impurity elements in the well region 10.

[0027] The source / drain region 71 can be disposed on the active region 50b, extending in the vertical direction Z, and contacting the side surface 33S2 of the plurality of upper semiconductor layers 34c, 38c, and 42c in the second direction X. For example, the source / drain region 71 may include a first source / drain region 71_1 and a second source / drain region 71_2 spaced apart from each other, and the plurality of upper semiconductor layers 34c, 38c, and 42c may be disposed between the first source / drain region 71_1 and the second source / drain region 71_2. The barrier layer 16 may also include a first portion located between the first source / drain region 71_1 and the active region 50b, and a second portion located between the second source / drain region 71_2 and the active region 50b.

[0028] In one example, the gate structure 83 may extend to the isolation region 52 and overlap with the active region 50b. The gate structure 83 may extend in a first direction Y, and the active region 50b may extend in a second direction X perpendicular to the first direction Y. Both the first direction Y and the second direction X may be set parallel to the upper surface 50U of the active region 50b. The gate structure 83 may be disposed on a plurality of upper semiconductor layers 34c, 38c, and 42c, while filling the space between the plurality of upper semiconductor layers 34c, 38c, and 42c.

[0029] The gate structure 83 may cover the upper surface, lower surface, and side surface 33S1 in the first direction Y of each of the plurality of upper semiconductor layers 34c, 38c, and 42c. The gate structure 83 may cover at least a portion of the side surface 30S1 in the first direction Y of the lower semiconductor layer 30c, while also covering the upper surface of the lower semiconductor layer 30c.

[0030] The gate structure 83 may include a gate dielectric 85 and a gate electrode 87. The gate dielectric 85 may include silicon oxide and / or a high-k dielectric. The gate electrode 87 may include a conductive material. The gate dielectric 85 may be disposed between the gate electrode 87 and the plurality of semiconductor layers 30c and 33, between the gate electrode 87 and the source / drain region 71, and between the isolation region 52 and the gate electrode 87, and is disposed on a side surface of the gate electrode 87 at a higher horizontal height than the horizontal height of the plurality of semiconductor layers 30c and 33. In this context, the term "higher horizontal height" is a relative spatial description used relative to the separation distance between the various elements and the main surface of the substrate 5.

[0031] The semiconductor device 1 may further include a gate cover pattern 90 on the gate structure 83, contact plugs 93 on the source / drain regions 71, and a gate spacer 65. The contact plugs 93 may include a first contact plug 93_1 electrically connected to the first source / drain region 71_1 and a second contact plug 93_2 electrically connected to the second source / drain region 71_2. The gate cover pattern 90 may be formed of an insulating material. The gate spacer 65 may be disposed between the gate cover pattern 90 and the contact plugs 93, and between the gate structure 83 and the contact plugs 93.

[0032] In some embodiments of the present invention, the barrier layer 16 can improve the leakage current characteristics of the semiconductor device 1. For example, the source / drain region 71, the plurality of semiconductor layers 30c and 33 serving as the channel region between the source / drain region 71, and the gate structure 83 can form a MOSFET with a three-dimensional channel structure. In such a MOSFET, the barrier layer 16 can block or significantly reduce the leakage current between the lower semiconductor layer 30c of the plurality of semiconductor layers 30c and 33 and the substrate 5. Furthermore, the barrier layer 16 can block or significantly reduce the leakage current between the source / drain region 71 and the substrate 5. Therefore, the barrier layer 16 can improve the overall operating characteristics of the semiconductor device 1.

[0033] In one example, the barrier impurity element in barrier layer 16 can be uniformly distributed within barrier layer 16. In another example, the concentration of the barrier impurity element in barrier layer 16 can be higher in the lower region of barrier layer 16 than in the upper region of barrier layer 16. In yet another example, the concentration of the barrier impurity element in barrier layer 16 can gradually vary from the lower region of barrier layer 16 to the upper region of barrier layer 16.

[0034] In some embodiments of the present invention, the barrier layer 16 may include one or more first regions and one or more second regions. Here, the first region may be a region where the concentration of the barrier impurity element is relatively higher than that of the second region(s). Alternatively, the first region may be a region containing the barrier impurity element, while the second region may be a region without the barrier impurity element.

[0035] exist Figure 3B In the example shown, the barrier layer 16 includes multiple first regions and multiple second regions. Here, similar to Figure 3A , Figure 3B yes Figure 2 A magnified view of region "A" in the image.

[0036] Reference Figure 3B The barrier layer 16a includes at least one first region 17 in contact with at least one second region 18.

[0037] However, the first region 17 can be configured as multiple first regions, and the second region 18 can be configured as multiple second regions. In one example, the barrier layer 16a may include first regions 17a and 17b and a second region 18a located between the first regions 17a and 17b spaced apart from each other in the vertical direction Z. As another example, the barrier layer 16a may include multiple first regions 17a, 17b, and 17c and multiple second regions 18a and 18b. The multiple first regions 17a, 17b, and 17c and the multiple second regions 18a and 18b may be stacked alternately in the vertical direction Z. Among the alternately stacked multiple first regions 17a, 17b, and 17c and multiple second regions 18a and 18b, the lowermost first region 17a may be located at the bottom, and the uppermost first region 17c may be located at the top.

[0038] The plurality of second regions 18a and 18b may differ from the plurality of first regions 17a, 17b and 17c. For example, the plurality of first regions 17a, 17b and 17c may be regions containing blocking impurity elements, and the concentration of the blocking impurity element in at least one of the plurality of second regions 18a and 18b may be approximately zero, or may be less than the concentration of the blocking impurity element in the plurality of first regions 17a, 17b and 17c. For example, the concentration of the blocking impurity element in each of the plurality of second regions 18a and 18b may be approximately zero, or may be less than the concentration of the blocking impurity element in the plurality of first regions 17a, 17b and 17c.

[0039] Each of the plurality of first regions 17a, 17b, and 17c may be formed of a doped epitaxial semiconductor material (e.g., epitaxial silicon) containing blocking impurity elements, and each of the plurality of second regions 18a and 18b may contain an epitaxial semiconductor material (e.g., epitaxial silicon) that does not contain blocking impurity elements, or contains a smaller amount of blocking impurity elements compared to the plurality of first regions 17a, 17b, and 17c. As an example, each of the plurality of second regions 18a and 18b may be formed of undoped epitaxial silicon.

[0040] Multiple first regions 17a, 17b and 17c can all be referred to as "first extensional regions", and multiple second regions 18a and 18b can all be referred to as "second extensional regions".

[0041] The multiple first regions 17a, 17b, and 17c can all be referred to as "barrier regions," and the multiple second regions 18a and 18b can all be referred to as "buffer regions." For example, the multiple first regions 17a, 17b, and 17c can be "barrier regions" that suppress diffusion or leakage current. The multiple second regions 18a and 18b can be "buffer regions" that prevent the multiple first regions 17a, 17b, and 17c from becoming amorphous by increasing the concentration of barrier impurity elements in the multiple first regions 17a, 17b, and 17c.

[0042] Figure 4 This is a diagram showing the concentration distribution of barrier impurity element BIE and trap impurity element WIE in barrier layer 16 and trap region 10. Figure 4 In the diagram, the axis marked "D" represents the depth in the direction from the surface of the lower semiconductor layer 30c to the well region 10, and the axis marked "C" represents the impurity concentration.

[0043] Reference Figure 4 A barrier layer 16 may be disposed between the well region 10 and the lower semiconductor layer 30c. The barrier layer 16 may contain a barrier impurity element (BIE), and the well region 10 may contain a well impurity element (WIE). As an example, the barrier impurity element (BIE) may be oxygen (O), and the well impurity element (WIE) may be arsenic (As).

[0044] The well impurity element WIE diffuses in well region 10, and the concentration of the well impurity element increases towards the barrier layer 16, thus reaching its maximum concentration in the barrier layer 16. For example, the well impurity element WIE diffuses from well region 10 and can therefore be deposited in the boundary region between the barrier layer 16 and well region 10, or in the barrier layer 16 adjacent to well region 10. Therefore, the barrier layer 16 can contain well impurity elements WIE that diffuse from well region 10 to deposit together with barrier impurity elements BIE. The concentration of well impurity elements WIE in the barrier layer 16 can be higher than the concentration of well impurity elements WIE in well region 10. The barrier layer 16 can prevent or significantly reduce the diffusion of well impurity elements WIE from well region 10 into the lower semiconductor layer 30c.

[0045] Figure 5A and Figure 5B Various examples of modifications to the thickness of the barrier layer 16 are shown. Therefore, Figure 5A and Figure 5B They are shown respectively Figure 2 A magnified view of region "A" in the image.

[0046] Reference Figure 5AThe thickness 16H of the barrier layer 16b can be less than the thickness 33H of at least one of the plurality of semiconductor layers 30c and 33. For example, the thickness 16H of the barrier layer 16b can be less than the thickness 30H of the lower semiconductor layer 30c, and can be less than the thickness 33H of each of the plurality of upper semiconductor layers 33. The barrier layer 16b described above can be used instead of Figure 2 and Figure 3A The barrier layer 16. As described above, a barrier layer 16b with a relatively small thickness 16H can improve the integration density of semiconductor devices.

[0047] Reference Figure 5B The thickness 16Ha of the barrier layer 16c can be greater than the thickness 33H of at least one of the plurality of semiconductor layers 30c and 33. For example, the thickness 16Ha of the barrier layer 16b can be greater than the thickness 30H of the lower semiconductor layer 30c, and can be greater than the thickness 33H of each of the plurality of upper semiconductor layers 33. The barrier layer 16c described above can be used instead of Figure 2 and Figure 3A The barrier layer 16 is described above. As such, a barrier layer 16c with a relatively large thickness 16Ha can improve the leakage current characteristics of the semiconductor device. Furthermore, since the barrier layer 16c with a relatively large thickness 16Ha can be used as a source / drain region (… Figure 2 71) Apply stress to improve the formation in the source / drain region ( Figure 2 The multiple semiconductor layers 30c and 33 in the channel between 71) are stressors for carrier mobility, thus improving the function of the semiconductor device.

[0048] In a similar way, Figure 6A and Figure 6B Various examples of modifications to the lower semiconductor layer 30c are shown. Therefore, Figure 6A and Figure 6B Too Figure 2 A magnified partial view of region "A" in the image.

[0049] Reference Figure 6A The thickness 30Ha of the lower semiconductor layer 30c' can be greater than the thickness 33Ha of each of the plurality of upper semiconductor layers 33. The aforementioned lower semiconductor layer 30c' can be the lower semiconductor layer previously described ( Figure 2 , Figure 3A , Figure 5A and Figure 5B Replace 30c in the text.

[0050] Reference Figure 6BThe thickness 30Hb of the lower semiconductor layer 30c" can be less than the thickness 33Ha of each of the plurality of upper semiconductor layers 33. The aforementioned lower semiconductor layer 30c" can be the lower semiconductor layer previously described ( Figure 2 , Figure 3A , Figure 5A and Figure 5B Replace 30c in the text.

[0051] Figure 7 and Figure 8 Various modification examples of the barrier layer 16, the lower semiconductor layer 30c, and the source / drain region 71 are shown, in which... Figure 7 It is along Figure 1 A cross-sectional view of the region intercepted by line I-I' in the diagram.

[0052] Reference Figure 7 The barrier layer 16d and the source / drain region 71a are in direct contact with each other (i.e., there is no intermediate layer or element). Here, the lower semiconductor layer 30d may have a side surface 30S2 in the second direction X, and the source / drain region 71a may be in contact with the side surface 30S2 of the lower semiconductor layer 30d in the second direction X.

[0053] The barrier layer 16d may include a first thickness portion and a second thickness portion that is thinner than the first thickness portion. The first thickness portion of the barrier layer 16d may be the portion disposed between the lower semiconductor layer 30d and the active region 50b, while the second thickness portion of the barrier layer 16d may be the portion disposed between the source / drain region 71a and the active region 50b.

[0054] The aforementioned barrier layer 16d, lower semiconductor layer 30d, and source / drain region 71a can be constructed using the previously described barrier layer ( Figure 2 16) Lower semiconductor layer ( Figure 2 30 in the middle) and source / drain region ( Figure 2 Replace 71 in the text.

[0055] Reference Figure 8 The barrier layer 16e can be compared with the reference. Figure 7 The lower semiconductor layer 30d, described as having a side surface in the second direction X, is self-aligned. Therefore, the barrier layer 16e can have a side surface 16S2 in the second direction X. The source / drain region 71b can be in direct contact with the well region 10 in the active region 50b'. The source / drain region 71b can be in contact with the side surface of the lower semiconductor layer 30d in the second direction X and the side surface 16S2 of the barrier layer 16e in the second direction X.

[0056] The aforementioned barrier layer 16e, lower semiconductor layer 30d, and source / drain region 71b can be respectively used as Figure 2 Barrier layer 16 in Figure 2 The lower semiconductor layer 30 and / or Figure 2 The source / drain region 71 in the middle is replaced.

[0057] Figure 9 and Figure 10 Various examples of modifications to the gate structure 83 are shown, as well as along... Figure 1 The corresponding cross-sectional view of the area intercepted by line II-II' in the diagram.

[0058] Reference Figure 9 The gate structure 83a covers the side surface 30S1 of the lower semiconductor layer 30c in the first direction Y, and also covers the upper surface of the lower semiconductor layer 30c, extending downward to cover at least a portion of the side surface 16S1 of the barrier layer 16 in the first direction Y. The gate structure 83a may include a gate dielectric 85a and a gate electrode 87a, and the gate dielectric 85a may be in direct contact with at least a portion of the upper surface of the lower semiconductor layer 30c, the side surface 16S1 of the lower semiconductor layer 30c in the first direction Y, and the side surface 16S1 of the barrier layer 16 in the first direction Y. The gate structure 83a described above can replace... Figure 2 The gate structure 83 in the middle.

[0059] Reference Figure 10 The gate structure 83b can cover a portion of the side surface 30S1 of the lower semiconductor layer 30c in the first direction Y, the side surface 16S1 of the barrier layer 16 in the first direction Y, and the side surface 50S of the active region 50b in the first direction Y, while also covering the upper surface of the lower semiconductor layer 30c. The gate structure 83b can include a gate dielectric 85b and a gate electrode 87b, and the gate dielectric 85b can contact the upper surface of the lower semiconductor layer 30c, the side surface 30S1 of the lower semiconductor layer 30c in the first direction Y, the side surface 16S1 of the barrier layer 16 in the first direction Y, and a portion of the side surface 50S of the active region 50b in the first direction Y. The aforementioned gate structure 83b can replace... Figure 2 The gate structure 83 in the middle.

[0060] Figure 11A A modified example of the barrier layer 16 and multiple semiconductor layers 30c and 33 is shown, and is along... Figure 1 A cross-sectional view of the region intercepted by lines I-I' and II-II' in the diagram.

[0061] Reference Figure 11A In multiple semiconductor layers ( Figure 2 In 30c and 33), the lower semiconductor layer 30c can be omitted. Therefore, multiple upper semiconductor layers 33 can be disposed on the barrier layer 116.

[0062] The gate structure 83 may include a gap filling portion 83g that fills the space between the lowest upper semiconductor layer 34c and the barrier layer 116 among the plurality of upper semiconductor layers 33, and also fills the space between the plurality of upper semiconductor layers 33. The upper surface of the barrier layer 116 may contact the gap filling portion 83g of the gate structure 83.

[0063] A portion of the side surface 116S1 of the barrier layer 116 in the first direction Y may contact the gate structure 83. The barrier layer 116 may contact the source / drain region 71. The barrier layer 116 may include a first thickness portion disposed between the gate structure 83 and the active region 50b and a second thickness portion disposed between the source / drain region 71 and the active region 50b. The first thickness portion of the barrier layer 116 may be thicker than the second thickness portion of the barrier layer 116.

[0064] Return to reference Figure 2 In multiple semiconductor layers 30c and 33, the lower semiconductor layer 30c can be omitted, and it can be used... Figure 11A The "modified" barrier layer 116 replaces the barrier layer 116.

[0065] Figure 11B Some embodiments of the invention are shown. Figure 2 The example of a modified semiconductor device is shown. Therefore, Figure 11B It shows along Figure 1 A cross-sectional view of the region intercepted by line I-I' in the diagram.

[0066] Reference Figure 11B The gap filling portion 83g of the gate structure 83 can be spaced apart from the source / drain region 71. For example, an internal spacer 69 with insulating properties can be disposed between the gap filling portion 83g of the gate structure 83 and the source / drain region 71.

[0067] Now refer to Figure 1 , Figure 2 as well as Figures 12 to 19 (Including the first and last items), certain embodiments of the inventive concept concerning a method for manufacturing semiconductor devices will be described here. Figure 12 This is an overall process flow diagram of an exemplary method. Figures 13 to 19 They respectively show the along Figure 1 A cross-sectional view of the region intercepted by line I-I' and the region intercepted along line II-II'.

[0068] Reference Figure 1 , Figure 12 and Figure 13 Substrate 5 can be prepared. Substrate 5 can be a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.

[0069] A well formation process is performed to form a well region 10 in the substrate 5 (S10). The well region 10 can be a P-type well region or an N-type well region. The well formation process may include implanting well impurity elements into the substrate 5 by performing an ion implantation process, and activating the well impurity elements in the substrate 5 by performing an annealing process.

[0070] By performing a first epitaxial growth process, a first layer 15 containing barrier impurity elements can be formed (S20). The first layer 15 may be a first epitaxial material layer grown from the well region 10 of the substrate 5, and may be doped with barrier impurity elements in situ.

[0071] As an example, a method for forming the above reference is used. Figure 3B The described barrier layer ( Figure 3B The first layer 15 of (16a) may include repeatedly performing a set of operations, wherein the set of operations includes: forming a doped epitaxial silicon layer grown from the well region 10 and doped with barrier impurity elements. Figure 3B 17a); forming from a doped epitaxial silicon layer ( Figure 3B The undoped epitaxial silicon layer grown in 17a) Figure 3B 18a); and the formation of an undoped epitaxial silicon layer ( Figure 3B The epitaxial silicon layer grown in 18a) and doped with barrier impurity elements ( Figure 3B (17b). As an example, the blocking impurity element can be oxygen (O) or carbon (C).

[0072] Reference Figure 1 , Figure 12 and Figure 14 The second and third epitaxial growth processes are repeatedly performed to form a stacked structure 25a including second layers 30a, 34a, 38a, and 42a and third layers 32a, 36a, and 40a (S20). For example, forming the stacked structure 25a may include repeatedly performing a set of operations, wherein the set of operations includes the second and third epitaxial growth processes. For example, performing the second epitaxial growth process to form the bottommost second layer 30a grown from the first layer 15, performing the third epitaxial growth process to form the bottommost third layer 32a grown from the bottommost second layer 30a, performing the second epitaxial growth process to form another second layer 34a grown from the bottommost third layer 32a, and performing the third epitaxial growth process to form another third layer 36a grown from another second layer 34a.

[0073] In one example, the second layers 30a, 34a, 38a and 42a may be undoped epitaxial silicon layers, and the third layers 32a, 36a and 40a may be epitaxial silicon-germanium layers with etch selectivity relative to the second layers 30a, 34a, 38a and 42a.

[0074] In one example, in the repeated execution of the second and third epitaxial growth processes, the second epitaxial growth process can be performed last. For example, in the second layers 30a, 34a, 38a and 42a and the third layers 32a, 36a and 40a, the bottommost layer can be the bottommost second layer 30a, and the topmost layer can be the topmost second layer 42a.

[0075] As another example, in a series of repeated second and third epitaxial growth processes, the third epitaxial growth process can be performed last.

[0076] Reference Figure 1 and Figure 15 For stacked structures ( Figure 14 25a), first layer ( Figure 1 15) and substrate 5 are etched to form field trench 50a.

[0077] A field trench 50a can define an active region 50b in the substrate 5. When forming the field trench 50a, the first layer ( Figure 14 15) is etched to form the first pattern 16, and the stacked structure ( Figure 14 25a) is etched to form a stacked line 25b.

[0078] The first pattern 16 can be referred to as a previous reference. Figure 2 The term "barrier layer" is described. In the following method description, reference numeral 16 denotes "first pattern".

[0079] Stacked line 25b may include a second layer etched ( Figure 14 The second lines 30b, 34b, 38b, and 42b formed by etching the third layer (30a, 34a, 38a, and 42a) and the third layer (30b, 34b, 38b, and 42b) Figure 14 The third line formed by 32a, 36a and 40a in the middle) Figure 14 (32b, 36b, and 40b in the original text).

[0080] Here, the well region 10 can be retained in the active region 50b, wherein the well region 10 can be retained in the substrate 5 below the field trench 50a, while also being retained in the active region 50b.

[0081] An isolation zone 52 can be provided to partially fill the field trench 50a. The isolation zone 52 can be formed of an insulating material such as silicon oxide.

[0082] The upper surface of the isolation zone 52 can be formed at a horizontal height that is lower than the upper surface of the lowermost second line 30b among the second lines 30b, 34b, 38b and 42b and higher than the upper surface of the first pattern 16.

[0083] In the modified example, the upper surface of the isolation zone 52 can be formed at a horizontal height that is lower than the horizontal height of the upper surface of the first pattern 16 and higher than the horizontal height of the lower surface of the first pattern 16.

[0084] In another modified example, the upper surface of the isolation zone 52 may be formed at a horizontal height lower than the lower surface of the first pattern 16.

[0085] In the example, the active region 50b, the first pattern 16, and the stacked line 25b can be stacked sequentially and vertically aligned. The active region 50b, the first pattern 16, and the stacked line 25b can extend along a second direction X. The second direction X can be a direction parallel to the upper surface of the substrate 5.

[0086] Reference Figure 1 and Figure 16 A sacrificial gate pattern 55 extending along the first direction Y can be provided. The sacrificial gate pattern 55 can extend to the isolation region 52, while covering the upper surface of the stacked line 25b and the side surface of the stacked line 25b in the first direction Y.

[0087] The sacrificial gate pattern 55 may include a lower sacrificial gate pattern 57 and an upper sacrificial gate pattern 59 located on the lower sacrificial gate pattern 57.

[0088] As an example, the lower sacrificial gate pattern 57 can be formed of polysilicon, and the upper sacrificial gate pattern 59 can be formed of silicon nitride.

[0089] Gate spacer 65 may be formed on the side surface of sacrificial gate pattern 55. Gate spacer 65 may be formed of insulating material.

[0090] Reference Figure 1 and Figure 17 Using the sacrificial gate pattern 55 and gate spacers 65 as an etching mask, the stacked lines are etched using an etching process. Figure 16 25b in the middle), to form recess 68. When forming recess 68, stacked lines ( Figure 16 25b) is etched to form a stacked pattern 25c.

[0091] Stacked lines ( Figure 16 The second line of 25b) Figure 16 In the first pattern, 30b, 34b, 38b, and 42b are etched to form a second pattern (30c, 34c, 38c, and 42c), stacking lines ( Figure 16 The third line of 25b in the middle ( Figure 16 32b, 36b and 40b in the middle are etched to form a third pattern (32c, 36c and 40c).

[0092] As an example, the bottom surface of the recess 68 can be positioned below the bottom surface of the lowest third pattern 32c among the third patterns 32c, 36c and 40c, and can be positioned above the bottom surface of the lowest second pattern 30c among the second patterns 30c, 34c, 38c and 42c.

[0093] In the modified example, the bottom surface of the recess 68 can be positioned above the bottom surface of the first pattern 16 and below the top surface of the first pattern 16.

[0094] In another modified example, the bottom surface of the recess 68 can be positioned below the bottom surface of the first pattern 16.

[0095] As an example, the lowest second pattern 30c among the second patterns 30c, 34c, 38c, and 42c can be referred to as the previous reference. Figure 2 The "lower semiconductor layer" described herein, wherein the remaining second patterns 34c, 38c, and 42c formed on the lowest second pattern 30c, may be referred to as the previous reference. Figure 2 The term "upper semiconductor layer" is used to describe this.

[0096] Reference Figure 1 and Figure 18 Source / drain regions 71 can be formed in the recess 68. The source / drain regions 71 can be source / drain epitaxial material layers grown from the surface of the stacked pattern 25c exposed by the recess 68 by performing a source / drain epitaxial growth process.

[0097] The source / drain region 71 may include N-type source / drain impurity elements or P-type source / drain impurity elements.

[0098] As an example, the source / drain region 71 may include a first source / drain region 71_1 and a second source / drain region 71_2 spaced apart from each other.

[0099] Then, an insulating layer is formed on the substrate 5 having source / drain regions 71, and the insulating layer is planarized until the lower sacrificial gate pattern 57 is exposed to form an interlayer insulating layer 74. The interlayer insulating layer 74 may be formed on the source / drain regions 71 and may have an upper surface coplanar with the upper surface of the lower sacrificial gate pattern 57.

[0100] Reference Figure 1 and Figure 19 Selectively remove the lower sacrificial gate pattern ( Figure 18(57) to form gate trench 77. During the formation of gate trench 77, the third pattern ( Figure 18 The side surfaces of 32c, 36c and 40c can be exposed.

[0101] After forming the gate trench 77, the third pattern having the side surface exposed by the gate trench 77 is removed. Figure 18 (32c, 36c and 40c) to form an interlayer space 80.

[0102] As previously described, the first pattern 16 can be referred to as the previous reference. Figure 2 The described "barrier layer". The first pattern 16, which can serve as such a barrier layer, can prevent or significantly reduce the diffusion of trap impurity elements in the trap region 10 into the second patterns 30c, 34c, 38c, and 42c, and the third patterns 32c, 36c, and 40c formed using various processes. The various processes may include: epitaxial growth processes for forming the second patterns 30c, 34c, 38c, and 42c, and the third patterns 32c, 36c, and 40c; epitaxial growth processes for forming the source / drain regions 71; and annealing processes for activating the source / drain impurity elements to give the source / drain regions 71 N-type or P-type conductivity. As described above, trap impurity elements do not diffuse into the third patterns 32c, 36c, and 40c, thus the third patterns can be stably and completely removed. Figure 18 (32c, 36c, and 40c).

[0103] Refer again Figure 1 and Figure 2 It is possible to partially fill the gate trench ( Figure 19 77) simultaneously fills the interlayer space ( Figure 19 The gate structure 83 (80) may include a gate dielectric 85 and a gate electrode 87. The gate dielectric 85 may include silicon oxide and / or a high-k dielectric. The gate electrode 87 may include a conductive material.

[0104] A gate trench can be formed on the gate structure 83. Figure 19 The remaining portion of the gate cover pattern 90 (77) may be formed of an insulating material such as silicon oxide and / or silicon nitride.

[0105] After etching the interlayer insulating layer located on the source / drain region 71 ( Figure 19 After step 74), a contact plug 93 can be formed on the source / drain region 71. The contact plug 93 may include a first contact plug 93_1 formed on the first source / drain region 71_1 and a second contact plug 93_2 formed on the second source / drain region 71_2.

[0106] As described above with reference to certain embodiments of the inventive concept, a semiconductor device may be provided in which a barrier layer is disposed between an active region and a semiconductor layer, wherein the barrier layer prevents or significantly reduces leakage current that may additionally occur between the semiconductor layer, which can be used as a channel, and the active region. The barrier layer can prevent or significantly reduce the diffusion of well impurity elements from the well region in the active region into the semiconductor layer.

[0107] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: Substrate; An active region, wherein the active region is located on the substrate; An isolation region is located on the substrate and on the side surface of the active region; A first source / drain region and a second source / drain region are located on the active region and spaced apart from each other. A barrier layer, the barrier layer being located on the active region and in physical contact with the active region; A lower semiconductor layer, which is located on the barrier layer and in physical contact with the barrier layer; An upper semiconductor layer, which is located on the lower semiconductor layer and spaced apart from each other in the vertical direction; as well as A gate structure covering the upper surface, lower surface, and side surface in a first direction of each of the upper semiconductor layers, and extending over the isolation region. Wherein, the vertical direction is perpendicular to the upper surface of the substrate. Wherein, the first direction is parallel to the upper surface of the substrate. The material of the barrier layer is different from the materials of the upper semiconductor layer and the lower semiconductor layer, and Wherein, at least a portion of the barrier layer, the upper semiconductor layer, and the lower semiconductor layer are located between the first source / drain region and the second source / drain region.

2. The semiconductor device according to claim 1, wherein, The lower surfaces of the first source / drain region and the lower surfaces of the second source / drain region are in physical contact with the active region.

3. The semiconductor device according to claim 1, wherein, The lower surfaces of the first source / drain region and the lower surfaces of the second source / drain region are at a lower horizontal level than the lower surface of the barrier layer.

4. The semiconductor device according to claim 1, wherein, The lower surface of the barrier layer is at a lower horizontal level than the lower surface of the gate structure adjacent to the side surface of the barrier layer.

5. The semiconductor device according to claim 1, wherein, The lower surface of the barrier layer is at a higher horizontal level than the lower surface of the gate structure adjacent to the side surface of the barrier layer.

6. The semiconductor device according to claim 1, wherein, The barrier layer contains elements that block impurities, and The upper semiconductor layer and the lower semiconductor layer do not contain the blocking impurity element.

7. The semiconductor device according to claim 1, wherein, The thickness of the lower semiconductor layer is different from the thickness of at least one of the upper semiconductor layers.

8. The semiconductor device according to claim 1, wherein, The lower semiconductor layer is in physical contact with the upper surface of the barrier layer.

9. The semiconductor device according to claim 1, wherein, The lower semiconductor layer and the upper semiconductor layer are configured as a channel.

10. The semiconductor device according to claim 1, wherein, The lower semiconductor layer and the barrier layer have the same width in a second direction that is perpendicular to both the vertical direction and the first direction.

11. The semiconductor device according to claim 1, wherein, The barrier layer is doped with oxygen.

12. The semiconductor device according to claim 11, wherein, The oxygen concentration in the barrier layer is 1×10⁻⁶. 15 atoms / cm 3 Up to 1×10 22 atoms / cm 3 Within the range.

13. The semiconductor device according to claim 1, wherein, The barrier layer is doped with impurity elements, wherein the concentration of the impurity elements in the lower region of the barrier layer is higher than the concentration of the impurity elements in the upper region of the barrier layer.

14. A semiconductor device, the semiconductor device comprising: Active region; An isolation zone, the isolation zone being located on a side surface of the active region; A first source / drain region and a second source / drain region are located on the active region and spaced apart from each other. A barrier layer, the barrier layer being located on the active region and in physical contact with the active region; A lower semiconductor layer, which is located on the barrier layer and in physical contact with the barrier layer; An upper semiconductor layer, which is located on the lower semiconductor layer and spaced apart from each other in the vertical direction; as well as A gate structure covering the upper surface, lower surface, and side surface in a first direction of each of the upper semiconductor layers, and extending over the isolation region. Wherein, the vertical direction is perpendicular to the first direction. The material of the barrier layer is different from the materials of the upper semiconductor layer and the lower semiconductor layer, and Wherein, at least a portion of the barrier layer, the upper semiconductor layer, and the lower semiconductor layer are located between the first source / drain region and the second source / drain region.

15. The semiconductor device according to claim 14, wherein, The lower surfaces of the first source / drain region and the lower surfaces of the second source / drain region are in physical contact with the active region.

16. The semiconductor device according to claim 14, wherein, The lower surfaces of the first source / drain region and the lower surfaces of the second source / drain region are at a lower horizontal level than the lower surface of the barrier layer.

17. The semiconductor device according to claim 14, wherein, The thickness of the lower semiconductor layer is different from the thickness of at least one of the upper semiconductor layers.

18. A semiconductor device, the semiconductor device comprising: The first source / drain region and the second source / drain region are spaced apart from each other; An active region, the active region including a portion located between the first source / drain region and the second source / drain region; A barrier layer, the barrier layer being located on the active region and in physical contact with the active region; A lower semiconductor layer, which is located on the barrier layer and in physical contact with the barrier layer; An upper semiconductor layer, which is located on the lower semiconductor layer and spaced apart from each other in the vertical direction; as well as A gate structure covering the upper surface, lower surface, and side surface in a first direction of each of the upper semiconductor layers. Wherein, the vertical direction is perpendicular to the first direction. The material of the barrier layer is different from the materials of the upper semiconductor layer and the lower semiconductor layer, and The active region, the upper semiconductor layer, the lower semiconductor layer, and the barrier layer are located between the first source / drain region and the second source / drain region.

19. The semiconductor device according to claim 18, wherein, The thickness of the lower semiconductor layer is different from the thickness of at least one of the upper semiconductor layers.

20. The semiconductor device according to claim 18, wherein, The active region is in physical contact with the first source / drain region and the second source / drain region.

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