Preparation method of semiconductor structure, semiconductor structure and image sensor

Abstract

The invention discloses a preparation method of a semiconductor structure, the semiconductor structure and an image sensor, and the method comprises the steps: providing a main body structure, forming a first patterned film layer on a first surface of a first substrate layer of the main body structure, a plurality of groove structures exposing the first surface are formed in the first patterned film layer; forming an oxide layer on one side, deviating from the first substrate layer, of the first patterned film layer, wherein the oxide layer covers the side wall of the groove structure; and etching the first substrate layer by taking the patterned film layer deposited with the oxide layer as a mask so as to form a light trapping structure on the first substrate layer, the light trapping structure comprising a plurality of light trapping holes which are densely distributed in a hexagonal manner. The light trapping hole in the light trapping structure formed by the mode has the characteristics of small size and high density, and the light trapping structure has low reflectivity to light, so that the image sensor formed by adopting the semiconductor structure is good in luminous flux and excellent in performance.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and in particular to a method for fabricating a semiconductor structure, a semiconductor structure, and an image sensor. Background Technology

[0002] A CMOS image sensor, also known as a CIS (Complementary Metal-Oxide-Semiconductor Image Sensor), is an electronic device that converts received light signals into electrical signals, and then into digital signals through a readout circuit. It is widely used in the vision field, such as in digital cameras, mobile phones, medical imaging equipment, security inspection equipment, and rangefinder cameras. In a CMOS image sensor, a pixel unit area of ​​a certain size is typically located on the light-receiving side to receive light signals. Therefore, the higher the optical transmittance of the pixel unit area (i.e., the higher the light flux), the better the optical sensitivity of the device, and consequently, the better the device performance.

[0003] To improve the light absorption efficiency of CMOS image sensors, traditional techniques involve adding anti-reflective coatings or increasing the thickness, but these methods offer limited improvement. To further enhance device performance, light-trapping structures have been applied to CMOS image sensors. A light-trapping structure is a special optical structure that creates micron-level textures on its surface, causing light to refract and reflect multiple times, thus trapping light and improving its absorption efficiency.

[0004] However, in existing schemes for setting up light-trapping effect structures in CMOS image sensors, due to limitations in process technology and equipment precision, the aperture of the light-trapping holes formed in the light-trapping effect structure and the center distance between two adjacent light-trapping holes (i.e., the pitch value) are relatively large. As a result, the light-trapping effect structure has poor light absorption efficiency and poor light throughput, and the performance improvement effect on CMOS image sensors is not ideal. Summary of the Invention

[0005] This application provides a method for fabricating a semiconductor structure, a semiconductor structure, and an image sensor to solve the problem that in existing schemes that set light-trapping structures in image sensors, the performance improvement effect of the image sensor is not ideal due to the large aperture and line spacing of the light-trapping holes in the formed light-trapping structures.

[0006] In a first aspect, embodiments of this application provide a method for fabricating a semiconductor structure, comprising:

[0007] A main structure is provided, wherein a first patterned film layer is formed on a first surface of a first base layer of the main structure, the first surface being the light-receiving surface of the main structure, and a plurality of groove structures are formed in the first patterned film layer, the groove structures exposing the first surface;

[0008] An oxide layer is formed on the side of the first patterned film layer opposite to the first substrate layer, and the oxide layer covers the sidewall of the groove structure.

[0009] The first substrate layer is etched using the patterned film layer after the oxide layer is deposited as a mask to form a light-trapping structure on the first substrate layer. The light-trapping structure includes a plurality of light-trapping holes arranged in a hexagonal close-packed pattern.

[0010] In the semiconductor structure fabrication method provided in this application embodiment, firstly, a main structure is provided, and a first patterned film layer is formed on the first surface of the first substrate layer of the main structure. The first surface is the light-receiving surface of the main structure, and a plurality of groove structures are formed in the first patterned film layer, the groove structures exposing the first surface; then, an oxide layer is formed on the side of the first patterned film layer away from the first substrate layer, the oxide layer covering the sidewall of the groove structure; finally, the first substrate layer is etched using the patterned film layer after the oxide layer is deposited as a mask to form a light-trapping structure on the first substrate layer, the light-trapping structure including a plurality of light-trapping holes arranged in a hexagonal close-packed pattern. By forming a first patterned film layer with multiple groove structures on the first surface of the first substrate layer of the main structure, and depositing an oxide layer on the sidewall of the groove structure, the inner diameter of the groove structure can be effectively reduced. Then, by etching the first substrate layer using the first patterned film layer as a mask, a light-trapping structure composed of light-trapping holes with a hexagonal close-packed distribution can be formed on the first substrate layer. The aperture of the light-trapping holes formed in this way is directly related to the inner diameter of the groove structure. Therefore, light-trapping holes with smaller apertures can be formed, so that the light-trapping holes of the light-trapping structure have the characteristics of small size and high density. This light-trapping structure has a low reflectivity of light. Therefore, the image sensor formed using the above semiconductor structure has better light throughput and its product performance is excellent.

[0011] In one optional embodiment, the aperture of each light-trapping hole in the light-trapping structure is less than 38 nm, the center-to-center distance between any two adjacent light-trapping holes is less than 78 nm, and the depth of the light-trapping hole is less than the thickness of the first substrate layer.

[0012] In the light-trapping structure formed by the above method, the aperture of the light-trapping aperture can be controlled below 38 nm, and the line spacing (i.e., center-to-center distance) between two adjacent light-trapping apertures can be controlled below 78 nm, thereby forming a high-density light-trapping aperture structure. Compared with the light-trapping structure with an aperture of 150 nm and a line spacing of 300 nm formed in the prior art, the small-size, high-density light-trapping aperture structure formed in this embodiment can effectively improve the light absorption efficiency, thereby improving the performance of the image sensor.

[0013] In one optional embodiment, forming a first patterned film layer on a first surface of the first substrate layer includes:

[0014] A first layered film structure and a second layered film structure are sequentially formed on the first surface;

[0015] The second layered film structure is patterned to form a plurality of first mask strips spaced apart along a first direction and a plurality of second mask strips spaced apart along a second direction on the side of the first film layer away from the main structure, thereby obtaining a second patterned film layer. The first film layer is the film layer in the first layered film structure that is farthest from the first substrate layer, and the first direction and the second direction form a fixed angle.

[0016] The first layer of the stacked film structure is etched using the second patterned film layer as a mask to obtain the first patterned film layer.

[0017] The above method involves forming a first and a second stacked film structure on a first surface as a sacrificial layer, and patterning the second stacked film structure. First mask strips spaced apart along a first direction and second mask strips spaced apart along a second direction are formed on the first film layer of the first stacked film structure. Since the first and second directions form a fixed angle, the first and second mask strips intersect each other, thereby forming multiple rhomboid groove regions on the first film layer, resulting in the second patterned film layer. During the etching of the first stacked film structure using the second patterned film layer as a mask, the first and second mask strips are used as mask layers to repeatedly etch the rhomboid groove regions formed therein, thus obtaining the first patterned film layer. Since the formation of the first patterned film layer uses the combination of existing exposure machines, deposition film technology and multilayer film etching process, there is no need to use more advanced exposure equipment or specially designed materials. It is easy to implement and has universality. Moreover, the light trapping holes of the final light trapping structure have the characteristics of small size and high density, thus effectively improving the light throughput of the image sensor.

[0018] In one optional embodiment, the patterning process of the second layer stacked film structure to form a plurality of first mask strips spaced apart along a first direction and a plurality of second mask strips spaced apart along a second direction on the side of the first film layer opposite to the main structure, thereby obtaining the second patterned film layer, includes:

[0019] The second layer of the laminated film structure is first patterned to form the plurality of first mask strips on the side of the first film layer away from the main structure;

[0020] A third layer of laminated structure is formed on the first film layer that forms the first mask strip;

[0021] The third layer of the film structure is subjected to a second patterning process to form the plurality of second mask strips on the side of the first film layer away from the main structure, thereby obtaining the second patterned film layer.

[0022] The above method requires two patterning processes during the patterning of the second layer of the stacked film structure. These two processes are used to form a first mask strip spaced along a first direction on the side of the first film layer away from the main structure, and a second mask strip spaced along a second direction. Since the first and second mask strips are intersected, multiple rhomboid groove regions are formed on the first film layer. Therefore, by setting the feature dimensions during the patterning process, such as line width and spacing, the size of the formed rhomboid groove regions can be ensured. This allows for a higher density of light-trapping holes obtained by the final etching, forming a high-density light-trapping structure and effectively improving the light absorption efficiency.

[0023] In one optional embodiment, the second laminated layer sequentially comprises, along the direction away from the main structure, a hard mask layer, a first transition layer, and a photoresist layer.

[0024] The first patterning process of the second layer stacked structure to form the plurality of first mask strips on the side of the first film layer opposite to the main structure includes:

[0025] The photoresist layer is subjected to exposure and development to form a patterned photoresist layer extending along a third direction, wherein the third direction is perpendicular to the first direction and the second direction, respectively.

[0026] The first transition layer and the hard mask layer are etched sequentially using the patterned photoresist layer as a mask to form the patterned hard mask layer.

[0027] The patterned hard mask layer is processed using a self-aligned dual imaging technique to obtain the plurality of first mask strips.

[0028] The above method, in the process of patterning the second layer of the film structure to obtain the first mask strip, adopts the combination of existing exposure machines and deposition film technology, such as using an immersion exposure machine and ALD (Atomic Layer Deposition) film deposition technology. It only requires setting the feature size in the patterning process, and the second patterned film layer can be obtained through two patterning processes. It does not rely on more advanced exposure equipment, and it is highly versatile and easy to implement.

[0029] In one optional embodiment, the first laminated film layer sequentially comprises, along the direction away from the main structure, a second film layer, a second transition layer, a third film layer, a third transition layer, and the first film layer.

[0030] The step of etching the first layer stack structure using the second patterned film layer as a mask to obtain the first patterned film layer includes:

[0031] Using the second patterned film layer as a mask, the first film layer, the third transition layer, the third film layer, the second transition layer and the second film layer are etched sequentially, and the first film layer, the third transition layer, the third film layer, the second transition layer and part of the second film layer are removed to obtain the first patterned film layer.

[0032] The above method employs a multilayer film etching process (i.e., multilayer Film Etch process) to etch the first layer of stacked film structure using the second patterned film layer as a mask. The groove structure obtained by etching is transferred layer by layer to the second film layer through the Film Etch process to obtain the first patterned film layer. Since the mask for etching is the second patterned film layer with diamond-shaped groove regions, a hole-shaped groove structure with the target size can be obtained through multiple etching processes. The method is simple and the effect is excellent.

[0033] In one optional embodiment, forming an oxide layer on the side of the first patterned film layer opposite to the first substrate layer includes:

[0034] An initial oxide layer is formed on the side of the first patterned film layer away from the first substrate layer by a deposition process, and the initial oxide layer covers the first patterned film layer.

[0035] The initial oxide layer is etched back to form an oxide layer covering the sidewalls of the groove structure.

[0036] In one optional embodiment, the step of etching back the initial oxide layer to form an oxide layer covering the sidewalls of the groove structure includes:

[0037] The initial oxide layer is etched such that the surface of the etched oxide layer facing away from the first substrate layer is flush with the opening surface of the groove structure, and the surface of the etched oxide layer facing away from the first substrate layer is flush with the bottom surface of the groove structure, thereby obtaining an oxide layer covering the sidewall of the groove structure.

[0038] The above method, in the process of forming the oxide layer covering the sidewalls of the groove structure, firstly forms an initial oxide layer on a first patterned film layer through a deposition process. This initial oxide layer covers the surface of the protruding portion in the first patterned film layer, as well as the sidewalls and bottom surface of the groove structure formed therein. Then, the initial oxide layer is etched back to remove the portion covering the surface of the protruding portion in the first patterned film layer and the portion covering the bottom surface of the groove structure, retaining only the portion covering the sidewalls of the groove structure, thus obtaining the aforementioned oxide layer. Because this oxide layer is deposited on the sidewalls of the groove structure, the inner diameter of the groove structure can be further reduced. Therefore, when further etching is performed based on this groove structure, the aperture of the light-trapping hole formed can be sufficiently small. The small-aperture light-trapping structure can ensure good light absorption, thereby improving device performance.

[0039] In one optional embodiment, the groove structure in the first patterned film layer is a pore-shaped groove structure, the pore diameter of the groove structure is a first value, the center-to-center distance between any two adjacent groove structures is a second value, and the thickness of the oxide layer is a third value.

[0040] The aperture of the light trapping hole is determined based on the first value and the third value, and the center distance between any two adjacent light trapping holes is determined based on the second value.

[0041] In an optional embodiment, after forming the light-trapping structure on the first substrate layer, the method further includes:

[0042] A planarization layer is formed to fill at least a plurality of light-trapping holes in the light-trapping structure.

[0043] After the light-trapping structure is formed in the first substrate layer, the above method can be used to form a planarization layer that fills at least a plurality of light-trapping holes on the first surface of the first substrate layer through CMP (Chemical Mechanical Polishing) process, so as to facilitate the subsequent process of the semiconductor structure.

[0044] In one alternative implementation, prior to providing the main structure, the method further includes:

[0045] Provides pixel wafers and logic wafers;

[0046] The pixel wafer and the logic wafer are bonded together to form an initial main structure;

[0047] The base layer of the pixel wafer in the initial main structure is thinned to obtain the main structure, wherein the first base layer is the base layer after the pixel wafer is thinned.

[0048] The above method involves thinning the substrate layer of the pixel wafer on an initial main structure formed by bonding pixel wafers and logic wafers. The light-trapping structure is then formed on the thinned first substrate layer, thus avoiding interference with subsequent process steps.

[0049] Secondly, embodiments of this application provide a semiconductor structure, which is prepared using the preparation method described in any of the embodiments of the first aspect above.

[0050] Thirdly, embodiments of this application provide an image sensor, including the semiconductor structure described in the second aspect above.

[0051] For the technical effects that the semiconductor structure disclosed in the second aspect and the image sensor disclosed in the fourth aspect may achieve, please refer to the above description of the technical effects that can be achieved for the first aspect or various possible solutions in the first aspect, and will not be repeated here. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 A schematic diagram of the optical path of light incident on a light trapping structure, provided for related technologies;

[0054] Figure 2A A schematic diagram of the light propagation path of an image sensor without a light-trapping structure, provided for related technologies;

[0055] Figure 2B A schematic diagram of the light propagation path of an image sensor with a light-trapping structure, provided for related technologies;

[0056] Figure 3 This is a schematic diagram illustrating the workflow of a semiconductor structure fabrication method provided in an embodiment of this application.

[0057] Figure 4 This is a schematic diagram of a main structure provided in an embodiment of this application;

[0058] Figure 5 This application provides a schematic diagram of a workflow for forming a first patterned film layer according to an embodiment of the present application.

[0059] Figure 6A This application provides a schematic diagram of a structure in which a first layer of film is formed on a first surface.

[0060] Figure 6B This application provides a schematic diagram of a structure in which a first layered film structure and a second layered film structure are formed on a first surface.

[0061] Figure 7 A top view of a second patterned film layer provided in an embodiment of this application;

[0062] Figure 8A This is a schematic diagram of a structure for forming a patterned photoresist layer, provided in an embodiment of this application.

[0063] Figure 8B This is a schematic diagram of a structure for forming a patterned hard mask layer, provided in an embodiment of this application.

[0064] Figure 8C This application provides a schematic diagram of a structure for forming multiple first mask strips.

[0065] Figure 9 This application provides a schematic diagram of a process for patterning a hard mask layer using SADP technology, as shown in the embodiments of the present application.

[0066] Figure 10A This is a schematic diagram of a structure for forming a third layer of film, provided in an embodiment of this application.

[0067] Figure 10B This is a schematic diagram of a structure for forming a second patterned film layer, provided in an embodiment of this application.

[0068] Figure 11A This is a schematic diagram of a structure for forming a patterned transition layer, provided in an embodiment of this application.

[0069] Figure 11B This is a schematic diagram of a structure for forming a patterned film layer, provided in an embodiment of this application.

[0070] Figure 11C This is a schematic diagram of a structure for forming a first patterned film layer, provided in an embodiment of this application.

[0071] Figure 12 This is a schematic diagram illustrating the geometric relationship between a mask strip and a groove structure provided in an embodiment of this application.

[0072] Figure 13A top view of an oxide layer formed on a first patterned film layer provided in an embodiment of this application;

[0073] Figure 14 A schematic diagram of a light-trapping structure formed on a first substrate layer is provided in an embodiment of this application;

[0074] Figure 15 A plan view of a light-trapping structure provided in an embodiment of this application;

[0075] Figure 16 A graph showing the reflectance of light of different wavelengths for a light-trapping structure with different pitch values ​​provided in this application embodiment;

[0076] Figure 17 This application provides a schematic diagram of a structure in which a planarization layer is formed on a first substrate layer.

[0077] Figure 18 This is a schematic diagram of an image sensor with a light-trapping structure provided in an embodiment of this application. Detailed Implementation

[0078] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0079] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0080] CMOS image sensors (hereinafter referred to as image sensors) are widely used photoelectric conversion devices. The luminous flux directly affects the device's performance; higher luminous flux results in better optical sensitivity and overall better device performance. Therefore, increasing the luminous flux of image sensors is a continuous direction for improving device performance.

[0081] In related technologies, to improve the light throughput of image sensors, an anti-reflective coating can be applied to the surface of the silicon substrate to reduce reflection; or the thickness of the silicon substrate can be increased to allow incident light to travel a longer distance and absorb more incident light. However, both increasing the anti-reflective coating and increasing the thickness of the silicon substrate have reached the bottleneck of the device's photon detection efficiency. Therefore, the concept of applying light-trapping structures (also called light-trapping effect structures) to image sensors has emerged.

[0082] A light-trapping structure is a special optical structure that creates micron-level textures on its surface, causing light to refract and reflect multiple times to achieve a light-trapping effect and improve light absorption efficiency. In addition, this structure can increase light scattering and diffraction, and lengthen the light propagation path. Therefore, it can also significantly reduce the destructive interference of incident light, further improving the light absorption and utilization rate.

[0083] Figure 1 A schematic diagram of the optical path of light incident on a light-trapping structure is shown, such as... Figure 1 As shown, when a beam of light A1 passes through the glass cover plate 11 and enters the light trapping hole 121 of the light trapping structure 12, multiple refractions and reflections will occur inside the light trapping hole 121. With each additional refraction, a larger portion of the light will enter the corresponding area. After multiple refractions, only a small portion of the light is ultimately reflected, thereby effectively improving the light absorption and utilization rate.

[0084] Based on simulation data of light reflection on silicon surfaces, it is known that the smaller the opening diameter (i.e., aperture) of the light-trapping holes in a light-trapping structure, the higher the density of light-trapping holes, the lower the light reflectivity, and the higher the light absorption rate of the light-trapping structure. Currently, although there are methods for forming light-trapping structures in the substrate layer, due to limitations in process technology and equipment precision, the aperture and pitch of the light-trapping holes in the light-trapping structures are relatively large, only achieving light-trapping structures with an aperture of 150nm and a pitch of 300nm, and the improvement effect on light absorption rate is not significant.

[0085] Furthermore, while it's possible to achieve similar light-trapping structures with high light absorption rates through the combined use of novel self-assembly materials, the high cost of these materials significantly increases device costs, hindering product competitiveness. Additionally, the material properties and processes are strictly protected, making their technical details unavailable. Of course, more advanced exposure machines, such as EUV (Extreme Ultraviolet) machines, can be used to create small-aperture light-trapping structures. However, such equipment is currently banned in China, and among existing image sensor manufacturers, the most advanced immersion lithography machines have a maximum pitch of 76nm, which is insufficient to directly form small-aperture light-trapping holes.

[0086] Figure 2A A schematic diagram of the light propagation path of an image sensor without a light-trapping structure is shown. Figure 2B A schematic diagram of the light propagation path of an image sensor with a light-trapping structure is shown.

[0087] like Figure 2A As shown, the image sensor 20 may include a microlens 201, a color filter 202, a silicon substrate 203, metal layers B1, B2, and B3. The silicon substrate 203 contains multiple electrons and holes. Figure 2A and Figure 2B In the silicon substrate, black-filled dots represent electrons, and white-filled dots represent holes.

[0088] Since no light-trapping structure is provided in the silicon substrate 203, when light is incident on the silicon substrate 203 through the microlens 201 and the filter 202, part of the light will be refracted into the silicon substrate 203 and pass through the silicon substrate 203 to reach the subsequent metal layers. These metal layers form photosensitive devices to convert the received light signals into electrical signals; the rest of the light will be reflected. Therefore, only the part of the light that has passed through the silicon substrate 203 is utilized, and the reflected light cannot be utilized. When the light reflectivity is high, the light absorption utilization rate will be low, the photosensitive device will receive less light signal, and the optical sensitivity of the device will be correspondingly worse.

[0089] like Figure 2B As shown, the image sensor 30 may include a microlens 301, a filter 302, a silicon substrate 303, a metal layer C1, a metal layer C2, and a metal layer C3, wherein a light-trapping structure 20 is formed in the silicon substrate 303.

[0090] Since a light-trapping structure 12 is formed in the silicon substrate 303, taking one of the light-trapping holes 121 as an example, when light passes through the microlens 301 and the filter 302 and is incident on the silicon substrate 303, the light will be incident on the light-trapping hole 121 on the silicon substrate 303, and will undergo multiple reflections and refractions on the surface of the light-trapping hole 121. Each time a refraction occurs, a portion of the light will pass through the silicon substrate 303 and reach the subsequent metal layer. In this way, through multiple refractions, most of the light will pass through the silicon substrate 303 and be captured and utilized by the subsequent metal layer. Only a small portion of the light will be reflected, thereby effectively improving the light absorption and utilization rate, and thus improving the optical sensitivity of the device.

[0091] Therefore, forming an effective light-trapping structure in an image sensor is crucial for improving its performance. Consequently, there is an urgent need for a method to form small-aperture, high-density light-trapping structures on semiconductor devices to effectively enhance image sensor performance.

[0092] Based on this, embodiments of this application provide a method for fabricating a semiconductor structure, a semiconductor structure, and an image sensor, which form a small-aperture, high-density light-trapping structure on a substrate layer to reduce light reflectivity, improve light absorption and utilization, and thereby improve the performance of devices using the semiconductor structure.

[0093] The technical solution in this application will now be described with reference to the accompanying drawings:

[0094] The following specific embodiments illustrate the method for fabricating the semiconductor structure provided in this application. Figure 3 As shown, the method includes the following steps:

[0095] Step S301: Provide a main structure, and form a first patterned film layer on the first surface of the first base layer of the main structure. The first surface is the light-receiving surface of the main structure. Multiple groove structures are formed in the first patterned film layer, and the groove structures expose the first surface.

[0096] In some embodiments of the present invention, the main structure provided in these embodiments can be generated in the following manner:

[0097] A pixel wafer and a logic wafer are provided; the pixel wafer and the logic wafer are bonded together to form an initial main structure; the base layer of the pixel wafer in the initial main structure is thinned to obtain the main structure, wherein the first base layer is the base layer after the pixel wafer is thinned.

[0098] Figure 4 A schematic diagram of the main structure provided in an embodiment of the present invention is shown. Figure 4As shown, the main structure 40 includes a pixel wafer 41 and a logic wafer 42 stacked together. The pixel wafer 41 is located above the logic wafer 42, and a first passivation layer 43 is disposed between the pixel wafer 41 and the logic wafer 42. The logic wafer 42 includes a second substrate layer 421, a first metal layer 422, a second passivation layer 423, and a second metal layer 424 stacked together, wherein corresponding logic processing circuits are disposed in the first metal layer 422, the second passivation layer 423, and the second metal layer 424. The pixel wafer 41 includes a third metal layer 411, a third passivation layer 412, a fourth metal layer 413, and a first substrate layer 414 stacked together, wherein corresponding pixel unit circuits are disposed in the third metal layer 411, the third passivation layer 412, and the fourth metal layer 413.

[0099] In specific implementations, both the first substrate layer 414 and the second substrate layer 421 can be silicon (Si) substrate layers, and the first passivation layer 43, the second passivation layer 423 and the third passivation layer 412 can be SiN (silicon nitride) layers. Of course, in practical applications, passivation layers formed of other materials can also be used. This is only an example and should not impose any limitations on this application.

[0100] In this embodiment, the first surface is a light-receiving surface of a semiconductor structure, such as... Figure 4 As shown, the first surface S1 is the side surface of the first base layer 414 that faces away from the main structure.

[0101] In this embodiment, the main structure is obtained by thinning the base layer of the pixel wafer on the initial main structure formed by bonding the pixel wafer and the logic wafer, and a light-trapping structure is formed on the thinned first base layer. Therefore, it will not interfere with the subsequent process.

[0102] After forming and providing the above-mentioned main structure, in this embodiment of the invention, a first patterned film layer is formed on the first surface of the first base layer of the main structure, which can be achieved in the following way:

[0103] In some embodiments, during the formation of the first patterned film layer in step S301, such as Figure 5 As shown, this can be achieved through steps S301-1 to S301-3, as detailed below:

[0104] Step S301-1: A first layered film structure and a second layered film structure are sequentially formed on the first surface.

[0105] In specific implementation, two multilayer composite film stacking deposition operations are performed on the first surface of the thinned first substrate layer to form a first layer stacked film structure and a second layer stacked film structure, which are used as sacrificial layers for subsequent patterning processing and etching pattern transfer operations.

[0106] Figure 6A This diagram illustrates a structure in which a first layered film structure is formed on the first surface of a main structure, according to an embodiment of the present invention. Figure 6B This diagram illustrates a structure provided by an embodiment of the present invention, in which a first layered film structure and a second layered film structure are formed on the first surface of a main structure.

[0107] like Figure 6A As shown, firstly, a multilayer composite film is deposited on the first surface S1 of the first substrate layer 414 to form a first stacked film structure 44. Specifically, the first stacked film structure 44 comprises a second film layer 441, a second transition layer 442, a third film layer 443, a third transition layer 444, and a first film layer 445 stacked along a direction D1 away from the main structure 40. The second film layer 441, the third film layer 443, and the first film layer 445 are all oxide layers. The first stacked film structure 44 is used for subsequent etching pattern transfer operations.

[0108] For example, the second film layer 441 and the first film layer 445 can be SiOx layers, the third film layer 443 can be a BPSG layer, the second transition layer 442 can be a SION layer, and the third transition layer 444 can be a Poly layer.

[0109] like Figure 6B As shown, after forming the first stacked film structure 44, a multilayer composite film deposition operation is performed on the surface of the first film layer 445 in the first stacked film structure 44 that faces away from the main structure 40, to form the second stacked film structure 45. Specifically, the second stacked film layer 45 is stacked along the direction D1 facing away from the main structure 40 and includes: a hard mask layer 451, a first transition layer 452, and a photoresist layer 453. The second stacked film layer 45 is used for subsequent patterning processing operations.

[0110] For example, the hard mask layer 451 can be a SOC layer, the first transition layer 452 can be a SION layer, and the photoresist layer 453 can be a PR layer.

[0111] Step S301-2: The second layer of the stacked film structure is patterned to form a plurality of first mask strips spaced apart along the first direction and a plurality of second mask strips spaced apart along the second direction on the side of the first film layer away from the main structure, thereby obtaining the second patterned film layer. The first film layer is the film layer that is farthest from the first substrate layer in the first layer of the stacked film structure, and the first direction and the second direction form a fixed angle.

[0112] Figure 7 A top view of the second patterned film layer provided in an embodiment of this application is shown. Figure 7As shown, in the second patterned film layer 445a obtained by processing the first film layer 445, a plurality of first mask strips E1 are arranged at intervals along the first direction D2, and a plurality of second mask strips E2 are arranged at intervals along the second direction D3. The first mask strips E1 and the second mask strips E2 intersect each other to form a rhomboid groove region F1. One apex of the rhomboid groove region F1 is the fixed angle formed by the first direction D2 and the second direction D3.

[0113] In some embodiments, step S301-2 can be performed in the following manner to obtain the second patterned film layer:

[0114] First, the second layer of the laminated film structure undergoes a first patterning process to form multiple first mask strips on the side of the first film layer facing away from the main structure. In a specific implementation, a technique similar to SADP (Self-Alignment Double Pitch) can be used to pattern the second layer of the laminated film structure to form multiple first mask strips on the first film layer. The specific implementation method is as follows:

[0115] Figures 8A to 8C Schematic diagrams are shown of multiple first mask strips obtained by patterning the second layer of the film structure.

[0116] like Figure 8A As shown, the photoresist layer 453 is first exposed and developed to form a patterned photoresist layer 453a extending along the third direction D4, wherein the third direction D3 is perpendicular to the first direction D2 and the second direction D3 respectively, and the third direction D3 is opposite to the direction D1 away from the main structure 40.

[0117] In practical implementation, an immersion exposure machine can be used to expose and develop the photoresist layer 453. During the exposure process, the feature dimensions of the pattern to be formed can be set to define the periodic pattern. For example, the line width can be set to 40 nm, the spacing to 60 nm, and the pattern angle to 60°. Thus, the patterned photoresist layer 453a formed is a 60° parallel strip with a space of 60 nm and a line of 40 nm. Of course, the above parameters are only examples and should not be construed as limiting this application.

[0118] like Figure 8B As shown, the first transition layer 452 and the hard mask layer 451 are etched sequentially using the patterned photoresist layer 453a as a mask, and the patterned photoresist layer 453a, the first transition layer 452, and part of the hard mask layer 451 are removed to form the patterned hard mask layer 451a. That is, in a specific implementation, the parallel strip pattern formed by the above exposure can be transferred to the hard mask layer 451 using a multilayer film etching process.

[0119] like Figure 8C As shown, the patterned hard mask layer 451a is processed using SADP technology to obtain multiple first mask strips E1. Figure 8C The dashed box is a top view of a plurality of first mask strips E1 formed on the first film layer 445, wherein the plurality of first mask strips E1 are arranged at intervals along the first direction D2.

[0120] In specific implementation, the patterned hard mask layer 451a is processed using SADP technology to obtain multiple first mask strips E1, which can be achieved in the following way:

[0121] Figure 9 A schematic diagram of the process for patterning a hard mask layer using SADP technology is shown. See also Figure 9 In (a), firstly, a parallel stripe pattern is formed in the patterned hard mask layer 451a, wherein the width of each stripe pattern is Line and the spacing is Space. See also Figure 9 In step (b), an oxide layer 51 is then deposited on the surface of the patterned hard mask layer 451a using a deposition process such as ALD. See also Figure 9 In step (c), the oxide deposited on the surface and bottom of the patterned hard mask layer 451a is then removed using an etch-back process. See also... Figure 9 In step (d), finally, the patterned hard mask layer 451a is removed, leaving only the oxide layer 51a after the etch-back process, to obtain the result shown in step (d). Figure 8C The dashed box shows the multiple first mask strips E1.

[0122] It should be noted that the oxide layer deposited on the surface of the patterned hard mask layer 451a may be of the same material as or different from the first film layer 445, and this application embodiment does not impose any restrictions on this. For ease of explanation, the following embodiments all use the example of depositing an oxide layer of the same material as the first film layer 445 on the surface of the patterned hard mask layer 451a.

[0123] The spacing (Space) and width (Line) of the strip pattern have the following relationship:

[0124] Space = Line + 2 × t; (1)

[0125] In equation (1), t is used to characterize the thickness of the deposited oxide layer 51.

[0126] For example, if the width of the stripe pattern is set to Line = 40nm and the spacing between the stripe patterns is set to Space = 60nm, then the resulting stripe pattern has a Pitch = 100nm. If the thickness of the deposited oxide layer 51 is set to t = 10nm, then a plurality of equally spaced first mask strips E1 with a width of 10nm, a spacing of 40nm, and a Pitch = 50nm are ultimately formed. If the width of the stripe pattern is set to Line = 40nm, the spacing between the stripe patterns is set to Space = 120nm, and the thickness of the deposited oxide layer 51 is set to t = 40nm, then a plurality of equally spaced first mask strips E1 with a width of 40nm, a spacing of 40nm, and a Pitch = 80nm are ultimately formed.

[0127] Then, a third layer of laminated film structure is formed on the first film layer that forms the first mask strip.

[0128] In practical implementation, ALD film deposition technology can be used to stack a third layer on the side of the first film layer that forms the first mask strip away from the first substrate layer. The individual layers in the third layer can be the same as or different from those in the second layer. For example, the third layer may include a stacked SOC layer, a SION layer, and a PR layer.

[0129] Figure 10A A schematic diagram of the structure forming the third layer of the film is shown. Figure 10A As shown, a third layered film structure 46 is formed on the side of the first film layer 445 that forms the first mask strip E1 away from the first base layer 414. The third layered film structure 46 is provided with the following layers stacked along the direction D1 away from the main structure 40: hard mask layer 451b, transition layer 452b and photoresist layer 453b.

[0130] Finally, the third layer of the film structure is patterned a second time to form multiple second mask strips on the side of the first film layer away from the main structure, thus obtaining the second patterned film layer.

[0131] It should be noted that the specific implementation process of the second patterning process of the third layer of the film structure is similar to the implementation process of the first patterning process of the second layer of the film structure, except that the angle of the final second mask strip is different from the angle of the first mask strip. Therefore, the implementation method can refer to the implementation process of the first patterning process of the second layer of the film structure, and will not be repeated here.

[0132] For example, the feature dimensions for the second patterning process can be set as: Line = 40nm, Space = 60nm, and pattern angle β = -60°, thereby forming multiple equally spaced second mask strips with a width of 10nm, a spacing of 40nm, and an angle of -60°. Of course, the above parameters are merely examples and should not be construed as limiting this application.

[0133] Figure 10B A schematic diagram of the structure forming the second patterned film layer is shown. Figure 10B As shown, the dashed box is a top view of the formed second patterned film layer 445a, wherein the formed plurality of first mask strips E1 are arranged at intervals along the first direction D2, and the formed plurality of second film strips E2 are arranged at intervals along the second direction D3.

[0134] In the above embodiments, during the formation of the second patterned film layer, two patterning processes are required. These processes are used to form first mask strips spaced apart along a first direction and second mask strips spaced apart along a second direction on the first film layer. Since the first and second mask strips are intersected, multiple rhomboid groove regions are formed on the first film layer. Therefore, by setting the feature dimensions during the patterning process, such as line width and spacing, the size of the formed rhomboid groove regions can be guaranteed. This allows for a higher density of the light-trapping holes obtained by the final etching, forming a high-density light-trapping structure and effectively improving the light absorption efficiency.

[0135] Furthermore, since the entire process utilizes the combination of existing exposure machines, deposition film technology, and multilayer film etching processes, such as using an Immersion exposure machine + ALD film deposition technology + multilayer film etching process, only the feature dimensions in the patterning process need to be set, and the second patterned film layer can be obtained through two patterning processes. It does not rely on more advanced exposure equipment, making it highly versatile and easy to implement.

[0136] Step S301-3: Using the second patterned film layer as a mask, the first stacked film structure is etched to obtain the first patterned film layer.

[0137] In some embodiments, the process of obtaining the first patterned film layer through steps S301-3 can be implemented in the following way: using the second patterned film layer as a mask, the first film layer, the third transition layer, the third film layer, the second transition layer and the second film layer are etched sequentially, and the first film layer, the third transition layer, the third film layer, the second transition layer and part of the second film layer are removed to obtain the first patterned film layer.

[0138] in, Figures 11A to 11C Schematic diagrams of the first patterned film layer obtained by etching the first layer stacked film structure are shown.

[0139] like Figure 11A As shown, the first patterned film layer 445a and the third transition layer 444 are first etched using the second patterned film layer 445a as a mask to obtain the patterned transition layer 444a, which includes a groove structure G1. Specifically, during the etching operation using the second patterned film layer 445a as a mask, the first mask strip E1 and the second mask strip E2 are used as masks to etch the rhomboid groove region formed therein, so as to etch an approximately circular hole-shaped groove structure G1 in the rhomboid groove region. These hole-shaped groove structures G1 can expose the third film layer 443; then the second patterned film layer 445a and part of the third transition layer 444 are removed to obtain the patterned transition layer 444a.

[0140] like Figure 11B As shown, using the patterned transition layer 444a as a mask, the third film layer 443 is etched to obtain the patterned film layer 443a, which includes a groove structure G2. Specifically, during the etching operation using the patterned transition layer 444a as a mask, the protruding portion of the patterned transition layer 444a is used as a mask to etch the hole-like groove structure G1 to etch out the groove structure G2. These groove structures G2 can expose the second transition layer 442, and with each additional etching, the groove structure becomes closer to a circle. Then, the patterned transition layer 444a and part of the third film layer 443 are removed to obtain the patterned film layer 443a.

[0141] like Figure 11C As shown, finally, using the patterned film layer 443a as a mask, the second transition layer 442 and the second film layer 441 are etched sequentially to obtain the first patterned film layer 441a. Figure 11C As shown in the dashed box, the first patterned film layer 441a includes multiple groove structures G3. The groove structures G3 expose the first surface S1 of the first substrate layer 414, and the multiple groove structures G3 are arranged in a hexagonal close-packed configuration. Each groove structure G3 is a hole-like groove structure. Specifically, during the etching operation using the patterned film layer 443a as a mask, the protruding portion of the patterned film layer 443a is used as a mask to etch the hole-like groove structures G2, thus etching out the groove structures G3. These groove structures G3 can expose the first surface S1 of the first substrate layer 414, and with each subsequent etching, the groove structure becomes closer to a circle. Then, by removing the patterned film layer 443a, the second transition layer 442, and part of the second film layer 441, the first patterned film layer 441a is obtained.

[0142] During the etching process of obtaining the first patterned film layer 441a with the groove structure G3 using the second patterned film layer 445a as a mask, the process is based on planar geometry and combined with... Figure 12The following relationship can be obtained:

[0143] P1 = CD + d; (2)

[0144]

[0145] CD = S1 (4)

[0146] Wherein, P1 is used to characterize the width of the first mask strip E1 and the second mask strip E2, S1 is used to characterize the spacing between two adjacent mask strips, CD is used to characterize the aperture of the groove structure G3, d is used to characterize the spacing between two adjacent groove structures G3, and P1 is used to characterize the pitch value of two adjacent groove structures G3.

[0147] The aperture of the groove structure G3 formed in the first patterned film layer 441a, the spacing between two adjacent groove structures G3, and the pitch value of two adjacent groove structures G3 can be obtained by using the above formulas (2)-(4).

[0148] For example, assuming that in the formed second patterned film layer 445a, the width of the first mask strip E1 and the second mask strip E2 are both L1 = 10nm, the spacing between two adjacent mask strips is S1 = 40nm, the angle of the first mask strip E1 is 60°, and the angle of the second mask strip E2 is -60°, then according to formulas (2)-(4), the aperture CD of the groove structure G3 can be obtained as 40nm, the spacing d between two adjacent groove structures G3 is 17.7nm, and the pitch value of two adjacent groove structures G3 is 57.7nm.

[0149] In the above embodiments, the process of etching the first layer of the stacked film structure using the second patterned film layer as a mask is achieved by a multi-layer Flim ETCH process. The groove structure obtained by etching is transferred layer by layer to the second film layer through the Flim ETCH process to obtain the first patterned film layer. Since the mask for etching is the second patterned film layer with a diamond-shaped groove area, a hole-shaped groove structure with the target size can be obtained through multiple etching processes. The implementation method is simple and the effect is excellent.

[0150] In step S302, an oxide layer is formed on the side of the first patterned film layer opposite to the first substrate layer, and the oxide layer covers the sidewall of the groove structure.

[0151] In some embodiments, the oxide layer can be formed in the following manner: an initial oxide layer is formed on the side of the first patterned film layer away from the first substrate layer by a deposition process, the initial oxide layer covering the first patterned film layer; the initial oxide layer is then etched back to form an oxide layer covering the sidewalls of the groove structure. Specifically, during the etch-back process of the initial oxide layer, the initial oxide layer can be etched such that the surface of the etched oxide layer on the side away from the first substrate layer is flush with the opening surface of the groove structure, and the surface of the etched oxide layer on the side close to the first substrate layer is flush with the bottom surface of the groove structure, thereby obtaining an oxide layer covering the sidewalls of the groove structure.

[0152] In a specific implementation, an initial oxide layer can be deposited on the upper surface of the first patterned film layer 441a using an ALD process. This initial oxide layer will cover the surface of the protruding portion in the first patterned film layer 441a, as well as the sidewalls and bottom surface of the groove structure G3 formed therein. Then, the oxide on the surface and bottom is etched away using a back-etching process, leaving only the oxide deposited on the sidewalls of the groove structure G3. In this way, the aperture of the groove structure G3 will be further reduced.

[0153] In some embodiments, the aperture of the groove structure in the first patterned film layer is a first value, the center-to-center distance between any two adjacent groove structures (i.e., the pitch) is a second value, and the thickness of the oxide layer is a third value. Then, the aperture of the groove structure in the first patterned film layer after the oxide layer is deposited is determined according to the first value and the third value, which can be specifically expressed as: aperture of the groove structure after the oxide layer is deposited = first value - 2 × third value.

[0154] Figure 13 A top view is shown of an oxide layer formed on a first patterned film layer. (See diagram.) Figure 13 As shown, the oxide layer 61 covers the sidewalls of each groove structure G3 of the first patterned film layer 441a, thereby reducing the aperture of the groove structure G3.

[0155] For example, assuming that the pore size of the groove structure G3 formed in the first patterned film layer 441a is 40 nm, the pitch is 57.7 nm, and the thickness of the deposited oxide layer is 5.6 nm, the pore size of the groove structure G3 can be reduced to 28.8 nm by means of the above method.

[0156] In the above embodiment, since the oxide layer is deposited on the sidewall of the groove structure, the inner diameter of the groove structure can be further reduced. In this way, when further etching is performed based on the groove structure, the aperture of the light trapping hole formed can be small enough. The small aperture light trapping structure can ensure a good light absorption rate, thereby improving the device performance.

[0157] Step S303: Using the patterned film layer after the oxide layer is deposited as a mask, the first substrate layer is etched to form a light-trapping structure on the first substrate layer. The light-trapping structure includes multiple light-trapping holes arranged in a hexagonal close-packed pattern.

[0158] In a specific implementation, the protruding portion in the patterned film layer after the oxide layer is deposited can be used as a mask to etch the first surface of the first substrate layer exposed by the groove structure, thereby forming a light-trapping structure with a hexagonal close-packed distribution structure on the first substrate layer. Since the aperture of the groove structure is further reduced in step S302, the aperture of the light-trapping hole obtained by etching based on the groove structure will also be smaller.

[0159] Figure 14 A schematic diagram of a light-trapping structure formed on a first substrate layer is shown. Figure 14 The dashed box in (a) is a top view of the light trapping structure 12 including the light trapping hole 121. As can be seen from (a), the multiple light trapping holes 121 in the light trapping structure 12 are arranged in a hexagonal, uniform, and densely packed manner. Figure 14 The dashed box in (b) is a cross-sectional view of the light trapping structure 12 including the light trapping hole 121. As can be seen from (b), the depth of each light trapping hole 121 in the light trapping structure 12 is less than the thickness of the first substrate layer 414.

[0160] In some embodiments, the aperture of the light-trapping aperture is less than or equal to the aperture of the groove structure in the first patterned film layer after the oxide layer is deposited, and the center-to-center distance between any two adjacent light-trapping apertures is equal to the center-to-center distance between any two adjacent groove structures.

[0161] For example, assuming that after depositing the oxide layer, the aperture of the groove structure G3 is reduced to 28.8 nm and the pitch is 57.7 nm, then the pitch of the light trapping hole 121 in the light trapping structure 12 formed in step S303 is also 57.7 nm. The aperture of the light trapping hole 121 may be 28.8 nm or less than 28.8 nm, such as 28.6 nm.

[0162] In some embodiments, the aperture of each light-trapping hole in the light-trapping structure is less than 38 nm, and the center-to-center distance between any two adjacent light-trapping holes is less than 78 nm.

[0163] Figure 15 A plan view of the light-trapping structure is shown. (See attached image.) Figure 15 As shown, each light-trapping hole 121 in the light-trapping structure 12 is arranged in a hexagonal, uniform, and densely packed pattern.

[0164] Figure 16 The graph shows the reflectance of light-trapping structures with different pitch values ​​for different wavelengths of light. Figure 16As shown in the graph, the horizontal axis X represents the wavelength of light, and the vertical axis Y represents reflectivity. This graph shows that for the same wavelength of light, the smaller the pitch value of the light-trapping structure, the lower its reflectivity, and correspondingly, the higher its light absorption and utilization rate. Therefore, the smaller the pitch of the light-trapping structure formed in a semiconductor structure (or the denser the light-trapping holes), the higher the luminous flux of the semiconductor structure and the better its performance.

[0165] Therefore, in the light-trapping structure formed by the above method, the aperture of the light-trapping aperture can be controlled below 38 nm, and the line spacing (i.e., center-to-center distance) between two adjacent light-trapping apertures can be controlled below 78 nm, thereby forming a high-density light-trapping aperture structure. Compared with the light-trapping structure with an aperture of 150 nm and a line spacing of 300 nm formed in the prior art, the small-size, high-density light-trapping aperture structure formed in this embodiment can effectively improve the light absorption efficiency, thereby improving the performance of the image sensor.

[0166] In some embodiments, after forming the light-trapping structure on the first substrate layer, a planarization layer that fills at least a plurality of light-trapping holes in the light-trapping structure may also be formed on the first substrate layer.

[0167] In practical implementation, a planarization layer can be formed by filling the light-trapping aperture with a material that matches the refractive index and then smoothing the surface using a CMP process, which facilitates subsequent 3D IC fabrication processes. The material that matches the refractive index can be determined by the material of the first substrate layer and the thickness of the wafer; this application does not impose any limitations on this.

[0168] Figure 17 A schematic diagram of a structure in which a planarization layer is formed on a first substrate layer is shown. (See diagram below.) Figure 17 As shown, the planarization layer 47 fills at least a plurality of light-trapping holes 121 in the light-trapping structure 12 in the first substrate layer 414 to facilitate subsequent process fabrication of the semiconductor structure 40.

[0169] In the semiconductor structure fabrication method provided in this application embodiment, by forming a first patterned film layer with multiple groove structures on the first surface of the first substrate layer of the main structure, and depositing an oxide layer on the sidewall of the groove structure, the inner diameter of the groove structure can be effectively reduced. Then, by etching the first substrate layer with the first patterned film layer as a mask, a light-trapping structure composed of light-trapping holes with a hexagonal close-packed distribution structure can be formed on the first substrate layer. The aperture of the light-trapping holes formed in this way is directly related to the inner diameter of the groove structure. Therefore, light-trapping holes with smaller apertures can be formed, so that the light-trapping holes of the light-trapping structure have the characteristics of small size and high density. This light-trapping structure has a low reflectivity of light. Therefore, the image sensor formed using the above semiconductor structure has better light throughput and its product performance is excellent.

[0170] Based on the same concept, an embodiment of the present application further provides a semiconductor structure. Since this semiconductor structure is obtained by the preparation method of the semiconductor structure in the embodiment of the present application, and the principle of solving problems by this semiconductor structure is similar to that of the method, the implementation of this substrate semiconductor structure can refer to the implementation of the method, and the repeated parts will not be elaborated here.

[0171] Based on the same concept, an embodiment of the present application further provides an image sensor. The principle of solving problems by this image sensor is similar to that of the aforementioned semiconductor structure. Therefore, the implementation of this image sensor can refer to the implementation of the aforementioned semiconductor structure, and the repeated parts will not be elaborated here.

[0172] Figure 18 The structural schematic diagram of an image sensor with a light trapping structure is shown. As Figure 18 shown, the image sensor 180 includes the semiconductor structure 40 provided in the above embodiment. A light trapping structure 12 is formed on the first base layer 414 of the semiconductor structure 40. And after forming the light trapping structure 12, subsequent process flows are performed, which may specifically include:

[0173] Using DTI (Deep Trench Isolation in English; Deep Trench Isolation in Chinese) technology to form deep trenches on the first base layer 414; performing the BSL (Backside Scribe Line in English; Backside Scribe Line in Chinese) process flow to form scribe lines 50 for separating different chips on the planarization layer 47; performing the BPAD (Backside PAD in English; Backside PAD in Chinese) 1 process flow to set a metal pad PAD1 on the back of the chip for connecting external circuits; performing the BALPAD (Backside Al PAD in English; Backside Al PAD in Chinese) process flow to set a pad 60 made of aluminum on the back of the chip; performing the BSLR (Backside Scribe Line Reverse in English; Backside Scribe Line Reverse in Chinese) process flow to perform scribing on the back of the wafer to divide it into individual chips; performing the BSGND (Backside GND in English; Backside GND in Chinese) process flow; performing the BMG (Backside Matrix Grid in English; Backside Matrix Grid in Chinese) process flow to set an electrode grid structure on the back of the chip; performing the BPAD2 process flow to set a metal pad PAD2 on the back of the chip.

[0174] It should be noted that other essential components of this image sensor are those that should be understood by those of ordinary skill in the art and will not be elaborated here, nor should they be regarded as a limitation to the present application.

[0175] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0176] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A main structure is provided, wherein a first patterned film layer is formed on a first surface of a first base layer of the main structure, the first surface being the light-receiving surface of the main structure, and a plurality of groove structures are formed in the first patterned film layer, the groove structures exposing the first surface; An oxide layer is formed on the side of the first patterned film layer opposite to the first substrate layer, and the oxide layer covers the sidewall of the groove structure. The first substrate layer is etched using the patterned film layer after the oxide layer is deposited as a mask to form a light-trapping structure on the first substrate layer. The light-trapping structure includes a plurality of light-trapping holes arranged in a hexagonal close-packed pattern.

2. The method as described in claim 1, characterized in that, The aperture of each light-trapping hole in the light-trapping structure is less than 38 nm, the center-to-center distance between any two adjacent light-trapping holes is less than 78 nm, and the depth of the light-trapping hole is less than the thickness of the first substrate layer.

3. The method as described in claim 1, characterized in that, The step of forming a first patterned film layer on the first surface of the first substrate layer includes: A first layered film structure and a second layered film structure are sequentially formed on the first surface; The second layered film structure is patterned to form a plurality of first mask strips spaced apart along a first direction and a plurality of second mask strips spaced apart along a second direction on the side of the first film layer away from the main structure, thereby obtaining a second patterned film layer. The first film layer is the film layer in the first layered film structure that is farthest from the first substrate layer, and the first direction and the second direction form a fixed angle. The first layer of the stacked film structure is etched using the second patterned film layer as a mask to obtain the first patterned film layer.

4. The method as described in claim 3, characterized in that, The process of patterning the second layer structure to form a plurality of first mask strips spaced apart along a first direction and a plurality of second mask strips spaced apart along a second direction on the side of the first layer away from the main structure, thereby obtaining the second patterned layer, includes: The second layer of the laminated film structure is first patterned to form the plurality of first mask strips on the side of the first film layer away from the main structure; A third layer of laminated structure is formed on the first film layer that forms the first mask strip; The third layer of the film structure is subjected to a second patterning process to form the plurality of second mask strips on the side of the first film layer away from the main structure, thereby obtaining the second patterned film layer.

5. The method as described in claim 4, characterized in that, The second layer of the film stack includes, in sequence, the following components along the direction away from the main structure: a hard mask layer, a first transition layer, and a photoresist layer; The first patterning process of the second layer stacked structure to form the plurality of first mask strips on the side of the first film layer opposite to the main structure includes: The photoresist layer is subjected to exposure and development to form a patterned photoresist layer extending along a third direction, wherein the third direction is perpendicular to the first direction and the second direction, respectively. The first transition layer and the hard mask layer are etched sequentially using the patterned photoresist layer as a mask to form the patterned hard mask layer. The patterned hard mask layer is processed using a self-aligned dual imaging technique to obtain the plurality of first mask strips.

6. The method as described in claim 3, characterized in that, The first film layer comprises, in sequence along the direction away from the main structure: a second film layer, a second transition layer, a third film layer, a third transition layer, and the first film layer; The step of etching the first layer stack structure using the second patterned film layer as a mask to obtain the first patterned film layer includes: Using the second patterned film layer as a mask, the first film layer, the third transition layer, the third film layer, the second transition layer and the second film layer are etched sequentially, and the first film layer, the third transition layer, the third film layer, the second transition layer and part of the second film layer are removed to obtain the first patterned film layer.

7. The method as described in claim 1, characterized in that, The step of forming an oxide layer on the side of the first patterned film layer opposite to the first substrate layer includes: An initial oxide layer is formed on the side of the first patterned film layer away from the first substrate layer by a deposition process, and the initial oxide layer covers the first patterned film layer. The initial oxide layer is etched back to form an oxide layer covering the sidewalls of the groove structure.

8. The method as described in claim 7, characterized in that, The step of etching back the initial oxide layer to form an oxide layer covering the sidewalls of the groove structure includes: The initial oxide layer is etched such that the surface of the etched oxide layer facing away from the first substrate layer is flush with the opening surface of the groove structure, and the surface of the etched oxide layer facing away from the first substrate layer is flush with the bottom surface of the groove structure, thereby obtaining an oxide layer covering the sidewall of the groove structure.

9. The method according to any one of claims 1-8, characterized in that, The groove structure in the first patterned film layer is a pore-shaped groove structure, the pore diameter of the groove structure is a first value, the center-to-center distance between any two adjacent groove structures is a second value, and the thickness of the oxide layer is a third value. The aperture of the light trapping hole is determined based on the first value and the third value, and the center-to-center distance between any two adjacent light trapping holes is determined based on the second value.

10. The method according to any one of claims 1-8, characterized in that, After forming the light-trapping structure on the first substrate layer, the method further includes: A planarization layer is formed to fill at least a plurality of light-trapping holes in the light-trapping structure.

11. The method according to any one of claims 1-8, characterized in that, Before providing the main structure, it also includes: Provides pixel wafers and logic wafers; The pixel wafer and the logic wafer are bonded together to form an initial main structure; The base layer of the pixel wafer in the initial main structure is thinned to obtain the main structure, wherein the first base layer is the base layer after the pixel wafer is thinned.

12. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the preparation method as described in any one of claims 1-11.

13. An image sensor, characterized in that, Including the semiconductor structure as described in claim 12.

Images