Piezoelectric heterogeneous substrate and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a piezoelectric heterogeneous substrate and a preparation method thereof. The piezoelectric heterogeneous substrate comprises a substrate layer, a piezoelectric film layer, a first stress adjusting layer and a second stress adjusting layer, the first stress adjusting layer is arranged on the side, close to the substrate layer, of the piezoelectric film layer, and the second stress adjusting layer is arranged between the piezoelectric film layer and the first stress adjusting layer. The thermal expansion coefficient of the second stress adjusting layer is smaller than that of the first stress adjusting layer and that of the piezoelectric film layer; by adopting the structure of the first stress adjusting layer and the second stress adjusting layer, the stress from the piezoelectric film layer can be actively counteracted, and the problem that stress concentration is easily caused as a brittle-brittle interface formed by the silicon substrate and the silicon dioxide layer cannot release energy through plastic deformation under thermal stress is avoided; the reliability of the device is improved, and the frequency consistency of the acoustic wave device can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a piezoelectric heterosubstrate and its preparation method. Background Technology

[0002] Piezoelectric thin films, represented by single-crystal lithium niobate (LiNbO3), lithium tantalate (LiTaO3), and aluminum nitride (AlN), have become core materials for modern radio frequency front-end filters and integrated photonic devices due to their excellent piezoelectric, ferroelectric, and optical properties. To integrate these piezoelectric materials with silicon-based semiconductor processes, the industry often uses wafer bonding, thin film deposition, or ion beam lift-off and transfer techniques to construct a composite structure of "piezoelectric thin film / functional layer (usually silicon oxide) / supporting substrate".

[0003] However, such traditional structures inherently suffer from thermomechanical stress problems. A significant coefficient of thermal expansion (CTE) mismatch exists between the piezoelectric layer, the silicon dioxide bonding layer, and the silicon support substrate. This stress problem is further exacerbated when metal layers (such as molybdenum or aluminum) are introduced into the structure. Metal layers typically have high CTEs, and their contraction behavior differs from the surrounding materials. During substrate cooling, the difference in contraction between layers leads to significant thermal mismatch stress near the interface. Tensile stress easily forms within the metal layer, causing electrode warping, wrinkling, and even peeling, while simultaneously transmitting stress upwards, exacerbating lattice distortion in the piezoelectric film. This stress not only causes warping of the piezoelectric heterostructure substrate, making subsequent nanoscale processing such as photolithography and etching difficult and reducing yield, but it can also induce microcracks and dislocations in the piezoelectric film, degrading its piezoelectric performance. Ultimately, this leads to increased device insertion loss, decreased quality factor, and frequency drift, impairing device reliability and stability.

[0004] Existing technologies mostly use a single material as a buffer layer, but their stress management is passive and unidirectional. It can only partially relax the stress from the substrate, but it is difficult to actively counteract the stress from the piezoelectric layer and the metal layer above. In addition, the brittle-brittle interface formed by the silicon substrate and the silicon dioxide layer cannot release energy through plastic deformation under thermal stress, which easily leads to stress concentration and threatens long-term reliability. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this application provides a piezoelectric heterojunction substrate that can actively counteract stress from the upper piezoelectric layer and metal layer. This avoids the problem of stress concentration caused by the brittle-brittle interface formed between the silicon substrate and the silicon dioxide layer, which cannot release energy through plastic deformation under thermal stress, thus improving the reliability of the device. The specific technical solution is as follows: On one hand, this application provides a piezoelectric heterostructure, comprising: Substrate layer; piezoelectric thin film layer; A first stress-adjusting layer is disposed on the side of the piezoelectric thin film layer near the substrate layer; A second stress-adjusting layer is disposed between the piezoelectric thin film layer and the first stress-adjusting layer. The coefficient of thermal expansion of the second stress-adjusting layer is less than that of the first stress-adjusting layer and the piezoelectric thin film layer. The first stress-adjusting layer is used to apply compressive stress to the second stress-adjusting layer to generate tensile stress within the second stress-adjusting layer. The tensile stress is opposite in direction to the compressive stress generated by the tensile stress applied to the second stress-adjusting layer by the piezoelectric thin film layer.

[0006] In a possible implementation, the coefficient of thermal expansion of the first stress-adjusting layer is less than or equal to the coefficient of thermal expansion of the piezoelectric thin film layer.

[0007] In a possible implementation, the piezoelectric heterostructure further includes a metal layer disposed between the piezoelectric thin film layer and the second stress-adjusting layer, wherein the coefficient of thermal expansion of the first stress-adjusting layer is smaller than that of the metal layer.

[0008] In a possible implementation, the piezoelectric heterostructure satisfies at least one of the following characteristics: The ratio between the thermal expansion coefficient of the second stress-adjusting layer and the thermal expansion coefficient of the first stress-adjusting layer ranges from 0.1 to 0.5. The ratio between the thermal expansion coefficient of the second stress-adjusting layer and the thermal expansion coefficient of the piezoelectric thin film layer ranges from 0.03 to 0.3. The ratio between the thermal expansion coefficient of the second stress-adjusting layer and the thermal expansion coefficient of the metal layer ranges from 0.02 to 0.2.

[0009] In a possible implementation, the piezoelectric heterostructure satisfies at least one of the following characteristics: The coefficient of thermal expansion of the first stress-adjusting layer ranges from 2.5 to 5.0 ppm / k; The material of the first stress-adjusting layer is polycrystalline silicon and / or amorphous silicon, wherein the grain size of the polycrystalline silicon ranges from 5 to 500 nm; The coefficient of thermal expansion of the second stress-adjusting layer ranges from 0.5 to 3.5 ppm / k; The material of the second stress-adjusting layer is silicon oxide and / or silicon nitride; The coefficient of thermal expansion of the piezoelectric thin film layer ranges from 4.0 to 16.5 ppm / k; The material of the piezoelectric thin film layer includes at least one of lithium niobate, lithium tantalate, and aluminum nitride. The coefficient of thermal expansion of the metal layer ranges from 4.5 to 23.0 ppm / k; The material of the metal layer includes at least one of gold, silver, copper, aluminum, nickel, platinum, titanium, tantalum, tungsten, chromium and molybdenum; The substrate material includes at least one of silicon oxide, quartz, sapphire, silicon carbide, silicon nitride, gallium nitride, and diamond.

[0010] In a possible implementation, the piezoelectric heterostructure satisfies at least one of the following characteristics: The ratio between the thickness of the first stress-adjusting layer and the thickness of the second stress-adjusting layer ranges from 1.5 to 20. The ratio between the thickness of the first stress-adjusting layer and the thickness of the second stress-adjusting layer ranges from 0.05 to 1.5.

[0011] In a possible implementation, the piezoelectric heterostructure satisfies at least one of the following characteristics: The thickness of the first stress-adjusting layer ranges from 150 to 3000 nm; The thickness of the second stress-adjusting layer ranges from 100 to 2000 nm; The thickness of the second stress-adjusting layer ranges from 2000 to 40000 nm; The thickness of the piezoelectric thin film layer ranges from 100 nm to 10000 nm; The thickness of the metal layer ranges from 10 nm to 100 nm; The thickness of the substrate layer ranges from 200um to 1000um.

[0012] In a possible implementation, the piezoelectric heterostructure satisfies at least one of the following characteristics: The intrinsic stress of the first stress-adjusting layer is compressive stress; The intrinsic stress of the second stress-adjusting layer is compressive stress or tensile stress.

[0013] In a possible implementation, the piezoelectric heterostructure further includes a third stress-adjusting layer and a fourth stress-adjusting layer, wherein the first stress-adjusting layer and the third stress-adjusting layer are symmetrically distributed based on the substrate layer, and the second stress-adjusting layer and the fourth stress-adjusting layer are symmetrically distributed based on the substrate layer; The thermal expansion coefficient of the fourth stress-adjusting layer is less than that of the third stress-adjusting layer and the piezoelectric thin film layer. The thermal expansion coefficient of the third stress-adjusting layer is less than or equal to that of the piezoelectric thin film layer.

[0014] In another aspect, the present invention provides a method for preparing a piezoelectric heterosubstrate as described in any of the above embodiments, the method comprising: S1: Provide a substrate; S2: A first stress-adjusting layer is formed on the substrate to obtain a substrate having the first stress-adjusting layer; S3: The piezoelectric thin film is bonded to the substrate having the first stress adjustment layer through the second stress adjustment layer to form the piezoelectric heterostructure; the first stress adjustment layer is disposed on the side of the piezoelectric thin film layer near the substrate layer; The second stress-adjusting layer is disposed between the piezoelectric thin film layer and the first stress-adjusting layer. The coefficient of thermal expansion of the second stress-adjusting layer is less than that of the first stress-adjusting layer and the piezoelectric thin film layer. The first stress-adjusting layer is used to apply compressive stress to the second stress-adjusting layer to generate tensile stress within the second stress-adjusting layer. The tensile stress is opposite in direction to the compressive stress generated by the tensile stress applied to the second stress-adjusting layer by the piezoelectric thin film layer.

[0015] In a possible implementation, the method further includes: The piezoelectric thin film is bonded to the substrate having the first stress adjustment layer by a metal layer and the second stress adjustment layer to form the piezoelectric heterostructure substrate; in the piezoelectric heterostructure substrate, the metal layer is disposed between the piezoelectric thin film layer and the second stress adjustment layer, and the coefficient of thermal expansion of the first stress adjustment layer is smaller than the coefficient of thermal expansion of the metal layer.

[0016] In a possible implementation, the method further includes, prior to bonding the piezoelectric film to the substrate having the first stress-adjusting layer via the second stress-adjusting layer: S31: Form the second stress-adjusting layer on the piezoelectric film to obtain a pre-piezoelectric film having the second stress-adjusting layer; S32: Anneal the piezoelectric film with the second stress adjustment layer to obtain a piezoelectric film with the second stress adjustment layer. The annealing temperature during the annealing process is not higher than the first preset annealing temperature, which is in the range of 500~700℃. and / or S33: A second stress-adjusting layer is formed on the substrate having the first stress-adjusting layer to obtain a pre-substrate having a double stress-adjusting layer; S34: Anneal the prepared substrate with the double stress adjustment layer to obtain a substrate with the double stress adjustment layer. The annealing temperature during the annealing process is not higher than the second preset annealing temperature, which is in the range of 800~1000℃.

[0017] Based on the above technical solution, this application has the following beneficial effects: The technical solution of the present invention provides a piezoelectric heterostructure, which includes a substrate layer, a piezoelectric thin film layer, a first stress adjustment layer, and a second stress adjustment layer. The first stress adjustment layer is disposed on the side of the piezoelectric thin film layer near the substrate layer, and the second stress adjustment layer is disposed between the piezoelectric thin film layer and the first stress adjustment layer. The coefficient of thermal expansion of the second stress adjustment layer is smaller than that of the first stress adjustment layer and the piezoelectric thin film layer. The second stress adjustment layer is subjected to tensile stress by the piezoelectric thin film layer, thereby generating compressive stress inside. Furthermore, because the coefficient of thermal expansion of the second stress adjustment layer is smaller than that of the first stress adjustment layer and the piezoelectric thin film layer, the second stress adjustment layer is subjected to tensile stress, thereby generating compressive stress inside. The thermal expansion coefficient of the piezoelectric thin film layer is such that the first stress adjustment layer applies a certain compressive stress to the second stress adjustment layer, which in turn generates tensile stress within the second stress adjustment layer. This tensile stress can counteract the compressive stress generated by the tensile stress applied to the second stress adjustment layer by the piezoelectric thin film layer. Therefore, by adopting the structure of the first and second stress adjustment layers, this invention can actively counteract the stress from the piezoelectric thin film layer, avoiding the problem that the brittle-brittle interface formed between the silicon substrate and the silicon dioxide layer cannot release energy through plastic deformation under thermal stress, thus easily causing stress concentration. This improves the reliability of the device and also improves the frequency consistency of the acoustic wave device. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of this application, the accompanying drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a piezoelectric heterostructure substrate in a specific embodiment of the present invention.

[0020] Figure 2 This is a schematic diagram of the structure of a piezoelectric heterostructure substrate in a specific embodiment of the present invention.

[0021] Figure 3 This is a schematic diagram of the fabrication process of the piezoelectric heterosubstrate of the present invention.

[0022] Figure 4 This is a schematic diagram of another preparation process of the piezoelectric heterosubstrate preparation method of the present invention.

[0023] In the figure: 101-substrate layer, 102-piezoelectric thin film layer, 103-first stress adjustment layer, 104-second stress adjustment layer, 105-metal layer. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0025] For the terms defined below, unless a different definition is given elsewhere in the claims or this specification, these definitions shall apply. All numerical values, whether explicitly indicated or not, are defined herein as being modified by the term "about." The term "about" generally refers to a range of numerical values ​​that a person skilled in the art would consider equivalent to the stated values ​​to produce substantially the same properties, functions, results, etc. A range of numerical values ​​indicated by a low value and a high value is defined as including all numerical values ​​included within that range and all subranges included within that range.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0027] On the one hand, such as Figure 1-2 As shown, the following describes a piezoelectric heterostructure provided in an embodiment of this application, comprising: Substrate 101; In some embodiments, the substrate 101 is made of at least one of silicon oxide, quartz, sapphire, silicon carbide, silicon nitride, gallium nitride, and diamond. The materials selected for the substrate 101 have good insulation properties, which enables the fabricated device to have a high quality factor, while also having excellent isolation to prevent signal crosstalk in the substrate.

[0028] In some embodiments, the thickness of the substrate layer 101 ranges from 200 μm to 1000 μm. By limiting the appropriate thickness range of the substrate layer 101, it is avoided that the substrate is too thin, resulting in insufficient rigidity to restrain the stress of the upper layers.

[0029] In some embodiments, the coefficient of thermal expansion of the substrate 101 ranges from 2 to 8 ppm / k.

[0030] The piezoelectric heterostructure of the present invention further includes a piezoelectric thin film layer 102.

[0031] In some embodiments, the piezoelectric thin film layer 102 is made of at least one of lithium niobate, lithium tantalate, and aluminum nitride. Specifically, the lithium niobate is monocrystalline lithium niobate, and the lithium tantalate is monocrystalline lithium tantalate. The coefficient of thermal expansion of monocrystalline lithium niobate is 7.5~13.7 ppm / k, that of monocrystalline lithium tantalate is 4~16.3 ppm / k, and that of aluminum nitride is 4.5~5.5 ppm / k. Using the above materials as the piezoelectric thin film layer 102 can broaden the application range of piezoelectric heterostructures.

[0032] In some embodiments, the coefficient of thermal expansion of the piezoelectric thin film layer 102 ranges from 4.0 to 16.5 ppm / k. The upper limit of the coefficient of thermal expansion of the piezoelectric thin film layer 102 can be, but is not limited to, 16.5 ppm / k, 16.4 ppm / k, 16.3 ppm / k, etc., and the lower limit can be, but is not limited to, 4.0 ppm / k, 4.1 ppm / k, 4.2 ppm / k, etc.; it is understood that the coefficient of thermal expansion of the piezoelectric thin film layer 102 can also be any value within the above range, which will not be enumerated here. By limiting the range of the coefficient of thermal expansion of the piezoelectric thin film layer 102, excessively large coefficients of thermal expansion can prevent excessive stress on the heterogeneous piezoelectric substrate from becoming uncompensable, thereby causing phenomena such as film cracking, peeling, or substrate fragmentation.

[0033] In some embodiments, the thickness of the piezoelectric thin film layer 102 ranges from 100 nm to 10000 nm. The upper limit of the thickness of the piezoelectric thin film layer 102 can be, but is not limited to, 10000 nm, 9999 nm, 9998 nm, etc., and the lower limit of the thickness of the piezoelectric thin film layer 102 can be, but is not limited to, 100 nm, 101 nm, 102 nm, etc.; understandably, the thickness of the piezoelectric thin film layer 102 can also be any value within the above range, which will not be enumerated here. By limiting a suitable thickness range of the piezoelectric thin film layer 102, the compensation stress required for the prepared piezoelectric heterostructure substrate can be within a controllable range. If the thickness of the piezoelectric thin film layer 102 is too large, the harmful stress generated will be greater, and the required amount of compensation stress will also be greater, thus making stress compensation impossible.

[0034] The piezoelectric heterojunction substrate of the present invention further includes a first stress adjustment layer 103 and a second stress adjustment layer 104. The first stress adjustment layer 103 is disposed on the side of the piezoelectric thin film layer 102 near the substrate layer 101. The second stress adjustment layer 104 is disposed between the piezoelectric thin film layer 102 and the first stress adjustment layer 103. The coefficient of thermal expansion of the second stress adjustment layer 104 is smaller than that of the first stress adjustment layer 103 and the piezoelectric thin film layer 102. The first stress adjustment layer 103 is used to apply compressive stress to the second stress adjustment layer 104 to generate tensile stress in the second stress adjustment layer 104. The tensile stress is opposite in direction to the compressive stress generated in the second stress adjustment layer 104 by the tensile stress applied by the piezoelectric thin film layer 102. The present invention provides a piezoelectric heterostructure, which includes a substrate layer 101, a piezoelectric thin film layer 102, a first stress-adjusting layer 103, and a second stress-adjusting layer 104. The first stress-adjusting layer 103 is disposed on the side of the piezoelectric thin film layer 102 closest to the substrate layer 101, and the second stress-adjusting layer 104 is disposed between the first stress-adjusting layer 103 and the substrate layer 101. The coefficient of thermal expansion of the second stress-adjusting layer 104 is smaller than that of the first stress-adjusting layer 103 and the piezoelectric thin film layer 102. The second stress-adjusting layer 104 is subjected to tensile stress by the piezoelectric thin film layer 102, thereby generating compressive stress internally. Because the coefficient of thermal expansion of the second stress-adjusting layer 104 is smaller than that of the first stress-adjusting layer 103 and the piezoelectric thin film layer 102, the second stress-adjusting layer 104 is subjected to tensile stress by the piezoelectric thin film layer 102, thereby generating compressive stress internally. The thermal expansion coefficient of the piezoelectric thin film layer 102 is such that the first stress adjustment layer 103 applies a certain compressive stress to the second stress adjustment layer 104, which in turn generates tensile stress inside the second stress adjustment layer 104. This tensile stress can offset the compressive stress generated by the tensile stress applied to the second stress adjustment layer 104 by the piezoelectric thin film layer 102. Therefore, by adopting the structure of the first stress adjustment layer 103 and the second stress adjustment layer 104, the present invention can actively offset the stress from the piezoelectric thin film layer 102, avoiding the problem that the brittle-brittle interface formed between the silicon substrate and the silicon dioxide layer cannot release energy through plastic deformation under thermal stress, thus easily causing stress concentration. This improves the reliability of the device and also improves the frequency consistency of the acoustic wave device.

[0035] In some embodiments, the coefficient of thermal expansion of the first stress-adjusting layer 103 is less than or equal to the coefficient of thermal expansion of the piezoelectric thin film layer 102. If the coefficient of thermal expansion of the first stress-adjusting layer 103 is large, then during cooling, the first stress-adjusting layer 103 contracts more violently than the piezoelectric thin film layer 102, which will exert a strong downward pulling force on the second stress-adjusting layer 104 and the piezoelectric thin film layer 102. This force will induce additional tensile stress inside the piezoelectric layer, resulting in a large net tensile stress on the piezoelectric layer. The second stress-adjusting layer 104 will be unable to adjust, leading to severe warping or even cracking of the device. This application solves the above phenomenon by limiting the coefficient of thermal expansion of the first stress-adjusting layer 103 to be less than or equal to the coefficient of thermal expansion of the piezoelectric thin film layer 102.

[0036] In some embodiments, the ratio between the coefficient of thermal expansion of the second stress-adjusting layer 104 and the coefficient of thermal expansion of the first stress-adjusting layer 103 ranges from 0.1 to 0.5. This configuration ensures that the first stress-adjusting layer 103 can generate tensile stress in a certain direction within the second stress-adjusting layer 104 to counteract the compressive stress generated by the tensile stress applied from the piezoelectric thin film layer 102, while avoiding excessive difference in the coefficients of thermal expansion between the two layers, which could lead to huge thermal stress and cause the buffer layer or compensation layer to crack or delaminate.

[0037] In some embodiments, the ratio between the coefficient of thermal expansion of the second stress-adjusting layer 104 and the coefficient of thermal expansion of the piezoelectric thin film layer 102 is in the range of 0.03 to 0.3. This setting ensures that the compensation direction of the first stress-adjusting layer 103 and the second stress-adjusting layer 104 is correct, and also avoids the phenomenon that excessive compensation force may push the device to warp in the opposite direction.

[0038] In some embodiments, such as Figure 2 As shown, the piezoelectric heterojunction substrate further includes a metal layer 105, which is disposed between the piezoelectric thin film layer 102 and the second stress adjustment layer 104. The coefficient of thermal expansion of the first stress adjustment layer 103 is less than that of the metal layer 105. Based on the piezoelectric thin film layer 102 in the piezoelectric substrate, a metal layer 105 is further added, and the metal layer 105 is disposed between the piezoelectric thin film layer 102 and the second stress adjustment layer 104. Due to the addition of the metal layer 105, the second stress adjustment layer 104 is simultaneously subjected to tensile stress applied by both the piezoelectric thin film layer 102 and the second stress adjustment layer 104. The required compensation force further increases. Therefore, by limiting the coefficient of thermal expansion of the first stress adjustment layer 103 to be less than that of the metal layer 105, the compensation force can be further improved, allowing the stresses of the device to cancel each other out.

[0039] In some embodiments, the ratio between the coefficient of thermal expansion of the second stress-adjusting layer 104 and the coefficient of thermal expansion of the metal layer 105 is in the range of 0.02 to 0.2. This configuration allows the second stress-adjusting layer 104 to have sufficient compensating force to offset the force applied by the metal layer 105, while also allowing the metal layer 105 to further broaden the application range of the piezoelectric heterostructure substrate.

[0040] In some embodiments, the coefficient of thermal expansion of the metal layer 105 ranges from 4.5 to 23.0 ppm / k. The upper limit of the coefficient of thermal expansion of the metal layer 105 can be, but is not limited to, 23 ppm / k, 22 ppm / k, 21 ppm / k, etc., and the lower limit of the coefficient of thermal expansion of the metal layer 105 can be, but is not limited to, 4.5 ppm / k, 4.6 ppm / k, 4.7 ppm / k, etc.; it is understood that the coefficient of thermal expansion of the metal layer 105 can also be any value within the above range, which will not be enumerated here.

[0041] In some embodiments, the thickness of the metal layer 105 ranges from 10 nm to 100 nm. The upper limit of the thickness of the metal layer 105 can be, but is not limited to, 100 nm, 99 nm, 98 nm, etc., and the lower limit of the thickness of the metal layer 105 can be, but is not limited to, 10 nm, 11 nm, 12 nm, etc.; it is understood that the thickness of the metal layer 105 can also be any value within the above range, which will not be enumerated here.

[0042] In some embodiments, the material of the metal layer 105 includes at least one of gold, silver, copper, aluminum, nickel, platinum, titanium, tantalum, tungsten, chromium, and molybdenum. By limiting the range of the material and thermal expansion coefficient of the metal layer 105, excessive thermal expansion coefficient of the metal layer 105 may generate uncompensated stress during cooling, directly leading to warping, wrinkling, or even microcracks in the metal film, and in severe cases, detachment from the interface. Furthermore, a high-stress environment can change the lattice constant of the metal, affecting its crystal quality, resistivity, and electron mobility.

[0043] In some embodiments, the coefficient of thermal expansion of the first stress-adjusting layer 103 ranges from 2.5 to 5.0 ppm / k. The upper limit of the coefficient of thermal expansion of the first stress-adjusting layer 103 can be, but is not limited to, 5.0 ppm / k, 4.9 ppm / k, 4.8 ppm / k, etc., and the lower limit of the coefficient of thermal expansion of the first stress-adjusting layer 103 can be, but is not limited to, 2.5 ppm / k, 2.6 ppm / k, 2.7 ppm / k, etc.; it is understood that the coefficient of thermal expansion of the first stress-adjusting layer 103 can also be any value within the above range, which will not be enumerated here.

[0044] In some embodiments, the material of the first stress adjustment layer 103 is polycrystalline silicon and / or amorphous silicon, with the grain size of the polycrystalline silicon ranging from 5 to 500 nm. Using polycrystalline silicon and / or amorphous silicon as the first stress adjustment layer 103 allows it to absorb and relax localized stress concentrations transferred from the substrate through minute deformations and grain boundary slip, effectively suppressing crack formation at the interface between the substrate layer 101 and the second stress adjustment layer 104. However, the grain size of the polycrystalline silicon can affect the buffering capacity of the first stress adjustment layer 103 to some extent.

[0045] In some embodiments, the coefficient of thermal expansion of the second stress-adjusting layer 104 ranges from 0.5 to 3.5 ppm / k. The upper limit of the coefficient of thermal expansion of the second stress-adjusting layer 104 can be, but is not limited to, 3.5 ppm / k, 3.4 ppm / k, 3.3 ppm / k, etc., and the lower limit of the coefficient of thermal expansion of the second stress-adjusting layer 104 can be, but is not limited to, 0.5 ppm / k, 0.6 ppm / k, 0.7 ppm / k, etc.; it is understood that the coefficient of thermal expansion of the second stress-adjusting layer 104 can also be any value within the above range, which will not be enumerated here.

[0046] In some embodiments, the material of the second stress adjustment layer 104 is silicon oxide and / or silicon nitride. By limiting the coefficients of thermal expansion of the first stress adjustment layer 103 and the second stress adjustment layer 104, it can be ensured that the first stress adjustment layer 103 and the second stress adjustment layer 104 can drive their compensation action. Silicon oxide and silicon nitride are chosen as the materials of the second stress adjustment layer 104 mainly because both have low coefficients of thermal expansion.

[0047] In some embodiments, the thickness of the first stress-adjusting layer 103 ranges from 150 to 3000 nm, and the thickness of the second stress-adjusting layer 104 ranges from 100 to 2000 nm. The upper limit of the thickness of the first stress-adjusting layer 103 can be, but is not limited to, 3000 nm, 2999 nm, 2998 nm, etc., and the lower limit of the thickness of the first stress-adjusting layer 103 can be, but is not limited to, 150 nm, 151 nm, 152 nm, etc.; it is understood that the thickness of the first stress-adjusting layer 103 can also be any value within the above range, which will not be enumerated here. The upper limit of the thickness of the second stress-adjusting layer 104 can be, but is not limited to, 2000 nm, 1999 nm, 1998 nm, etc., and the lower limit of the thickness of the second stress-adjusting layer 104 can be, but is not limited to, 100 nm, 101 nm, 102 nm, etc.; it is understood that the thickness of the second stress-adjusting layer 104 can also be any value within the above range, which will not be enumerated here.

[0048] The first stress-adjusting layer 103 needs to be thick enough to effectively relax and absorb most of the stress from the substrate and interface through its own plastic deformation. If the first stress-adjusting layer 103 is too thin, it will not have a buffering mechanical function. If it is too thick, it may lead to increased process difficulty and cost, and its own stress will also be large. The second stress-adjusting layer 104 needs to be thick enough to generate a large reverse stress, so as to effectively counteract the stress brought by the piezoelectric layer or metal layer 105. If its thickness is too thin, its counteracting effect will be greatly weakened. Therefore, the thickness range between the first stress-adjusting layer 103 and the second stress-adjusting layer 104 is limited to avoid the above problems.

[0049] In some embodiments, the ratio between the thickness of the first stress-adjusting layer 103 and the thickness of the second stress-adjusting layer 104 ranges from 1.5 to 20. When the device is an acoustic device, a thinner silicon oxide layer is required. Therefore, by limiting the above thickness ratio, the prepared piezoelectric heterostructure substrate can be more suitable for acoustic devices, and the problem of the second stress-adjusting layer 104 being too thick and the buffer layer being too thin, resulting in a large compensation force but insufficient substrate rigidity, is avoided. The problem of the buffer layer being too thick leading to excessive stress and instability is also avoided.

[0050] In some embodiments, the thickness of the first stress-adjusting layer 103 ranges from 150 to 3000 nm, and the thickness of the second stress-adjusting layer 104 ranges from 2000 to 40000 nm. The upper limit of the thickness of the first stress-adjusting layer 103 can be, but is not limited to, 3000 nm, 2999 nm, 2998 nm, etc., and the lower limit of the thickness of the first stress-adjusting layer 103 can be, but is not limited to, 150 nm, 151 nm, 152 nm, etc.; it is understood that the thickness of the first stress-adjusting layer 103 can also be any value within the above range, which will not be enumerated here. The upper limit of the thickness of the second stress-adjusting layer 104 can be, but is not limited to, 40000 nm, 39999 nm, 39998 nm, etc., and the lower limit of the thickness of the second stress-adjusting layer 104 can be, but is not limited to, 2000 nm, 2001 nm, 2002 nm, etc.; it is understood that the thickness of the second stress-adjusting layer 104 can also be any value within the above range, which will not be enumerated here. When the second stress adjustment layer 104 acts as the lower cladding or lower waveguide layer of an optical device, the second stress adjustment layer 104 is thicker and has stronger mechanical stability. It is less dependent on the first stress adjustment layer 103. Therefore, the second stress adjustment layer 104 is thicker.

[0051] In some embodiments, the ratio between the thickness of the first stress-adjusting layer 103 and the thickness of the second stress-adjusting layer 104 ranges from 0.05 to 1.5.

[0052] In some embodiments, the intrinsic stress of the first stress-adjusting layer 103 is compressive stress. During deposition, the first stress-adjusting layer 103 with intrinsic compressive stress can partially offset the tensile stress that the second stress-adjusting layer 104 may bring, thus preventing the multilayer structure from peeling or warping due to stress imbalance in the early stages of the process.

[0053] Specifically, the first stress-adjusting layer 103 is prepared by a deposition process. Specifically, the deposition process is at least one of PECVD, LPCVD, and PVD. When the deposition process is PECVD, the frequency range of the power supply used is 100–400 kHz, or the deposition temperature is less than 300°C, or the chamber pressure range is 50–300 mTorr. By using a low-frequency power supply, a lower deposition temperature, and lower gas pressure, the intrinsic compressive stress of the first stress-adjusting layer 103 can be increased. For amorphous silicon or polycrystalline silicon, a low-frequency power supply can be used to enhance the ion bombardment effect. However, for amorphous silicon, at lower deposition temperatures (<300℃), the hydrogen content is higher, which easily generates high-pressure stress. When the deposition process is LPCVD, the deposition temperature is less than 650℃, or amorphous silicon is first deposited at a deposition temperature of 550℃, followed by controlled incomplete crystallization or co-doping (such as in-situ phosphorus doping) to maintain the first stress adjustment layer 103 at compressive stress. When the deposition process is PVD, the first stress adjustment layer 103 can be made at compressive stress through low gas pressure and substrate negative bias. For example, when using PVD or PECVD deposition processes, during the deposition process, a substrate bias voltage of -50V to -200V is applied, or the power ratio of a 380kHz low-frequency power supply is increased in PECVD. The intrinsic compressive stress range of the prepared first stress adjustment layer 103 is -200MPa to -800MPa.

[0054] In some embodiments, the intrinsic stress of the second stress-adjusting layer 104 is tensile stress. When the intrinsic stress of the second stress-adjusting layer 104 is tensile stress, its tensile stress can initially balance the intrinsic compressive stress of the first stress-adjusting layer 103, allowing the entire stack to maintain initial mechanical stability after deposition, avoiding failure before baking or annealing. At the same time, the second stress-adjusting layer 104 can initially counteract the upward trend of the first stress-adjusting layer 103, allowing the entire stack to remain balanced after deposition, and can also trigger an automatic compensation mechanism.

[0055] Specifically, the second stress-adjusting layer 104, which has intrinsic stress of tensile stress, is prepared by PECVD or LPCVD deposition process. When the deposition process is PECVD and the material of the second stress-adjusting layer 104 is silicon oxide, it is achieved by using a high-frequency power supply (e.g., 13.56MHz) or reducing the low-frequency power supply (380kHz) and appropriately increasing the chamber pressure, or by using tetraethyl orthosilicate as the source silane. If the deposition process is PECVD and the material of the second stress-adjusting layer 104 is only silicon nitride, the ratio of N2 / NH3 is increased and the relative flow rate of SIH4 is reduced, based on appropriately increasing the chamber pressure and using a high-frequency power supply or reducing the low-frequency power supply, thereby making the intrinsic stress of the prepared second stress-adjusting layer 104 tensile stress.

[0056] Specifically, the intrinsic tensile stress of the second stress-adjusting layer 104 ranges from 100 MPa to 500 MPa. For example, when the deposition process used is PECVD and the material of the second stress-adjusting layer 104 is silicon nitride, the power supply frequency is 13.56 MHz and the deposition gas pressure is 2.0 to 5.0 Torr. The intrinsic tensile stress of the second stress-adjusting layer 104 prepared using this embodiment ranges from 100 MPa to 500 MPa.

[0057] In some embodiments, when the deposition process used is LPCVD, the material of the prepared second stress-regulating layer 104 is silicon oxide and silicon nitride. This is mainly because silicon oxide exhibits intrinsic compressive stress during LPCVD fabrication, therefore silicon nitride needs to be added to make the intrinsic stress of the second stress-regulating layer 104 tensile stress. For example, when the deposition process used is LPCVD, 100 nm of silicon nitride is deposited first, followed by 100 nm of LPCVD silicon oxide, resulting in the prepared second stress-regulating layer 104 having intrinsic tensile stress. In this embodiment, the stress of the 100 nm silicon nitride is high tensile stress, ranging from +1000 MPa, while the stress of the 100 nm silicon oxide is low compressive stress, ranging from -300 MPa, resulting in a net tensile stress of +350 MPa for the second stress-regulating layer 104.

[0058] In some embodiments, the intrinsic stress of the second stress-adjusting layer 104 is compressive stress.

[0059] Specifically, the ratio between the thicknesses of the first stress-adjusting layer 103 and the second stress-adjusting layer 104 ranges from 2 to 20. When the intrinsic stress of the second stress-adjusting layer 104 is compressive stress, this compressive stress may cause it to warp upwards or delaminate at the internal interface. Therefore, the thicknesses of the first stress-adjusting layer 103 and the second stress-adjusting layer 104 need to meet the aforementioned thickness ratio, making the first stress-adjusting layer 103 thicker. By utilizing the grain boundary slip of the first stress-adjusting layer 103 at high temperatures, it can absorb the stress of the second stress-adjusting layer 104, thereby maintaining the force balance of the piezoelectric heterostructure substrate, and enabling the subsequent automatic compensation mechanism to proceed smoothly.

[0060] Specifically, the second stress-regulating layer 104, having an intrinsic compressive stress, is prepared by a thermal oxidation process or an LPCVD deposition process. When the second stress-regulating layer 104 is prepared by an LPCVD deposition process, the material of the second stress-regulating layer 104 is silicon oxide and silicon nitride; when the second stress-regulating layer 104 is prepared by a thermal oxidation process, the material of the second stress-regulating layer 104 is only silicon oxide. For example, when the second stress-regulating layer 104 is prepared by a thermal oxidation process, and the material of the second stress-regulating layer 104 is only silicon oxide, the thickness ratio between the first stress-regulating layer 103 and the second stress-regulating layer 104 is 4.

[0061] In some embodiments, the piezoelectric heterostructure substrate further includes a third stress adjustment layer and a fourth stress adjustment layer, wherein the first stress adjustment layer 103 and the third stress adjustment layer are symmetrically distributed based on the substrate layer 101, and the second stress adjustment layer 104 and the fourth stress adjustment layer are symmetrically distributed based on the substrate layer 101. The coefficient of thermal expansion of the fourth stress-adjusting layer is less than that of the third stress-adjusting layer and the piezoelectric thin film layer 102. The coefficient of thermal expansion of the third stress-adjusting layer is less than or equal to that of the piezoelectric thin film layer 102. Two stress-adjusting layers are symmetrically arranged on the upper and lower sides of the substrate, which can further adjust the mechanical balance of the entire piezoelectric heterojunction substrate and avoid warping.

[0062] Specifically, the material, thickness, and coefficient of thermal expansion of the fourth stress-adjusting layer are consistent with those of the second stress-adjusting layer 104, and the material, thickness, and coefficient of thermal expansion of the third stress-adjusting layer are consistent with those of the first stress-adjusting layer 103.

[0063] On the other hand, the following describes a method for fabricating a piezoelectric heterosubstrate as described in any of the above embodiments, provided by embodiments of this application. The fabrication method includes: S1: Provide a substrate a; In some embodiments, the material of substrate a includes at least one selected from silicon oxide, quartz, sapphire, silicon carbide, silicon nitride, gallium nitride, and diamond.

[0064] In some embodiments, the coefficient of thermal expansion of substrate a ranges from 2 to 8 ppm / k.

[0065] In some embodiments, the thickness of substrate a ranges from 200um to 1000um.

[0066] S2: As Figure 3-4 As shown, a first stress adjustment layer 103 is formed on substrate a to obtain substrate b having the first stress adjustment layer 103; In some embodiments, the method further includes providing a piezoelectric film e before bonding the piezoelectric film to the substrate b having the first stress adjustment layer 103 via the second stress adjustment layer 104.

[0067] In some embodiments, a piezoelectric thin film e is provided, comprising: Ion implantation is performed on the piezoelectric thin film to form a defect layer inside the piezoelectric thin film, resulting in a piezoelectric thin film with a defect layer.

[0068] In some embodiments, a piezoelectric thin film e is provided, comprising: S201: Obtain the sacrificial substrate; S202: Ion implantation is performed on the piezoelectric thin film to form a defect layer inside the piezoelectric thin film, thereby obtaining a piezoelectric thin film with a defect layer; S203: Bond the sacrificial substrate to the piezoelectric thin film to obtain a piezoelectric thin film with a sacrificial substrate.

[0069] In some embodiments, the piezoelectric thin film is obtained by employing a chemical / physical deposition method.

[0070] In some embodiments, the piezoelectric thin film is made of at least one of lithium niobate, lithium tantalate, and aluminum nitride. Specifically, the lithium niobate is monocrystalline lithium niobate, and the lithium tantalate is monocrystalline lithium tantalate. The coefficient of thermal expansion of monocrystalline lithium niobate is 7.5~13.7 ppm / k, that of monocrystalline lithium tantalate is 4~16.3 ppm / k, and that of aluminum nitride is 4.5~5.5 ppm / k.

[0071] In some embodiments, the coefficient of thermal expansion of the piezoelectric thin film ranges from 4.0 to 16.5 ppm / k. The upper limit of the coefficient of thermal expansion of the piezoelectric thin film layer 102 can be, but is not limited to, 16.5 ppm / k, 16.4 ppm / k, 16.3 ppm / k, etc., and the lower limit of the coefficient of thermal expansion of the piezoelectric thin film layer 102 can be, but is not limited to, 4.0 ppm / k, 4.1 ppm / k, 4.2 ppm / k, etc.; it is understood that the coefficient of thermal expansion of the piezoelectric thin film layer 102 can also be any value within the above range, which will not be enumerated here.

[0072] In some embodiments, the thickness of the piezoelectric thin film layer 102 ranges from 100 nm to 10000 nm. The upper limit of the thickness of the piezoelectric thin film layer 102 can be, but is not limited to, 10000 nm, 9999 nm, 9998 nm, etc., and the lower limit of the thickness of the piezoelectric thin film layer 102 can be, but is not limited to, 100 nm, 101 nm, 102 nm, etc.; it is understood that the thickness of the piezoelectric thin film layer 102 can also be any value within the above range, which will not be enumerated here.

[0073] S3: As Figure 3-4As shown, the piezoelectric thin film is bonded to the substrate b having the first stress adjustment layer 103 through the second stress adjustment layer 104 to form a piezoelectric heterostructure substrate d; the first stress adjustment layer 103 is disposed on the side of the piezoelectric thin film layer 102 close to the substrate layer 101. The second stress-adjusting layer 104 is disposed between the piezoelectric thin film layer 102 and the first stress-adjusting layer 103. The coefficient of thermal expansion of the second stress-adjusting layer 104 is smaller than that of the first stress-adjusting layer 103 and the piezoelectric thin film layer 102. The first stress-adjusting layer 103 is used to apply compressive stress to the second stress-adjusting layer 104 to generate tensile stress in the second stress-adjusting layer 104. The tensile stress is opposite in direction to the compressive stress generated in the second stress-adjusting layer 104 by the tensile stress applied by the piezoelectric thin film layer 102.

[0074] In some embodiments, such as Figure 3-4 As shown, bonding the piezoelectric thin film e to the substrate b having the first stress adjustment layer 103 via the second stress adjustment layer 104 includes: forming the second stress adjustment layer 104 on the substrate having the first stress adjustment layer 103 to obtain a substrate c having a double stress adjustment layer. A piezoelectric thin film is formed on a substrate c with a double stress-adjusting layer to obtain a piezoelectric heterostructure.

[0075] Specifically, piezoelectric thin films are formed through chemical or physical deposition.

[0076] In some embodiments, the method further includes bonding the piezoelectric thin film e to the substrate b having the first stress adjustment layer 103 via the second stress adjustment layer 104: A second stress-adjusting layer 104 is formed on the piezoelectric thin film e to obtain a piezoelectric thin film having the second stress-adjusting layer 104; And / or, a second stress adjustment layer 104 is formed on a substrate b having a first stress adjustment layer 103 to obtain a substrate c having a double stress adjustment layer.

[0077] In some embodiments, the coefficient of thermal expansion of the first stress-adjusting layer 103 is less than or equal to the coefficient of thermal expansion of the piezoelectric thin film layer 102.

[0078] In some embodiments, the ratio between the coefficient of thermal expansion of the second stress-adjusting layer 104 and the coefficient of thermal expansion of the first stress-adjusting layer 103 is in the range of 0.1 to 0.5.

[0079] In some embodiments, the ratio between the coefficient of thermal expansion of the second stress-adjusting layer 104 and the coefficient of thermal expansion of the piezoelectric thin film layer 102 is in the range of 0.03 to 0.3.

[0080] In some embodiments, the coefficient of thermal expansion of the first stress-adjusting layer 103 ranges from 2.5 to 5.0 ppm / k. The upper limit of the coefficient of thermal expansion of the first stress-adjusting layer 103 can be, but is not limited to, 5.0 ppm / k, 4.9 ppm / k, 4.8 ppm / k, etc., and the lower limit of the coefficient of thermal expansion of the first stress-adjusting layer 103 can be, but is not limited to, 2.5 ppm / k, 2.6 ppm / k, 2.7 ppm / k, etc.; it is understood that the coefficient of thermal expansion of the first stress-adjusting layer 103 can also be any value within the above range, which will not be enumerated here.

[0081] In some embodiments, the first stress-adjusting layer 103 is made of polycrystalline silicon and / or amorphous silicon, with the grain size of the polycrystalline silicon ranging from 5 to 500 nm.

[0082] In some embodiments, the coefficient of thermal expansion of the second stress-adjusting layer 104 ranges from 0.5 to 3.5 ppm / k. The upper limit of the coefficient of thermal expansion of the second stress-adjusting layer 104 can be, but is not limited to, 3.5 ppm / k, 3.4 ppm / k, 3.3 ppm / k, etc., and the lower limit of the coefficient of thermal expansion of the second stress-adjusting layer 104 can be, but is not limited to, 0.5 ppm / k, 0.6 ppm / k, 0.7 ppm / k, etc.; it is understood that the coefficient of thermal expansion of the second stress-adjusting layer 104 can also be any value within the above range, which will not be enumerated here.

[0083] In some embodiments, the material of the second stress-adjusting layer 104 is silicon oxide and / or silicon nitride.

[0084] In some embodiments, the thickness of the first stress-adjusting layer 103 ranges from 150 to 3000 nm, and the thickness of the second stress-adjusting layer 104 ranges from 100 to 2000 nm. The upper limit of the thickness of the first stress-adjusting layer 103 can be, but is not limited to, 3000 nm, 2999 nm, 2998 nm, etc., and the lower limit of the thickness of the first stress-adjusting layer 103 can be, but is not limited to, 150 nm, 151 nm, 152 nm, etc.; it is understood that the thickness of the first stress-adjusting layer 103 can also be any value within the above range, which will not be enumerated here. The upper limit of the thickness of the second stress-adjusting layer 104 can be, but is not limited to, 2000 nm, 1999 nm, 1998 nm, etc., and the lower limit of the thickness of the second stress-adjusting layer 104 can be, but is not limited to, 100 nm, 101 nm, 102 nm, etc.; it is understood that the thickness of the second stress-adjusting layer 104 can also be any value within the above range, which will not be enumerated here.

[0085] In some embodiments, the ratio between the thickness of the first stress-adjusting layer 103 and the thickness of the second stress-adjusting layer 104 ranges from 1.5 to 20.

[0086] In some embodiments, the thickness of the first stress-adjusting layer 103 ranges from 150 to 3000 nm, and the thickness of the second stress-adjusting layer 104 ranges from 2000 to 40000 nm. The upper limit of the thickness of the first stress-adjusting layer 103 can be, but is not limited to, 3000 nm, 2999 nm, 2998 nm, etc., and the lower limit of the thickness of the first stress-adjusting layer 103 can be, but is not limited to, 150 nm, 151 nm, 152 nm, etc.; it is understood that the thickness of the first stress-adjusting layer 103 can also be any value within the above range, which will not be enumerated here. The upper limit of the thickness of the second stress-adjusting layer 104 can be, but is not limited to, 40000 nm, 39999 nm, 39998 nm, etc., and the lower limit of the thickness of the second stress-adjusting layer 104 can be, but is not limited to, 2000 nm, 2001 nm, 2002 nm, etc.; it is understood that the thickness of the second stress-adjusting layer 104 can also be any value within the above range, which will not be enumerated here.

[0087] In some embodiments, the ratio between the thickness of the first stress-adjusting layer 103 and the thickness of the second stress-adjusting layer 104 ranges from 0.05 to 1.5.

[0088] In some embodiments, such as Figure 4 As shown, the method further includes: bonding a piezoelectric thin film to a substrate b having a first stress adjustment layer 103 via a metal layer 105 and a second stress adjustment layer 104 to form a piezoelectric heterostructure g; in the piezoelectric heterostructure g, the metal layer 105 is disposed between the piezoelectric thin film layer 102 and the second stress adjustment layer 104, and the coefficient of thermal expansion of the first stress adjustment layer 103 is less than the coefficient of thermal expansion of the metal layer 105. Based on the piezoelectric thin film layer 102 on the piezoelectric substrate, a metal layer 105 is further added, and the metal layer 105 is disposed between the piezoelectric thin film layer 102 and the second stress adjustment layer 104. Due to the addition of the metal layer 105, the second stress adjustment layer 104 is simultaneously subjected to tensile stress applied by the piezoelectric thin film layer 102 and the second stress adjustment layer 104. The required compensation force further increases, thus limiting the coefficient of thermal expansion of the first stress adjustment layer 103 to be less than the coefficient of thermal expansion of the metal layer 105 further improves the compensation force, allowing the stresses of the device to cancel each other out.

[0089] In some embodiments, the method further includes bonding the piezoelectric thin film e to the substrate b having the first stress adjustment layer 103 via the metal layer 105 and the second stress adjustment layer 104: S301: A metal layer 105 is formed on the piezoelectric thin film to obtain a piezoelectric thin film f with the metal layer 105; S302: A second stress adjustment layer 104 is formed on a substrate b having a first stress adjustment layer 103 to obtain a substrate c having a double stress adjustment layer; Alternatively, S303: A metal layer 105 is formed on the piezoelectric thin film e to obtain a piezoelectric thin film f having the metal layer 105; S304: A second stress adjustment layer 104 is formed on a piezoelectric thin film f having a metal layer 105 to obtain a piezoelectric thin film having a metal layer 105 and a second stress adjustment layer 104. Alternatively, S305: A second stress adjustment layer 104 is formed on a substrate b having a first stress adjustment layer 103 to obtain a substrate c having a double stress adjustment layer; S306: A metal layer 105 is formed on a substrate c having a double stress adjustment layer, resulting in a substrate with a double stress adjustment layer and a metal layer 105.

[0090] In some embodiments, the method further includes bonding the piezoelectric thin film to the substrate having the first stress adjustment layer 103 via the metal layer 105 and the second stress adjustment layer 104: S307: A second stress adjustment layer 104 is formed on a substrate b having a first stress adjustment layer 103 to obtain a substrate c having a double stress adjustment layer; S308: A metal layer 105 is formed on the piezoelectric thin film e to obtain a piezoelectric thin film f having the metal layer 105; S309: A second stress-adjusting layer 104 is formed on a piezoelectric thin film f having a metal layer 105, thereby obtaining a piezoelectric thin film having a metal layer 105 and a second stress-adjusting layer 104.

[0091] In some embodiments, the metal layer 105 is prepared by physical vapor deposition.

[0092] In some embodiments, the metal layer 105 is formed by a patterning process. Specifically, the metal layer 105 can be formed using existing methods such as photoresist and wet or dry etching to achieve a patterned metal layer 105. Once the metal layer 105 is patterned, it can be used as the lower electrode of an acoustic resonator.

[0093] In some embodiments, the intrinsic stress of the first stress-adjusting layer 103 is compressive stress.

[0094] In some embodiments, the first stress-regulating layer 103 is prepared by a deposition process. Specifically, the deposition process is at least one of PECVD, LPCVD, and PVD.

[0095] In some embodiments, the intrinsic stress of the second stress-adjusting layer 104 is tensile stress. Specifically, the second stress-adjusting layer 104 with intrinsic tensile stress is prepared by PECVD or LPCVD deposition process. Specifically, the intrinsic tensile stress of the second stress-adjusting layer 104 ranges from 100 MPa to 500 MPa. For example, when the deposition process used is PECVD and the material of the second stress-adjusting layer 104 is silicon nitride, the frequency of the power supply used is 13.56 MHz, and the deposition gas pressure is 2.0 to 5.0 Torr. The intrinsic tensile stress of the second stress-adjusting layer 104 prepared using this embodiment ranges from 100 MPa to 500 MPa.

[0096] In some embodiments, when the deposition process used is LPCVD, the material of the prepared second stress-regulating layer 104 is silicon oxide and silicon nitride. For example, when the deposition process used is LPCVD, 100 nm of silicon nitride is deposited first, followed by 100 nm of LPCVD silicon oxide, and the intrinsic stress of the prepared second stress-regulating layer 104 is tensile stress. For example, when the deposition process used is LPCVD, 100 nm of silicon nitride is deposited first, followed by 100 nm of LPCVD silicon oxide, and the intrinsic stress of the prepared second stress-regulating layer 104 is tensile stress. In this embodiment, the stress of the 100 nm silicon nitride is high tensile stress, ranging from +1000 MPa, while the stress of the 100 nm silicon oxide is low compressive stress, ranging from -300 MPa, resulting in a net tensile stress of +350 MPa for the second stress-regulating layer 104.

[0097] In some embodiments, the intrinsic stress of the second stress-adjusting layer 104 is compressive stress.

[0098] Specifically, the ratio between the thicknesses of the first stress-adjusting layer 103 and the second stress-adjusting layer 104 ranges from 2 to 20. When the intrinsic stress of the second stress-adjusting layer 104 is compressive stress, this compressive stress may cause it to warp upwards or delaminate at the internal interface. Therefore, the thicknesses of the first stress-adjusting layer 103 and the second stress-adjusting layer 104 need to meet the aforementioned thickness ratio, making the first stress-adjusting layer 103 thicker. By utilizing the grain boundary slip of the first stress-adjusting layer 103 at high temperatures, it can absorb the stress of the second stress-adjusting layer 104, thereby maintaining the force balance of the piezoelectric heterostructure substrate, and enabling the subsequent automatic compensation mechanism to proceed smoothly.

[0099] Specifically, the second stress-regulating layer 104, having an intrinsic compressive stress, is prepared by a thermal oxidation process or an LPCVD deposition process. When the second stress-regulating layer 104 is prepared by an LPCVD deposition process, the material of the second stress-regulating layer 104 is silicon oxide and silicon nitride; when the second stress-regulating layer 104 is prepared by a thermal oxidation process, the material of the second stress-regulating layer 104 is only silicon oxide. For example, when the second stress-regulating layer 104 is prepared by a thermal oxidation process, and the material of the second stress-regulating layer 104 is only silicon oxide, the thickness ratio between the first stress-regulating layer 103 and the second stress-regulating layer 104 is 4.

[0100] In some embodiments, the ratio between the coefficient of thermal expansion of the second stress-adjusting layer 104 and the coefficient of thermal expansion of the metal layer 105 is in the range of 0.02 to 0.2.

[0101] In some embodiments, the coefficient of thermal expansion of the metal layer 105 ranges from 4.5 to 23.0 ppm / k. The upper limit of the coefficient of thermal expansion of the metal layer 105 can be, but is not limited to, 23 ppm / k, 22 ppm / k, 21 ppm / k, etc., and the lower limit of the coefficient of thermal expansion of the metal layer 105 can be, but is not limited to, 4.5 ppm / k, 4.6 ppm / k, 4.7 ppm / k, etc.; it is understood that the coefficient of thermal expansion of the metal layer 105 can also be any value within the above range, which will not be enumerated here.

[0102] In some embodiments, the thickness of the metal layer 105 ranges from 10 nm to 100 nm.

[0103] In some embodiments, the material of the metal layer 105 includes at least one selected from gold, silver, copper, aluminum, nickel, platinum, titanium, tantalum, tungsten, chromium, and molybdenum.

[0104] In some embodiments, after bonding the piezoelectric thin film to a substrate having a first stress-adjusting layer 103 via a second stress-adjusting layer 104 to form a piezoelectric heterosubstrate, the method further includes: S4: A third stress-adjusting layer is formed on the formed piezoelectric heterostructure to obtain a piezoelectric heterostructure with a third stress-adjusting layer. S5: A fourth stress-adjusting layer is formed on a piezoelectric heterostructure with a third stress-adjusting layer to obtain a piezoelectric heterostructure with a double stress-adjusting layer. In the piezoelectric heterostructure with a double stress-adjusting layer, the first stress-adjusting layer 103 and the third stress-adjusting layer are symmetrically distributed based on the substrate layer 101, and the second stress-adjusting layer 104 and the fourth stress-adjusting layer are symmetrically distributed based on the substrate layer 101. The thermal expansion coefficient of the fourth stress-adjusting layer is less than that of the third stress-adjusting layer and the piezoelectric thin film layer 102. The thermal expansion coefficient of the third stress-adjusting layer is less than or equal to that of the piezoelectric thin film layer 102.

[0105] Specifically, the material, thickness, and coefficient of thermal expansion of the fourth stress-adjusting layer are consistent with those of the second stress-adjusting layer 104, and the material, thickness, and coefficient of thermal expansion of the third stress-adjusting layer are consistent with those of the first stress-adjusting layer 103.

[0106] In some embodiments, the method further includes bonding the piezoelectric film to the substrate having the first stress-adjusting layer 103 via the second stress-adjusting layer 104: S31: A second stress-adjusting layer 104 is formed on the piezoelectric film to obtain a pre-piezoelectric film with the second stress-adjusting layer 104; S32: Anneal the piezoelectric film with the second stress adjustment layer 104 to obtain the piezoelectric film with the second stress adjustment layer 104. The annealing temperature during the annealing process is not higher than the first preset annealing temperature, which is in the range of 500~700℃. and / or S33: A second stress adjustment layer 104 is formed on a substrate having a first stress adjustment layer 103 to obtain a pre-substrate c with a double stress adjustment layer; S34: Anneal the prepared substrate c with the double stress adjustment layer to obtain a substrate with the double stress adjustment layer. The annealing temperature during the annealing process shall not be higher than the second preset annealing temperature, which is in the range of 800~1000℃.

[0107] Specifically, the annealing process is carried out under an inert atmosphere. Specifically, the inert atmosphere can be nitrogen.

[0108] Specifically, the first preset annealing temperature is 600°C, and the second preset annealing temperature is 900°C. By limiting the above annealing temperatures, it is ensured that unstable defects introduced by deposition can be effectively eliminated, the film can be densified, and the intrinsic stress of the second stress adjustment layer 104 can be kept within a stable range.

[0109] In some embodiments, before forming a piezoelectric heterostructure after bonding the piezoelectric thin film to the substrate having the first stress adjustment layer 103 via the second stress adjustment layer 104, the method further includes: The bonded substrate is post-processed to obtain a piezoelectric heterostructure.

[0110] In some embodiments, the post-processing includes: performing high-temperature annealing on the bonded heterostructure to cause the piezoelectric film to fall off along the defect layer, resulting in a pre-treated heterostructure; and performing planarization on the pre-treated heterostructure to obtain a piezoelectric heterostructure. When the piezoelectric film forms a defect layer through ion implantation, high-temperature annealing is required to cause the piezoelectric film to fall off along the defect layer.

[0111] In some embodiments, post-processing includes thinning and planarizing the bonded heterostructure to obtain a piezoelectric heterostructure. When the piezoelectric film is bonded to the substrate by direct bonding, only thinning and planarization are required.

[0112] The piezoelectric heterostructure prepared by the above-described method of the present invention has a first stress adjustment layer 103 and a second stress adjustment layer 104. The thermal expansion coefficient of the second stress adjustment layer 104 is limited to be less than that of the first stress adjustment layer 103 and the piezoelectric thin film layer 102. This can actively counteract the stress from the piezoelectric thin film layer 102, avoiding the problem that the brittle-brittle interface formed between the silicon substrate and the silicon dioxide layer cannot release energy through plastic deformation under thermal stress, thus easily causing stress concentration. This improves the reliability of the device, and the prepared device has a longer lifespan under thermal cycling and power aging. At the same time, it can also improve the frequency consistency of the acoustic wave device. The low warpage can make the lithographic linewidth uniform, and the center frequency deviation of the obtained filter is small, which improves the yield to a certain extent. It also increases the power energy and makes the electromigration tolerance of the low-stress metal electrode higher.

[0113] The foregoing description has fully disclosed the specific embodiments of this application. It should be noted that any modifications made by those skilled in the art to the specific embodiments of this application do not depart from the scope of the claims. Accordingly, the scope of the claims of this application is not limited to the foregoing specific embodiments.

Claims

1. A piezoelectric heterostructure, characterized in that, include: Substrate layer; piezoelectric thin film layer; A first stress-adjusting layer is disposed on the side of the piezoelectric thin film layer near the substrate layer; A second stress-adjusting layer is disposed between the piezoelectric thin film layer and the first stress-adjusting layer. The coefficient of thermal expansion of the second stress-adjusting layer is less than that of the first stress-adjusting layer and the piezoelectric thin film layer. The first stress-adjusting layer is used to apply compressive stress to the second stress-adjusting layer to generate tensile stress within the second stress-adjusting layer. The tensile stress is opposite in direction to the compressive stress generated by the tensile stress applied to the second stress-adjusting layer by the piezoelectric thin film layer.

2. The piezoelectric heterostructure according to claim 1, characterized in that, The coefficient of thermal expansion of the first stress-adjusting layer is less than or equal to the coefficient of thermal expansion of the piezoelectric thin film layer.

3. The piezoelectric heterostructure according to claim 2, characterized in that, The piezoelectric heterostructure further includes a metal layer disposed between the piezoelectric thin film layer and the second stress-adjusting layer, wherein the coefficient of thermal expansion of the first stress-adjusting layer is smaller than that of the metal layer.

4. The piezoelectric heterostructure according to claim 3, characterized in that, The piezoelectric heterosubstrate satisfies at least one of the following characteristics: The ratio between the thermal expansion coefficient of the second stress-adjusting layer and the thermal expansion coefficient of the first stress-adjusting layer ranges from 0.1 to 0.

5. The ratio between the thermal expansion coefficient of the second stress-adjusting layer and the thermal expansion coefficient of the piezoelectric thin film layer ranges from 0.03 to 0.

3. The ratio between the thermal expansion coefficient of the second stress-adjusting layer and the thermal expansion coefficient of the metal layer ranges from 0.02 to 0.

2.

5. The piezoelectric heterostructure according to claim 3, characterized in that, The piezoelectric heterosubstrate satisfies at least one of the following characteristics: The coefficient of thermal expansion of the first stress-adjusting layer ranges from 2.5 to 5.0 ppm / k; The material of the first stress-adjusting layer is polycrystalline silicon and / or amorphous silicon, wherein the grain size of the polycrystalline silicon ranges from 5 to 500 nm; The coefficient of thermal expansion of the second stress-adjusting layer ranges from 0.5 to 3.5 ppm / k; The material of the second stress-adjusting layer is silicon oxide and / or silicon nitride; The coefficient of thermal expansion of the piezoelectric thin film layer ranges from 4.0 to 16.5 ppm / k; The material of the piezoelectric thin film layer includes at least one of lithium niobate, lithium tantalate, and aluminum nitride. The coefficient of thermal expansion of the metal layer ranges from 4.5 to 23.0 ppm / k; The material of the metal layer includes at least one of gold, silver, copper, aluminum, nickel, platinum, titanium, tantalum, tungsten, chromium and molybdenum; The substrate material includes at least one of silicon oxide, quartz, sapphire, silicon carbide, silicon nitride, gallium nitride, and diamond.

6. The piezoelectric heterostructure according to claim 1, characterized in that, The piezoelectric heterosubstrate satisfies at least one of the following characteristics: The ratio between the thickness of the first stress-adjusting layer and the thickness of the second stress-adjusting layer ranges from 1.5 to 20. The ratio between the thickness of the first stress-adjusting layer and the thickness of the second stress-adjusting layer ranges from 0.05 to 1.

5.

7. The piezoelectric heterostructure according to claim 3, characterized in that, The piezoelectric heterosubstrate satisfies at least one of the following characteristics: The thickness of the first stress-adjusting layer ranges from 150 to 3000 nm; The thickness of the second stress-adjusting layer ranges from 100 to 2000 nm; The thickness of the second stress-adjusting layer ranges from 2000 to 40000 nm; The thickness of the piezoelectric thin film layer ranges from 100 nm to 10000 nm; The thickness of the metal layer ranges from 10 nm to 100 nm; The thickness of the substrate layer ranges from 200um to 1000um.

8. The piezoelectric heterostructure according to claim 1, characterized in that, The piezoelectric heterosubstrate satisfies at least one of the following characteristics: The intrinsic stress of the first stress-adjusting layer is compressive stress; The intrinsic stress of the second stress-adjusting layer is compressive stress or tensile stress.

9. The piezoelectric heterostructure according to any one of claims 1-8, characterized in that, The piezoelectric heterostructure further includes a third stress-adjusting layer and a fourth stress-adjusting layer, wherein the first stress-adjusting layer and the third stress-adjusting layer are symmetrically distributed based on the substrate layer, and the second stress-adjusting layer and the fourth stress-adjusting layer are symmetrically distributed based on the substrate layer; The thermal expansion coefficient of the fourth stress-adjusting layer is less than that of the third stress-adjusting layer and the piezoelectric thin film layer. The thermal expansion coefficient of the third stress-adjusting layer is less than or equal to that of the piezoelectric thin film layer.

10. A method for preparing a piezoelectric heterosubstrate as described in any one of claims 1-9, characterized in that, The preparation method includes: S1: Provide a substrate; S2: A first stress-adjusting layer is formed on the substrate to obtain a substrate having the first stress-adjusting layer; S3: The piezoelectric thin film is bonded to the substrate having the first stress adjustment layer through the second stress adjustment layer to form the piezoelectric heterostructure; the first stress adjustment layer is disposed on the side of the piezoelectric thin film layer near the substrate layer; The second stress-adjusting layer is disposed between the piezoelectric thin film layer and the first stress-adjusting layer. The coefficient of thermal expansion of the second stress-adjusting layer is less than that of the first stress-adjusting layer and the piezoelectric thin film layer. The first stress-adjusting layer is used to apply compressive stress to the second stress-adjusting layer to generate tensile stress within the second stress-adjusting layer. The tensile stress is opposite in direction to the compressive stress generated by the tensile stress applied to the second stress-adjusting layer by the piezoelectric thin film layer.

11. The method for preparing a piezoelectric heterosubstrate according to claim 10, characterized in that, The method further includes: The piezoelectric thin film is bonded to the substrate having the first stress adjustment layer by a metal layer and the second stress adjustment layer to form the piezoelectric heterostructure substrate; in the piezoelectric heterostructure substrate, the metal layer is disposed between the piezoelectric thin film layer and the second stress adjustment layer, and the coefficient of thermal expansion of the first stress adjustment layer is smaller than the coefficient of thermal expansion of the metal layer.

12. The method for preparing a piezoelectric heterosubstrate according to claim 10, characterized in that, Before bonding the piezoelectric thin film to the substrate having the first stress-adjusting layer via the second stress-adjusting layer, the method further includes: S31: Form the second stress-adjusting layer on the piezoelectric film to obtain a pre-piezoelectric film having the second stress-adjusting layer; S32: Anneal the piezoelectric film with the second stress adjustment layer to obtain a piezoelectric film with the second stress adjustment layer. The annealing temperature during the annealing process is not higher than the first preset annealing temperature, which is in the range of 500~700℃. and / or S33: A second stress-adjusting layer is formed on the substrate having the first stress-adjusting layer to obtain a pre-substrate having a double stress-adjusting layer; S34: Anneal the prepared substrate with the double stress adjustment layer to obtain a substrate with the double stress adjustment layer. The annealing temperature during the annealing process is not higher than the second preset annealing temperature, which is in the range of 800~1000℃.

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