Wafer cutting method

Abstract

The embodiment of the invention provides a wafer cutting method. The wafer cutting method comprises the following steps: firstly, integrally cutting a wafer; the plurality of target chips adhered with the metal residues are picked out; a plurality of target chips are placed on a cutting machine, a manual cutting mode is selected, and cutting parameters are adjusted; moving the lens to the current target chip, and performing horizontal calibration on the current target chip; and adjusting the cutting base line to be aligned with the edge of the current target chip, translating the cutting base line outwards by a preset offset, and then performing supplementary cutting along the cutting base line by adopting a cutting knife to remove metal residues on the current target chip. According to the method, the metal residues of the target chip can be effectively removed on the premise that the functional structure of the chip is not damaged, the industrial technical bottleneck that the target chip is judged as a defective product when the metal residues are detected traditionally is broken through, fine repair of the chip adhered with the metal residues is achieved, the defective product is converted into a good product, and the production efficiency is improved. And the yield and the output quantity of final products are remarkably improved, the product loss is reduced, and the cost is saved.

Description

Technical Field

[0001] This disclosure pertains to the field of wafer dicing technology, specifically relating to a wafer dicing method. Background Technology

[0002] As semiconductor process standards become increasingly stringent, the requirements for chip design are also becoming more stringent. More and more customers are laying dielectric materials or metal support blocks on the dicing kerf. If the dimensions of these metal materials are not properly designed, it will be difficult to select a suitable dicing blade, and metal residue is easily generated during the dicing process. Because the metal support blocks laid on the dicing kerf lack passivation layer protection in the corresponding test component groups of the front-end wafer fab, the metal support blocks are easily lifted by the blade when dicing to this area. If the blade is not selected properly or the dicing position is off-center, metal residue is very likely to occur. Metal residue on the dicing kerf affects terminal leakage current and is difficult to handle after AOI detection, resulting in a rejection and yield loss. Long-term low yield will affect customer confidence and reduce factory efficiency.

[0003] To address the aforementioned problems, it is necessary to propose a well-designed wafer dicing method that effectively solves these issues. Summary of the Invention

[0004] The present disclosure aims to at least solve one of the technical problems existing in the prior art and provide a wafer dicing method.

[0005] This disclosure provides a wafer dicing method, the method comprising: Step 1: Place the wafer on the dicing machine and cut it along the dicing path with a dicing blade to obtain multiple chips. During the dicing process, metal support blocks are laid on the dicing path. Step 2: Select multiple target chips with metal residues from the multiple chips after cutting, and then attach the multiple target chips to the blue film in sequence at intervals; Step 3: Place the blue film with multiple target chips attached onto the cutting machine, select manual cutting mode and adjust the cutting parameters; Step 4: Move the lens to the target chip and perform horizontal calibration on the target chip; Step 5: Adjust the cutting baseline to align with the edge of the target chip. Shift the cutting baseline outward by a preset offset, and then use a cutting blade to make additional cuts along the cutting baseline to remove any metal residue on the target chip.

[0006] Optionally, the preset offset in step five is calculated according to the following formula: Y = (WM) / 2 + D / 2 - 2; Wherein, Y represents the preset offset, W represents the width of the wafer dicing channel, D is the width of the dicing blade, and M is the width of the metal support block.

[0007] Optionally, after removing any metal residue from the target chip, the method further includes: The target chip is subjected to visual inspection. If there is still metal residue on the edge of the target chip, the preset offset is reduced. Then, steps four and five are repeated until all metal residue on the target chip is removed.

[0008] Optionally, after all metal residues in the target chip have been removed, the method further includes: The metal target chip described next is re-horizontally calibrated, the position of the cutting baseline is readjusted, and then a second cutting is performed to remove metal residue.

[0009] Optionally, in step two, multiple target chips with adhering metal residues are selected from the multiple chips after cutting, including: A chip picker is used to remove multiple target chips that are determined to have metal residue adhering to them from among the multiple chips.

[0010] Optionally, in step two, multiple target chips are sequentially and spaced apart and adhered onto the blue film, including: Multiple target chips are placed on a tray, and the tray carrying the target chips is flipped over using a jig so that the back of the target chips is facing up. Lay the tray flat, cover the tray with an empty blue film, and then rub the film to make the target chips adhere to the blue film; After flipping the blue film, carefully remove the tray so that the multiple target chips are arranged flat and spaced on the blue film.

[0011] Optionally, multiple target chips are arranged in a row at equal intervals.

[0012] Optionally, after completing the recutting of multiple target chips, the method further includes: The target chips are cleaned and dried, and then separated from the blue film.

[0013] Optionally, step four involves moving the lens to the target chip and performing horizontal calibration on the target chip, including: Reduce the reference area for horizontal adjustment to 25%~30% of the lens's field of view; Align the horizontal baseline with the edge of the current target chip to perform horizontal calibration of the individual target chip.

[0014] Optionally, in step three, select manual cutting mode and adjust the cutting parameters, including: Select the manual cutting mode, adjust the program to Z1 mode, and set the cutting depth, horizontal confirmation range, and other preset cutting parameters.

[0015] The wafer dicing method of this disclosure first dices the wafer as a whole; then, it picks out multiple target chips with adhering metal residue; it places the multiple target chips on a dicing machine, selects the manual dicing mode, and adjusts the dicing parameters; it moves the lens to the current target chip and performs horizontal calibration on the current target chip; it adjusts the dicing baseline to align with the edge of the current target chip, shifts the dicing baseline outward by a preset offset, and then uses a dicing blade to perform supplementary dicing along the dicing baseline to remove the metal residue on the current target chip. This wafer dicing method can effectively remove metal residue from target chips without damaging the chip's functional structure, breaking through the industry technical bottleneck of traditionally judging products as defective upon detecting metal residue. It achieves refined repair of chips with adhering metal residue, transforming defective products into good products, significantly improving the yield and output of the final product, reducing product losses due to yield issues, and saving costs. Attached Figure Description

[0016] Figure 1 This is a schematic flowchart of a wafer dicing method according to one embodiment of the present disclosure; Figure 2 To narrow down the range of the arrangement relationship of multiple target chips and the reference area for horizontal adjustment in another embodiment of this disclosure; Figure 3 This is a schematic diagram illustrating the individual horizontal calibration of different target chips in another embodiment of this disclosure; Figure 4 This is a schematic diagram illustrating the process of determining the preset offset in another embodiment of this disclosure; Figure 5 This is a schematic diagram of the front and back collapse conditions of an IC chip with metal residue after being cut using the wafer cutting method provided in this embodiment of the present disclosure in another embodiment of the present disclosure. Figure 6 This is a schematic diagram illustrating the reliability value of an IC chip with metal residue after being cut using the wafer cutting method provided in this embodiment of the present disclosure in another embodiment. Detailed Implementation

[0017] To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0018] like Figure 1As shown, this embodiment of the present disclosure provides a wafer dicing method S100, which specifically includes: Step 1: Place the wafer on the dicing machine and use a dicing blade to cut along the wafer dicing track to obtain multiple chips. During the dicing process, metal support blocks are laid on the dicing track.

[0019] Specifically, a wafer is placed on a dicing machine, where metal support blocks are laid on the wafer dicing track. A dicing blade cuts along the wafer dicing track to obtain multiple chips. Due to the presence of the metal support blocks, metal residue forms on the edges of some chips during dicing, affecting chip yield. Therefore, chips with metal residue need to be re-diced to remove the metal residue from the chip edges.

[0020] Step 2: Select multiple target chips with metal residues from the multiple chips after cutting, and then attach the multiple target chips to the blue film in sequence at intervals.

[0021] Specifically, step two may include: S21. Use a chip picker to remove multiple target chips that are determined to have metal residue adhering to them from among the multiple chips.

[0022] S22. Place multiple target chips on a tray, and use a jig to flip the tray carrying the target chips so that the back of the target chips faces upward.

[0023] S23. Lay the tray flat, cover the tray with an empty blue film, and then rub the film to make the target chips adhere to the blue film.

[0024] S24. After flipping the blue film, carefully remove the tray so that multiple target chips are arranged flat and spaced on the blue film. This ensures that the chips remain stable, flat and spaced on the blue film, laying a crucial physical foundation for the subsequent precise positioning and recutting by the cutting machine, and preventing the chips from shifting or overlapping during the processing.

[0025] Among them, such as Figure 2 As shown, multiple target chips are arranged in a row at equal intervals. The linear and regular arrangement of multiple target chips makes the movement of the lens and the stepping path of the cutting table simple and predictable, reducing the idle time and repeated alignment time when the equipment moves between target chips. It is particularly suitable for batch continuous manual or semi-automatic recutting operations, thereby improving the overall production efficiency.

[0026] Step 3: Place the blue film with multiple target chips attached onto the cutting machine, select the manual cutting mode, and adjust the cutting parameters.

[0027] Specifically, step three may include: The blue film with multiple target chips attached is placed on the cutting machine. The manual cutting mode is selected, the program is adjusted to Z1 mode, and the cutting depth, horizontal confirmation range, and other preset cutting parameters are set. These preset cutting parameters may include cutting speed, feed rate, etc.

[0028] Specifically, in this embodiment, the blade height is calculated according to H=D / 2+J, where H is the height of the blade from the tray, D is the target chip thickness, and J is the adhesive film thickness. With a target chip thickness of 170 μm and an adhesive film thickness of 90 μm, the blade height should be set to 175 μm.

[0029] Step 4: Move the lens to the target chip and perform horizontal calibration on the target chip.

[0030] Specifically, step four may include: S41. Move the lens to the current target chip, and reduce the horizontally adjusted reference area to 25%~30% of the lens's field of view. Specifically, as follows... Figure 2 As shown, in this embodiment, the reference area for horizontal adjustment is reduced to 25% of the area within the lens's field of view. In other words, by placing multiple target chips at the center of the lens's field of view, the location of metal residue on the target chips can be better observed, and it is easier to perform horizontal calibration on each target chip.

[0031] S42. Align the horizontal baseline with the edge of the current target chip and perform horizontal calibration on the individual target chip.

[0032] Specifically, because each target chip may shift during the film application process, it is necessary to adjust the level of each target chip individually. Individual level calibration of each target chip overcomes the overall calibration error caused by uneven blue film or slight differences in chip thickness, resulting in extremely high precision in the recutting and positioning of individual target chips and ensuring that the recutting process does not damage the functional areas of the chip.

[0033] Step 5: Adjust the cutting baseline to align with the edge of the target chip. Shift the cutting baseline outward by a preset offset, and then use a cutting blade to make additional cuts along the cutting baseline to remove any metal residue on the target chip.

[0034] The preset offset in step five is calculated according to the following formula: Y = (WM) / 2 + D / 2 - 2; Wherein, Y represents the preset offset, W represents the width of the wafer dicing channel, D is the width of the dicing blade, and M is the width of the metal support block.

[0035] Specifically, the adjustment of the cutting baseline should be as follows: Figure 4 As shown, during normal wafer dicing, the dicing reference line should be aligned with the center of the dicing path. When dicing metal residue, the dicing reference line should be aligned with the edge of the target chip to be diced, where metal residue is adhered. Figure 4 Metal residue is present on the upper edge of the target chip in the lower middle part; this target chip is the current target chip.

[0036] Because the actual cutting marks will be slightly wider than the actual blade width, the cutting baseline needs to be shifted outward by a preset offset to align with the edge of the target chip, leaving a safety margin. The preset offset should be calculated according to the formula above. After calculating the normal single-sided preset allowance, it should be adjusted by an additional 2 μm based on experience. Taking a wafer dicing width of 60 μm, a metal support block width of 40 μm, and a cutting blade width of 46 μm as an example, the actual blade landing position should be at (60-40) / 2+46 / 2-2=31μm. After aligning the cutting baseline with the upper edge of the target chip below, move it upward by 31μm. The actual landing position is at this point to start cutting, ensuring that the metal residue of the current target chip is effectively removed and the sealing ring of the target chip is not damaged.

[0037] In this embodiment, a precise calculation formula is provided for the preset offset during dicing, realizing the scientific quantitative setting of the dicing path and avoiding the uncertainty and poor consistency problems caused by manual wafer estimation. By determining the dicing position through this preset offset formula, it is possible to ensure that metal residues are removed while protecting the functional areas of the target chip from damage to the maximum extent, thereby improving the accuracy, repeatability and yield of dicing.

[0038] For example, after removing metal residues from the target chip, the method further includes: The target chip is subjected to visual inspection. If there is still metal residue on the edge of the target chip, the preset offset is reduced. Then, steps four and five are repeated until all metal residue on the target chip is removed.

[0039] Specifically, after recutting the target chip, observe the cutting process. For example, confirm whether the cutting baseline matches the actual cutting position, and whether the recutting has eliminated metal residue without damaging the sealing ring of the target chip. If metal residue remains on the edge of the target chip, reduce the preset offset, and then repeat steps four and five to recalibrate and adjust the position of the cutting baseline. Perform recutting again, observing after each recutting until all metal residue on the target chip is completely removed.

[0040] In this embodiment, through a cycle of recutting-observation-adjustment, the preset offset can be fine-tuned (e.g., reduced) based on the actual cutting effect of the first cut. This enables the recutting process to cope with minor individual differences and uncertainties, ensuring that each target chip obtains the most suitable recutting parameters, thereby better removing metal residues.

[0041] For example, after all metal residues in the target chip have been removed, the method further includes: The metal target chip described next is re-horizontally calibrated, the position of the cutting baseline is readjusted, and then a second cutting is performed to remove metal residue.

[0042] Specifically, after completely removing the metal residue from the current target chip through recutting, the next target chip is then recut. That is, steps four and five are performed on the next target chip until all metal residue is removed. Figure 3 As shown, 3a is the horizontal calibration of the target chip when the first target chip is diced, 3b is the horizontal calibration of the target chip when the second target chip is diced, and 3c is the horizontal calibration of the target chip when the nth target chip is diced.

[0043] In this embodiment, by performing an independent recutting step on each target chip, the cumulative positioning error caused by uneven blue film tension and slight deviations in target chip placement during batch processing is overcome. By recalibrating the horizontal alignment and readjusting the cutting baseline for each target chip, it is ensured that the positioning for each recutting is based on the most accurate position information of that target chip at that time. This maximizes the guarantee that when multiple target chips are recut consecutively, each target chip can achieve the same positioning accuracy and cutting quality as the first target chip, realizing high stability and high repeatability of the recutting process.

[0044] For example, after completing the recutting of multiple target chips, the method further includes: Multiple target chips are cleaned and dried to remove contaminants such as silicon shavings and metal dust generated during the recutting process, ensuring the electrical reliability of the chips; and the multiple target chips are separated from the blue film to obtain chips that meet the requirements.

[0045] The wafer dicing method of this disclosure first dices the wafer as a whole; then, it picks out multiple target chips with adhering metal residue; it places the multiple target chips on a dicing machine, selects the manual dicing mode, and adjusts the dicing parameters; it moves the lens to the current target chip and performs horizontal calibration on the current target chip; it adjusts the dicing baseline to align with the edge of the current target chip, shifts the dicing baseline outward by a preset offset, and then uses a dicing blade to perform supplementary dicing along the dicing baseline to remove the metal residue on the current target chip. This wafer dicing method can effectively remove metal residue from target chips without damaging the chip's functional structure, breaking through the industry technical bottleneck of traditionally judging products as defective upon detecting metal residue. It achieves refined repair of chips with adhering metal residue, transforming defective products into good products, significantly improving the yield and output of the final product, reducing product losses due to yield issues, and saving costs.

[0046] like Figure 5 The diagram shown illustrates the front and back chipping conditions of an IC chip with metal residue after being diced using the wafer dicing method provided in this embodiment. Figure 5 It can be seen that the front and back collapse conditions of the IC chip with metal residue after recutting meet the customer's requirements.

[0047] like Figure 6 The diagram shown illustrates the reliability values ​​of an IC chip with metal residue after being cut using the wafer dicing method provided in this embodiment. Figure 6 It can be seen that the reliability value B10 of the IC chip with metal residue is 591.7, which meets the SPEC requirement of B10 > 350MPA.

[0048] In summary, IC chips with metal residues cut using the wafer dicing method provided in this disclosure meet the requirements for good products, reduce product loss, increase the number of good products, and increase the yield rate.

[0049] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the embodiments of this disclosure, and the embodiments of this disclosure are not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of this disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of this disclosure.

Claims

1. A wafer dicing method, characterized in that, The method includes: Step 1: Place the wafer on the dicing machine and cut it along the dicing path with a dicing blade to obtain multiple chips. During the dicing process, metal support blocks are laid on the dicing path. Step 2: Select multiple target chips with metal residues from the multiple chips after cutting, and then attach the multiple target chips to the blue film in sequence at intervals; Step 3: Place the blue film with multiple target chips attached onto the cutting machine, select manual cutting mode and adjust the cutting parameters; Step 4: Move the lens to the target chip and perform horizontal calibration on the target chip; Step 5: Adjust the cutting baseline to align with the edge of the target chip. Shift the cutting baseline outward by a preset offset, and then use a cutting blade to make additional cuts along the cutting baseline to remove any metal residue on the target chip.

2. The wafer dicing method according to claim 1, characterized in that, The preset offset in step five is calculated using the following formula: Y = (WM) / 2 + D / 2 - 2; Wherein, Y represents the preset offset, W represents the width of the wafer dicing channel, D is the width of the dicing blade, and M is the width of the metal support block.

3. The wafer dicing method according to claim 1, characterized in that, After removing any metal residue from the target chip, the method further includes: The target chip is subjected to visual inspection. If there is still metal residue on the edge of the target chip, the preset offset is reduced. Then, steps four and five are repeated until all metal residue on the target chip is removed.

4. The wafer dicing method according to claim 1, characterized in that, After all metal residues in the target chip have been removed, the method further includes: The metal target chip described next is re-horizontally calibrated, the position of the cutting baseline is readjusted, and then a second cutting is performed to remove metal residue.

5. The wafer dicing method according to claim 1, characterized in that, Step two involves selecting multiple target chips with adhering metal residues from the cut chips, including: A chip picker is used to remove multiple target chips that are determined to have metal residue adhering to them from among the multiple chips.

6. The wafer dicing method according to claim 5, characterized in that, Step two involves sequentially and at intervals attaching multiple target chips onto the blue film, including: Multiple target chips are placed on a tray, and the tray carrying the target chips is flipped over using a jig so that the back of the target chips is facing up. Lay the tray flat, cover the tray with an empty blue film, and then rub the film to make the target chips adhere to the blue film; After flipping the blue film, carefully remove the tray so that the multiple target chips are arranged flat and spaced on the blue film.

7. The wafer dicing method according to claim 1, characterized in that, Multiple target chips are arranged in a row at equal intervals.

8. The wafer dicing method according to claim 1, characterized in that, After completing the recutting of multiple target chips, the method further includes: The target chips are cleaned and dried, and then separated from the blue film.

9. The wafer dicing method according to claim 1, characterized in that, Step four involves moving the lens to the target chip and performing horizontal calibration on the target chip, including: Reduce the reference area for horizontal adjustment to 25%~30% of the lens's field of view; Align the horizontal baseline with the edge of the current target chip to perform horizontal calibration of the individual target chip.

10. The wafer dicing method according to claim 1, characterized in that, Step 3: Select manual cutting mode and adjust cutting parameters, including: Select the manual cutting mode, adjust the program to Z1 mode, and set the cutting depth, horizontal confirmation range, and other preset cutting parameters.

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