Semiconductor device

Abstract

A semiconductor device may include: a substrate including a front surface and a back surface opposite to each other; a first transistor disposed on the front surface of the substrate, the first transistor including a first gate electrode and a first source / drain pattern adjacent to both sides of the first gate electrode; a first interlayer insulating layer on the first transistor; a first front-side detection structure disposed on the first interlayer insulating layer and connected to the first gate electrode; a first backside detection structure adjacent to the backside of the substrate; and a first through detection structure connecting the first front side detection structure to the first rear side detection structure. The first through detection structure may include a front side contact through the first interlayer insulating layer and a first back side contact through a portion of the substrate.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2024-0160507, filed on November 12, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor device and a method for detecting faults in the semiconductor device. Background Technology

[0004] Semiconductor devices include integrated circuits composed of metal-oxide-semiconductor field-effect transistors (MOS-FETs). To meet the increasing demand for semiconductor devices with smaller pattern sizes and simplified design rules, MOS-FETs are being aggressively miniaturized. As MOSFETs shrink, defects or faults may appear in semiconductor devices. Fault analysis is widely used in the semiconductor industry to detect defects or faults in semiconductor devices (e.g., integrated circuits). However, as semiconductor device designs become more complex, detecting defects or faults becomes increasingly difficult. Summary of the Invention

[0005] Some embodiments of the present invention provide a semiconductor device configured to easily detect defects or faults in a semiconductor device.

[0006] Some embodiments of the present invention provide a method for easily detecting faults in a semiconductor device.

[0007] According to some embodiments of the present invention, a semiconductor device may include: a substrate including a front side and a back side opposite to each other; a first transistor adjacent to the front side of the substrate, the first transistor including a first gate electrode and first source / drain patterns on both sides adjacent to the first gate electrode; a first interlayer insulating layer disposed on the first transistor; a first front-side detection structure disposed on the first interlayer insulating layer and connected to the first gate electrode; a first rear-side detection structure adjacent to the back side of the substrate; and a first through-detection structure connecting the first front-side detection structure to the first rear-side detection structure. The first through-detection structure may include a front-side contact penetrating the first interlayer insulating layer and a first rear-side contact penetrating a portion of the substrate.

[0008] According to some embodiments of the present invention, a semiconductor device may include: a substrate including a front side and a back side opposite to each other; a first transistor adjacent to the front side of the substrate, the first transistor including a first gate electrode and first source / drain patterns on both sides adjacent to the first gate electrode; a second transistor adjacent to the front side of the substrate, the second transistor including a second gate electrode and second source / drain patterns on both sides adjacent to the second gate electrode; a first interlayer insulating layer disposed on the first transistor; a first front-side detection structure disposed on the first interlayer insulating layer and connected to the first gate electrode; a second front-side detection structure disposed on the first interlayer insulating layer and connected to the second gate electrode; a first rear-side detection structure adjacent to the back side of the substrate; a first through-hole member penetrating the first interlayer insulating layer and the substrate, and connecting the first front-side detection structure to the first rear-side detection structure; a second rear-side detection structure adjacent to the back side of the substrate; and a second through-hole member penetrating the first interlayer insulating layer and the substrate, and connecting the second front-side detection structure to the second rear-side detection structure. A first horizontal level at the lower end of the first rear-side detection structure may be the same as a second horizontal level at the lower end of the second rear-side detection structure.

[0009] According to some embodiments of the present invention, a semiconductor device may include: a substrate including a front side and a back side opposite to each other; a trigger circuit adjacent to the front side of the substrate; a first transistor adjacent to the front side of the substrate, the first transistor including a first gate electrode and first source / drain patterns on both sides adjacent to the first gate electrode, the first transistor being included in the trigger circuit; a first interlayer insulating layer disposed on the first transistor; a first front-side detection structure disposed on the first interlayer insulating layer and connected to the first gate electrode; a first rear-side detection structure adjacent to the back side of the substrate; a first through-detection structure connecting the first front-side detection structure to the first rear-side detection structure; a power line adjacent to the back side of the substrate; and a rear-side interconnect structure connected to the power line. The first through-detection structure may include a front-side contact penetrating the first interlayer insulating layer, a first rear-side contact penetrating a portion of the substrate, and a connecting conductive pattern between the front-side contact and the first rear-side contact. The connecting conductive pattern and the first source / drain pattern may be doped with the same dopant.

[0010] According to some embodiments of the present invention, a method for detecting faults in a semiconductor device may include: obtaining a semiconductor device comprising a trigger circuit disposed on a substrate, a front-side detection structure connected to the trigger circuit, a rear-side detection structure adjacent to the back side of the substrate, and a through-detection structure penetrating the substrate and connecting the front-side detection structure to the rear-side detection structure; and irradiating the lower end of the rear-side detection structure with an electron beam to detect faults in the trigger circuit. In some embodiments, the semiconductor device further includes a power line adjacent to the back side of the substrate and a rear-side interconnect structure connected to the power line, wherein the lower end of the rear-side detection structure is higher than the lower end of the rear-side interconnect structure. The method may further include: partially removing the rear portion of the semiconductor device before irradiating the electron beam to expose the lower end of the rear-side detection structure. Attached Figure Description

[0011] Figure 1 This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention.

[0012] Figures 2A to 2C It is shown Figure 1 A magnified view of part "P1".

[0013] Figure 3 This is a cross-sectional view illustrating some embodiments of a transistor according to a concept conceived in this invention.

[0014] Figure 4A and Figure 4B It is shown Figure 1 A magnified view of part "P2".

[0015] Figure 5 It shows the detection Figure 1 A schematic diagram of a method for troubleshooting in a semiconductor device.

[0016] Figure 6A This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention.

[0017] Figure 6B It shows the detection Figure 6A A schematic diagram of a method for troubleshooting in a semiconductor device.

[0018] Figure 7A This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention.

[0019] Figure 7B and Figure 7C It is shown Figure 7A A plan view of a portion of a semiconductor device.

[0020] Figure 8 It shows the detection Figure 7A A schematic diagram of a method for troubleshooting in a semiconductor device.

[0021] Figure 9 This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention.

[0022] Figure 10 This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention.

[0023] Figure 11 This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention.

[0024] Figure 12 This is a conceptual diagram illustrating some embodiments of a semiconductor device according to the present invention. Detailed Implementation

[0025] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments are illustrated. In this specification, terms indicating order, such as first, second, etc., are used to distinguish components having the same or similar functions from one another, and the numbering may vary according to the order in which they are mentioned.

[0026] According to some embodiments of the present invention, electron beam fault isolation (EFI) can be performed via the back side of a semiconductor device using a rear-side detection structure. The detection structure described herein is less complex because it involves fewer metal layers and is easier to manufacture. For example, rear-side fault detection according to some embodiments may omit the use of a support wafer.

[0027] It should be noted that the rear-side detection structure described herein is not limited to use in conjunction with electron beam fault isolation, but can be used with other types of techniques for testing semiconductor devices.

[0028] Figure 1 This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention. Figures 2A to 2C It is shown Figure 1 A magnified view of part "P1". Figure 3 This is a cross-sectional view illustrating some embodiments of a transistor according to a concept conceived in this invention. Figure 3 It is cut along the length direction D1. Figure 1 A cross-sectional view of the gate electrode of a transistor. Figure 4A and Figure 4B It is shown Figure 1 A magnified view of part "P2".

[0029] Reference Figure 1 , Figure 2A and Figure 4AThe semiconductor device 1000 according to the present embodiment may include a substrate 100. The substrate 100 may be a semiconductor substrate or compound semiconductor substrate formed of silicon, germanium, or silicon-germanium, or it may be an insulating substrate formed of an insulating material (e.g., silicon oxide). The substrate 100 may include a front side 100F and a back side 100B opposite to each other.

[0030] Transistor TR may be adjacent to the front side 100F of substrate 100. Thus, transistor TR may be closer to the front side 100F than the back side 100B. Each of transistors TR may include a gate electrode GE, source / drain patterns SD on both sides of the gate electrode GE, and a channel pattern CH between the source / drain patterns SD. Transistor TR may include a first transistor TR (1) and a second transistor TR (2). The first transistor TR (1) may include a first gate electrode GE (1), a first source / drain pattern SD (1) adjacent to both sides of the first gate electrode GE (1), and a first channel pattern CH (1) between the first source / drain patterns SD (1). The second transistor TR (2) may include a second gate electrode GE (2), a second source / drain pattern SD (2) adjacent to both sides of the second gate electrode GE (2), and a second channel pattern CH (2) between the second source / drain patterns SD (2).

[0031] The transistor TR can be configured as a multi-bridge channel FET (MBCFET), but the inventive concept is not limited to this example. For example, the transistor TR can be configured as a planar FET, FinFET, vertical FET, buried channel array transistor (BCAT), or gate all-around FET (GAAFET).

[0032] An active pattern AP can be defined by a trench TC formed in the upper portion of the substrate 100. The active pattern AP can be a vertically projecting portion of the substrate 100. In some embodiments, multiple active pattern APs can be provided. Some of the active pattern APs can be located in a PMOSFET region, while others can be located in an NMOSFET region. A device isolation layer ST can be provided to fill the trench TC. The device isolation layer ST can include a silicon oxide layer. The device isolation layer ST may not cover the channel pattern CH, which will be described below.

[0033] Reference Figure 3 The channel pattern CH can be disposed on one of the active patterns AP. The channel pattern CH may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked sequentially. The first semiconductor pattern to the third semiconductor pattern SP1, SP2, and SP3 may be spaced apart from each other in the vertical direction (i.e., the third direction D3).

[0034] Reference Figure 2A and Figure 3Each of the first to third semiconductor patterns SP1, SP2, and SP3 may be formed of or include at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe). For example, each of the first to third semiconductor patterns SP1, SP2, and SP3 may be formed of or include polycrystalline silicon. In some embodiments, each of the first to third semiconductor patterns SP1, SP2, and SP3 may be a nanosheet.

[0035] Reference Figure 2A A first source / drain pattern SD(1) may be disposed on both sides of a first channel pattern CH(1). A plurality of first grooves RS1 may be formed in the upper part of the substrate 100. The first source / drain pattern SD(1) may be disposed in the first grooves RS1 respectively. The first source / drain pattern SD(1) may be an impurity region of a first conductivity type (e.g., p-type). The stacked first semiconductor patterns to third semiconductor patterns SP1, SP2 and SP3 of the first channel pattern CH(1) may connect the first source / drain pattern SD(1) to each other.

[0036] Reference Figure 4A A second source / drain pattern SD(2) may be disposed on both sides of a second channel pattern CH(2). A plurality of second grooves RS2 may be formed in the upper part of the substrate 100. The second source / drain pattern SD(2) may be disposed in the second grooves RS2 respectively. The second source / drain pattern SD(2) may be an impurity region of a first conductivity type (e.g., p-type). The stacked first semiconductor pattern to third semiconductor pattern SP1, SP2 and SP3 of the second channel pattern CH(2) may connect the second source / drain pattern SD(2) to each other.

[0037] Reference Figure 3 The first gate electrode GE(1) may be configured to intersect the first channel pattern CH(1) and extend in the first direction D1. (Refer to...) Figure 4A The second gate electrode GE(2) may be configured to intersect the second channel pattern CH(2) and extend in the first direction D1. The first gate electrode GE(1) and the second gate electrode GE(2) may be vertically overlapped with the first channel pattern CH(1) and the second channel pattern CH(2), respectively.

[0038] Reference Figure 3Each of the first gate electrode GE(1) and the second gate electrode GE(2) may include a first inner electrode PO1 between the active pattern AP and the first semiconductor pattern SP1, a second inner electrode PO2 between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third inner electrode PO3 between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and an outer electrode PO4 on the third semiconductor pattern SP3.

[0039] Reference Figure 3 Each of the first gate electrode GE(1) and the second gate electrode GE(2) may be disposed on the top surface TS, the bottom surface BS and the opposite side surface SW of each of the first semiconductor pattern to the third semiconductor pattern SP1, SP2 and SP3.

[0040] Figure 2A , Figure 2C , Figure 4A and Figure 4B The first transistor TR(1) and the second transistor TR(2) may have a PMOSFET structure. Here, each of the first source / drain pattern SD(1) and the second source / drain pattern SD(2) may be formed or include at least one of Si, SiGe, SiGeB, Ge, InSb, GaSb and InGaSb.

[0041] For details, refer to Figure 2A and Figure 4A The first source / drain pattern SD(1) and the second source / drain pattern SD(2) can be epitaxial patterns formed by a selective epitaxial growth (SEG) process. In some embodiments, the top surface of each of the first source / drain pattern SD(1) and the second source / drain pattern SD(2) may be positioned at substantially the same level as the top surface of the third semiconductor pattern SP3. Alternatively, the top surface of each of the first source / drain pattern SD(1) and the second source / drain pattern SD(2) may be higher than the top surface of the third semiconductor pattern SP3.

[0042] The first source / drain pattern SD(1) may include a semiconductor material (e.g., SiGe) with a lattice constant greater than that of the substrate 100. In this case, the first source / drain pattern SD(1) may be configured to apply compressive stress to the first channel pattern CH(1) between the first source / drain patterns SD(1).

[0043] Each of the first source / drain patterns SD(1) may include a buffer layer BFL and a main layer MAL on the buffer layer BFL. (Refer to...) Figure 2A and Figure 4AThe buffer layer BFL may cover the inner surfaces of the first groove RS1 and the second groove RS2. In some embodiments, the buffer layer BFL may have a substantially conformal thickness. In another embodiment, the buffer layer BFL may have a decreasing thickness in the upward direction. The buffer layer BFL may be U-shaped due to the contours of the first groove RS1 and the second groove RS2.

[0044] The main layer MAL can fill most of the unfilled areas of the first groove RS1 and the second groove RS2, which are covered by the buffer layer BFL. The volume of the main layer MAL can be larger than the volume of the buffer layer BFL. Each of the buffer layer BFL and the main layer MAL can be formed of or include silicon germanium (SiGe). Specifically, the buffer layer BFL can contain a relatively low concentration of germanium (Ge). In another embodiment, the buffer layer BFL can contain only silicon (Si) and no germanium (Ge). The germanium concentration of the buffer layer BFL can be in the range of 0 at% to 10 at%.

[0045] The main layer MAL may contain a relatively high concentration of germanium (Ge). In some embodiments, the germanium concentration of the main layer MAL may be in the range of 30 at% to 70 at% . The germanium concentration of the main layer MAL may increase with increasing distance on the third-direction D3. For example, the main layer MAL adjacent to the buffer layer BFL may have a germanium concentration of about 40 at% , but the upper part of the main layer MAL may have a germanium concentration of about 60 at% .

[0046] Each of the buffer layer BFL and the main layer MAL may contain an impurity (e.g., boron, gallium, or indium) that causes the first source / drain pattern SD(1) and the second source / drain pattern SD(2) to have a p-type structure. The impurity concentration of each of the buffer layer BFL and the main layer MAL may be from 1E18 atom / cm3 to 5E22 atom / cm3. 3 Within a certain range. The impurity concentration of the main layer MAL can be higher than that of the buffer layer BFL.

[0047] The buffer layer BFL prevents stacking faults between the substrate 100 and the main layer MAL, and between the first to third semiconductor patterns SP1, SP2, and SP3 and the main layer MAL. Stacking faults increase channel impedance. The buffer layer BFL protects the main layer MAL during the fabrication of the semiconductor device 1000.

[0048] Alternatively, refer to Figure 2BThe first transistor TR(1) may have an NMOSFET structure. The second transistor TR(2) may also have an NMOSFET structure. Here, each of the first source / drain pattern SD(1) and the second source / drain pattern SD(2) may be formed or include at least one of Si, SiP, SiC, SiPC, InP, GaAs, AlAs, InAs, InAlAs and InGaAs.

[0049] As a specific example, refer to Figure 2B Each of the first source / drain pattern SD(1) and the second source / drain pattern SD(2) may be formed of or comprise the same semiconductor material (e.g., Si) as the substrate 100. Each of the first source / drain pattern SD(1) and the second source / drain pattern SD(2) may also contain an n-type impurity (e.g., phosphorus, arsenic, or antimony). The impurity concentration of the first source / drain pattern SD(1) and the second source / drain pattern SD(2) may be 1E18 atom / cm 3 Up to 5E22atom / cm 3 Within the range.

[0050] Reference Figure 2B In the case where the first transistor TR(1) and the second transistor TR(2) have an NMOSFET structure, the inner space IP can be located between the first inner electrode to the third inner electrode PO1, PO2 and PO3 of the first gate electrode GE(1) and the first source / drain pattern SD(1), respectively. Although not shown, the inner space IP can be located between the first inner electrode to the third inner electrode PO1, PO2 and PO3 of the second gate electrode GE(2) and the second source / drain pattern SD(2), respectively. The inner space IP can directly contact the first source / drain pattern SD(1). The inner space IP can directly contact the second source / drain pattern SD(2). Each of the first inner electrode to the third inner electrode PO1, PO2 and PO3 of the first gate electrode GE(1) can be spaced apart from the first source / drain pattern SD(1) by the inner space IP. Each of the first inner electrode to the third inner electrode PO1, PO2 and PO3 of the second gate electrode GE(2) can be spaced apart from the second source / drain pattern SD(2) by the inner space IP.

[0051] Reference Figure 2A and Figure 4AA pair of gate spacers GS may be respectively disposed on the opposite side surfaces of the external electrodes PO4 of each of the first gate electrode GE (1) and the second gate electrode GE (2). The gate spacers GS may extend along each of the first gate electrode GE (1) and the second gate electrode GE (2) and in a first direction D1. The top surface of the gate spacers GS may be higher than the top surface of each of the first gate electrode GE (1) and the second gate electrode GE (2). The top surface of the gate spacers GS may be coplanar with the top surface of the first interlayer insulating layer 110, which will be described below. The gate spacers GS may be formed of or include at least one of SiO2, SiON, SiCN, SiCON and SiN, and may have a single-layer or multi-layer structure.

[0052] A gate cap pattern GP may be disposed on each of the first gate electrode GE (1) and the second gate electrode GE (2). The gate cap pattern GP may extend along each of the first gate electrode GE (1) and the second gate electrode GE (2) and in a first direction D1. The gate cap pattern GP may comprise a material having etch selectivity relative to the first interlayer insulating layer 110 and the second interlayer insulating layer 120, which will be described below. In detail, the gate cap pattern GP may be formed of or include at least one of SiON, SiCN, SiCON, and SiN.

[0053] The gate insulating layer GI may be located between the first gate electrode GE (1) and the second gate electrode GE (2) and the first channel pattern CH (1) and the second channel pattern CH (2). The gate insulating layer GI may cover the top surface TS, the bottom surface BS, and the opposite side surface SW of each of the first to third semiconductor patterns SP1, SP2, and SP3. (Refer to...) Figure 3 The gate insulating layer GI can cover the top surface of the device isolation layer ST below each of the first gate electrode GE (1) and the second gate electrode GE (2).

[0054] In some embodiments, the gate insulating layer GI may include a silicon oxide layer, a silicon oxynitride layer, and / or a high-k dielectric layer. The high-k dielectric layer may be formed of or include at least one of high-k dielectric materials with a dielectric constant higher than that of silicon oxide. For example, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0055] Each of the first gate electrode GE(1) and the second gate electrode GE(2) may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be disposed on the gate insulating layer GI and may be adjacent to the first semiconductor pattern to the third semiconductor pattern SP1, SP2 and SP3. The first metal pattern may include a work function metal that can be used to adjust the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal pattern, a transistor with a desired threshold voltage can be realized. For example, the first inner electrode to the third inner electrode PO1, PO2 and PO3 of each of the first gate electrode GE(1) and the second gate electrode GE(2) may be composed of the first metal pattern or a work function metal.

[0056] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include a layer of at least one metallic material selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo) and nitrogen (N). In some embodiments, the first metal pattern may also include carbon (C). The first metal pattern may include a plurality of stacked work function metal layers.

[0057] The second metal pattern may be formed of or comprise a metal material with an impedance lower than that of the first metal pattern. For example, the second metal pattern may be formed of or comprise at least one metal material selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the external electrode PO4 of each of the first gate electrode GE (1) and the second gate electrode GE (2) may comprise the first metal pattern and the second metal pattern on the first metal pattern.

[0058] A first interlayer insulating layer 110 may be disposed on a substrate 100. The first interlayer insulating layer 110 may cover a gate spacer GS and a first source / drain pattern SD (1) and a second source / drain pattern SD (2). The top surface of the first interlayer insulating layer 110 may be substantially coplanar with the top surface of the gate cap pattern GP and the top surface of the gate spacer GS. A second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110 to cover the gate cap pattern GP. In some embodiments, each of the first interlayer insulating layer 110 and the second interlayer insulating layer 120 may include a silicon oxide layer.

[0059] The partition structure DB can be configured to separate cell areas from each other. Cell areas can be areas used for various logic cells (e.g., single-high cells (SHC) or double-high cells (DHC)) or for tap units. A logic cell can refer to a logic device configured to perform a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.). In other words, a logic cell may include transistors that construct the logic device and interconnects that connect the transistors to each other. Unlike logic cells, tap units may not include logic devices. That is, tap units may be configured to apply voltage to wires, but may simply be dummy units not used as circuit elements.

[0060] The separator structure DB can extend in the first direction D1 and parallel to the gate electrodes GE(1) and GE(2). The spacing between adjacent separator structures DB and gate electrodes GE(1) and GE(2) can be the same as the spacing between gate electrodes GE(1) and GE(2).

[0061] The separator structure DB can be configured to penetrate the first interlayer insulating layer 110 and extend into the substrate 100. The separator structure DB can electrically separate the active region of one cell region from the active region of another cell region adjacent to it.

[0062] Reference Figure 1 and Figure 2A An active contact AC may be provided, connected to at least one of the source / drain patterns SD. When viewed in a plan view, the active contact AC may be a strip pattern extending in a first direction D1. The active contact AC may be configured to penetrate the first interlayer insulation layer 110 and the second interlayer insulation layer 120.

[0063] The active contact AC can be a self-aligning contact. For example, the active contact AC can be formed using a gate cap pattern GP and a gate spacer GS via a self-aligning process. For example, the active contact AC can cover at least a portion of the side surface of the gate spacer GS.

[0064] A metal-semiconductor compound layer SC (e.g., a silicide layer) may be situated between an active contact AC and a source / drain pattern SD. The active contact AC can be electrically connected to one of the source / drain patterns SD via the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer SC may be formed of or include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0065] The gate contact GC can be configured to penetrate the second interlayer insulating layer 120 and the gate cap pattern GP, ​​and can be electrically connected to the gate electrode GE. The gate contact GC can be freely disposed on the gate electrode GE, and its position is not restricted.

[0066] The upper portion of the active contact AC adjacent to the gate contact GC can be filled with an upper insulating pattern UIP. The bottom surface of the upper insulating pattern UIP can be lower than the bottom surface of the gate contact GC. In other words, the top surface of the active contact AC adjacent to the gate contact GC can be formed at a level lower than the bottom surface of the gate contact GC by the upper insulating pattern UIP. Therefore, the gate contacts GC and active contacts AC that are adjacent to each other can be prevented from contacting each other, thus preventing short circuit problems between them.

[0067] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may be formed of or include at least one of a metallic material (e.g., aluminum, copper, tungsten, molybdenum, and cobalt). The barrier pattern BM may cover the side and bottom surfaces of the conductive pattern FM. The barrier pattern BM may include a metal layer and a metal nitride layer. The metal layer may be formed of or include at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may be formed of or include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0068] Reference Figure 1 , Figure 2A and Figure 4A The front interconnect layers (FWLs) can be sequentially stacked on the second interlayer insulation layer 120. Each front interconnect layer (FWL) may include a first front interconnect layer (FWL) (1) to a Jth front interconnect layer (FWL) (J). Each of the front interconnect layers (FWLs) may include a front insulation layer (FI) and a front through-hole (FV) and a front line (FT) disposed in the front insulation layer (FI). The number J may be a natural number greater than or equal to 3.

[0069] The front insulating layer FI may be formed of or include at least one of SiO2, SiN, SiON, SiCN, and SiOCH, and may have a single-layer or multi-layer structure. Each of the front through-hole element FV and the front wire FT may be formed of or include at least one of a metallic material (e.g., tungsten, copper, aluminum, titanium, and tantalum).

[0070] The front lines FT included in the odd-numbered front interconnect layers (e.g., FWL(1), FWL(3), ...) of the front interconnect layers FWL can extend in the second direction D2. The front lines FT included in the even-numbered front interconnect layers (e.g., FWL(2), FWL(4), ...) of the front interconnect layers FWL can extend in the first direction D1, which intersects the second direction D2. Some of the front lines FT and the front through-holes FV can be used to apply or transmit electrical signals to the gate contact GC and the active contact AC.

[0071] The smaller the distance from the front surface 100F of the substrate 100, the smaller the width, height, spacing, and / or density of the front line FT per unit area. The smaller the distance from the front surface 100F of the substrate 100, the smaller the width, height, spacing, and / or density of the front through-hole FV per unit area.

[0072] The first transistor TR(1), the second transistor TR(2), and some of the front-side lines FT and front-side through-holes FV can form part of a logic circuit, such as a flip-flop, inverter, AND circuit, OR circuit, XOR circuit, XNOR circuit, NAND circuit, and NOR circuit. The first transistor TR(1) and the second transistor TR(2) (specifically, the first gate electrode GE(1) of the first transistor TR(1) and the second gate electrode GE(2) of the second transistor TR(2)) can correspond to test points selected for detecting faults during the testing of a semiconductor device.

[0073] A bonding insulating layer 210 may be disposed on the front interconnect layer FWL(J) of the J-th layer. The bonding insulating layer 210 may be formed of or include at least one of SiO2, SiN, and SiCN, and may have a single-layer or multi-layer structure. A support substrate 200 may be disposed on the bonding insulating layer 210. The support substrate 200 may be a silicon substrate or an insulating substrate. The support substrate 200 may be omitted. The bonding insulating layer 210 may be referred to as a 'passivation layer'. The support substrate 200 and the bonding insulating layer 210 are sufficiently transparent to allow light to pass through them.

[0074] Reference Figure 1 , Figure 2A and Figure 4A The back surface 100B of the substrate 100 may be covered by a lower insulating layer 160. The lower insulating layer 160 may be formed of or include at least one of SiO2, SiN, and SiON, and may have a single-layer or multi-layer structure. A rear interconnect layer BWL may be stacked below the lower insulating layer 160. The rear interconnect layer BWL may include a first rear interconnect layer BWL(1) to a Kth rear interconnect layer BWL(K). The number K may be a natural number greater than or equal to 2. The number K may be less than the number J.

[0075] Each of the rear interconnect layers BWL may include a rear insulating layer BI and a rear through-hole element BV and a rear line BT disposed in the rear insulating layer BI. The rear insulating layer BI may be formed of or include at least one of SiO2, SiN, SiON, SiCN, and SiOCH, and may have a single-layer or multi-layer structure. The bottommost rear insulating layer BI (B) may be referred to as a passivation layer. Each of the rear through-hole element BV and the rear line BT may be formed of or include at least one of a metallic material (e.g., tungsten, copper, aluminum, titanium, and tantalum).

[0076] The rear-side lines BT included in the odd-numbered rear-side interconnect layers (e.g., BWL(1), BWL(3) etc.) of the rear-side interconnect layers BWL can extend in the second direction D2. The rear-side lines BT included in the even-numbered rear-side interconnect layers (e.g., BWL(2), BWL(4) etc.) of the rear-side interconnect layers BWL can extend in the first direction D1, which intersects the second direction D2. Some of the rear-side through-holes BV and the rear-side lines BT can form a rear-side power network. Some of the rear-side lines BT and the rear-side through-holes BV can apply a source voltage or a drain voltage to at least one of the source / drain patterns SD.

[0077] The width, height, and / or spacing of the topmost rear lines BT(P1), BT(P2), and BT(U) in the rear lines BT may be smaller than the width, height, and / or spacing of the bottommost rear lines BT(B1) and BT(B2). Each of the bottommost rear lines BT(B1) and BT(B2) in the rear lines BT may be referred to as a "bonding pad".

[0078] Reference Figure 1 , Figure 2A and Figure 4ASome of the topmost rear lines BT(P1), BT(P2), and BT(U) in the rear line BT can be power lines BT(P1) and BT(P2). A second rear contact BCA2 can be configured to penetrate the substrate 100 and connect power lines BT(P1) and BT(P2) to at least one of the source / drain patterns SD. For example, one of the second rear contacts BCA2 can be configured to penetrate the substrate 100 and connect one of the power lines BT(P1) to one of the first source / drain patterns SD(1) of the first transistor TR(1). Therefore, a drain voltage VDD or a source voltage VSS can be applied to one of the first source / drain patterns SD(1). In some embodiments, one of the second rear contacts BCA2 can be configured to penetrate the substrate 100 and connect one of the power lines BT(P2) to one of the second source / drain patterns SD(2) of the second transistor TR(2). Therefore, a drain voltage VDD or a source voltage VSS can be applied to one of the second source / drain patterns SD(2).

[0079] The second rear contact BCA2 may have a conductive cylindrical shape. Each of the rear contacts BCA1 and BCA2 may include a contact PCP and a pad LIN configured to at least surround the side surface of the contact PCP. The contact PCP may be formed of or include at least one of a metallic material (e.g., tungsten, molybdenum, ruthenium, cobalt, aluminum, and copper). The pad LIN may be formed of or include at least one of a silicon-based insulating material (e.g., SiO, SiN, SiOC, and SiOCN).

[0080] The first gate electrode GE(1) of the first transistor TR(1) can be connected to the first front detection structure FDS1, the first through detection structure TDS1, and the first rear detection structure BDS1. The second gate electrode GE(2) of the second transistor TR(2) can be connected to the second front detection structure FDS2, the through-hole TV, and the second rear detection structure BDS2.

[0081] Some of the front side lines FT and some of the front side through-pieces FV can form a first front side detection structure FDS1 and a second front side detection structure FDS2 that are spaced apart from each other.

[0082] Reference Figure 1 and Figure 2A The first front detection structure FDS1 can be placed in the first front interconnect layer FWL(1). When viewed in cross-section, the first front detection structure FDS1 may include a front line FT and two front through-pieces FV. The upper end of the first front detection structure FDS1 can be placed at the first horizontal layer LV1.

[0083] One end of the first front-side detection structure FDS1 can contact the gate contact GC on the first gate electrode GE(1). The other end of the first front-side detection structure FDS1 can be connected to a first through-detection structure TDS1 that penetrates the second interlayer insulating layer 120, the first interlayer insulating layer 110, and the substrate 100. The first through-detection structure TDS1 can be disposed between adjacent partition structures DB.

[0084] Reference Figure 1 and Figure 2A The first through-detection structure TDS1 may include a front contact FCA that penetrates the second interlayer insulating layer 120 and the first interlayer insulating layer 110, and a first rear contact BCA1 that penetrates the substrate 100.

[0085] like Figure 2A and Figure 2B As shown, the first through-detection structure TDS1 may further include a connecting conductive pattern CSD between the front contact FCA and the first rear contact BCA1. The first through-detection structure TDS1 may further include a metal-semiconductor compound layer SC between the connecting conductive pattern CSD and the front contact FCA.

[0086] In some embodiments, refer to Figure 2C The first rear contact BCA1 can pass through and connect the conductive pattern CSD and the metal semiconductor compound layer SC, and can contact the front contact FCA.

[0087] The front contact FCA may have a structure similar to that of the active contact AC. The front contact FCA may include a conductive pattern FM and a blocking pattern BM surrounding the conductive pattern FM.

[0088] The first rear contact BCA1 may have a structure similar to that of the second rear contact BCA2. The first rear contact BCA1 may include a contact PCP and a pad LIN configured to at least surround the side surface of the contact PCP. The upper end of the first rear contact BCA1 may be at the same level as the upper end of the second rear contact BCA2.

[0089] The interconnect conductive pattern (CSD) may have the same or similar structure as the source / drain pattern (SD). The interconnect conductive pattern (CSD) may be doped with the same dopants as the source / drain pattern (SD). The interconnect conductive pattern (CSD) may include a buffer layer (BFL) and a main layer (MAL) on the buffer layer (BFL), such as... Figure 2AAs shown. The conductive pattern CSD may be doped with p-type impurities or dopants. Alternatively, the conductive pattern CSD may be formed from or include at least one of Si, SiP, SiC, SiPC, InP, GaAs, AlAs, InAs, InAlAs, and InGaAs, such as... Figure 2B As shown. The conductive pattern CSD can be doped with n-type impurities (e.g., phosphorus, arsenic, or antimony).

[0090] Reference Figure 1 and Figure 4A The second front detection structure FDS2 may be disposed in the first front interconnect layer FWL(1) to the third front interconnect layer FWL(3). The second front detection structure FDS2 may include a front line FT and a front through member FV. The upper end of the second front detection structure FDS2 may be located at the second level LV2. The second level LV2 may be different from (e.g., higher than) the first level LV1.

[0091] When viewed in cross-section, the second front detection structure FDS2 may have an inverted "U" shape. One end of the second front detection structure FDS2 may contact the gate contact GC on the second gate electrode GE(2). The other end of the second front detection structure FDS2 may contact the through-hole TV.

[0092] Reference Figure 4A The through-hole element TV can be disposed between adjacent partition structures DB. The through-hole element TV can be configured to penetrate the second interlayer insulating layer 120, the first interlayer insulating layer 110, the substrate 100, and the lower insulating layer 160. The through-hole element TV can also penetrate the front insulating layer FI of the first front interconnect layer FWL(1), such as... Figure 4B As shown. The through-hole element TV may be formed of or include at least one of a metallic material (e.g., tungsten, molybdenum, ruthenium, cobalt, aluminum, and copper). The side surfaces of the through-hole element TV may be covered by a through-hole insulating layer TI. The through-hole insulating layer TI may be formed of or include at least one of SiO2 and SiN.

[0093] Reference Figure 1The rear line BT and the rear through-hole component BV can constitute a first rear detection structure BDS1, a second rear detection structure BDS2, and a rear interconnection structure BTS. The first rear detection structure BDS1 can be adjacent to the back surface 100B. Thus, the first rear detection structure BDS1 can be closer to the back surface 100B than the front surface 100F. The first rear detection structure BDS1 can be connected to the first through-hole detection structure TDS1. The second rear detection structure BDS2 can be connected to the through-hole component TV. The rear interconnection structure BTS can be connected to power lines BT(P1) and BT(P2).

[0094] The lower end of the first rear-side detection structure BDS1 can be positioned at the third level LV3. The lower end of the second rear-side detection structure BDS2 can be positioned at the fourth level LV4. The lower end of at least one of the rear-side interconnect structures BTS can be positioned at the fifth level LV5. The third level LV3 to the fifth level LV5 can be lower than the first level LV1 and the second level LV2. The third level LV3 to the fifth level LV5 can be substantially the same as each other. The vertical length of the first rear-side detection structure BDS1 can be the same as the vertical length of the second rear-side detection structure BDS2.

[0095] The first external connection terminal OB1 may be configured to penetrate the bottommost rear insulating layer BI(B) and be bonded to the first bonding pad BT(B1) of the rear interconnect structure BTS. The second external connection terminal OB2 may be configured to penetrate the bottommost rear insulating layer BI(B) and be bonded to the second bonding pad BT(B2) of the first rear detection structure BDS1 and the second rear detection structure BDS2. Each of the first external connection terminal OB1 and the second external connection terminal OB2 may include a conductive bump, a conductive pillar, and / or a solder ball. The second external connection terminal OB2 may be used as a test signal port of the semiconductor device 1000.

[0096] Figure 5 It shows the detection Figure 1 A schematic diagram of a method for troubleshooting in a semiconductor device.

[0097] Reference Figure 5 Reference can be manufactured Figures 1 to 4B The semiconductor device 1000 is described. The semiconductor device 1000 can be manufactured using conventional manufacturing processes. However, the connecting conductive pattern CSD and the source / drain pattern SD can be formed simultaneously. The front contact FCA and the active contact AC can be formed simultaneously. The first rear contact BCA1 and the second rear contact BCA2 can be formed simultaneously. The first rear detection structure BDS1, the second rear detection structure BDS2, and the rear interconnect structure BTS can be formed simultaneously.

[0098] In a method for detecting faults in a semiconductor device according to some embodiments of the present invention, an electron beam generating and sensing device 500 may be placed adjacent to the back side 1000B of the semiconductor device 1000. At least one of the second external connection terminals OB2 may then be irradiated by a first electron beam E1, and a reflected or emitted second electron beam E2 may be sensed. In the event of a fault in at least one of the logic circuits composed of the first transistor TR(1) and the second transistor TR(2), the characteristics of the second electron beam E2 (e.g., phase shift, amplitude variation of secondary electrons, energy spectrum variation, etc.) may differ from the characteristics of the first electron beam E1. By utilizing this method, the location of the fault in the semiconductor device can be accurately located.

[0099] As an example, electrons in the first electron beam E1 radiated to the second external connection terminal OB2 connected to the first rear-side detection structure BDS1 can be transferred to the first gate electrode GE(1) through the first rear-side detection structure BDS1, the first through-detection structure TDS1, and the first front-side detection structure FDS1. Depending on whether the first transistor TR(1) is faulty, at least a portion of the electrons can be emitted to the outside of the second external connection terminal OB2 through the first front-side detection structure FDS1, the first through-detection structure TDS1, and the first rear-side detection structure BDS1 to form a second electron beam E2. Characteristics of the second electron beam E2 (e.g., reflectivity or wavelength) can be analyzed to determine whether the first transistor TR(1) is faulty.

[0100] Semiconductor devices according to some embodiments of the present invention may include detection structures FDS1, FDS2, TDS1, BDS1, and BDS2 connected to test points for detecting faults during testing. Specifically, the first gate electrode GE(1) of the first transistor TR(1) may be connected to the first front-side detection structure FDS1, the first through-hole detection structure TDS1, the first rear-side detection structure BDS1, and a second external connection terminal OB2, thus allowing a test signal to be applied from outside the back surface 1000B of the semiconductor device 1000 to the first gate electrode GE(1). Similarly, the second gate electrode GE(2) of the second transistor TR(2) may be connected to the second front-side detection structure FDS2, the through-hole TV, the second rear-side detection structure BDS2, and another second external connection terminal OB2, thus allowing a test signal to be applied from outside the back surface 1000B of the semiconductor device 1000 to the second gate electrode GE(2). Therefore, the semiconductor device may have a structure that is easily tested.

[0101] Even if the first front-side detection structure FDS1 connected to the first gate electrode GE (1) is positioned at a different level than the second front-side detection structure FDS2 connected to the second gate electrode GE (2), the test signal can still be applied from the outside of the back side 1000B of the semiconductor device 1000 to the first gate electrode GE (1) and the second gate electrode GE (2) due to the rear-side detection structures BDS1 and BDS2. Therefore, to test the semiconductor device 1000, it is not necessary to form holes with different depths through the front side 1000F of the semiconductor device 1000, and thus, the test process can be performed in a simple and easy manner.

[0102] Furthermore, since the back-side detection structures BDS1 and BDS2 are located in the back-side interconnect layer BWL, which has a lower interconnect density than the front-side interconnect layer FWL, the interconnect wiring steps for arranging the back-side detection structures can be easily performed during the design of the semiconductor device.

[0103] Figure 6A This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention. Figure 6B It shows the detection Figure 6A A schematic diagram of a method for troubleshooting in a semiconductor device.

[0104] Reference Figure 6A The semiconductor device 1001 in the current embodiment may not include Figure 1 The second external connection terminal OB2. At least a portion of the bottom surface of the second bonding pad BT(B2) may not be covered by the bottommost rear insulating layer BI(B) and may be exposed to the outside. The second bonding pad BT(B2) may be used as a test signal port of the semiconductor device 1001.

[0105] Reference Figure 6B In a method for detecting faults in a semiconductor device according to some embodiments of the present invention, an electron beam generating and sensing device 500 may be placed adjacent to the back surface 1000B of the semiconductor device 1001. At least one of the second bonding pads BT(B2) can then be irradiated by a first electron beam E1, and the reflected or emitted second electron beam E2 can be sensed. By utilizing this method, the location of the fault in the semiconductor device can be accurately located. Bonding can be performed after the testing process. Figure 6A The process of the first external connection terminal OB1.

[0106] A semiconductor device according to another embodiment of the present invention may have the same characteristics as... Figure 6AThe structure is basically the same as that in the previous one, but the bottom surface of the second bonding pad BT(B2) is completely covered by the bottommost rear insulating layer BI(B). In this case, before the test process to detect faults in the semiconductor device, a portion of the bottommost rear insulating layer BI(B) can be removed to expose the bottom surface of the second bonding pad BT(B2).

[0107] Figure 7A This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention.

[0108] Reference Figure 7A The semiconductor device 1002 in the current embodiment may not include Figure 1 The second external connection terminal OB2 and the second bonding pad BT(B2). The rear line BT may also include a (K-1) rear line BT(K-1) connected to the first bonding pad BT(B1). The (K-1) rear line BT(K-1) may be included in the (K-1) rear interconnect layer BWL(K-1). In the semiconductor device 1002 according to the present embodiment, the third level LV3 at the lower end of the first rear detection structure BDS1 may be the same as the fourth level LV4 at the lower end of the second rear detection structure BDS2, and may be higher than the fifth level LV5 at the lower end of the rear interconnect structure BTS. In other words, the lowest rear line BT(E) used for detection (i.e., the lowest one of the rear lines BT constituting the first rear detection structure BDS1 and the second rear detection structure BDS2) may be placed between the first rear interconnect layer BWL(1) and the Kth rear interconnect layer BWL(K). The bottom rear line BT(E) used for detection can be used as a test signal port for semiconductor device 1001.

[0109] Figure 7B and Figure 7C It is shown Figure 7A A plan view of a portion of a semiconductor device.

[0110] Reference Figure 7A and Figure 7B The bottommost rear line BT(E) used for detection may not vertically overlap with the first bonding pad BT(B1) and the (K-1)th rear line BT(K-1). When viewed in a plan view, the bottommost rear line BT(E) used for detection may be located between the first bonding pads BT(B1).

[0111] Alternatively, refer to Figure 7A and Figure 7CThe first bonding pad BT(B1) may extend in the second direction D2 and may be connected to each other to form an interconnect for which a power supply voltage is applied. The first bonding pad BT(B1) may have a via OH. When viewed in a plan view, the bottommost rear line BT(E) for inspection may vertically overlap with the via OH.

[0112] Figure 8 It shows the detection Figure 7A A schematic diagram of a method for troubleshooting in a semiconductor device.

[0113] Reference Figure 8 In a method for detecting faults in a semiconductor device according to some embodiments of the present invention, trench H2 may be formed in Figure 7A In the back surface 1000B of the semiconductor device 1002, the lowest rear-side line BT(E) for detection is exposed. Here, since the third level LV3 at the lower end of the first rear-side detection structure BDS1 is equal to the fourth level LV4 at the lower end of the second rear-side detection structure BDS2, the trench H2 can be formed to have the same depth. In this case, the trench H2 can be formed more easily than forming trenches with different depths. That is, the depackaging process can be easily performed before testing the semiconductor device.

[0114] An electron beam generating and sensing device 500 may be placed adjacent to the back surface 1000B of the semiconductor device 1001. The electron beam generating and sensing device 500 may then be configured to radiate at least one of the lowermost rear-side lines BT(E) used for detection through a trench H2 with a first electron beam E1, and to sense a second electron beam E2 reflected or emitted from the lowermost rear-side line BT(E) used for detection. By using this method, the fault location of the semiconductor device can be accurately located.

[0115] Figure 9 This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention.

[0116] Reference Figure 9In the semiconductor device 1003 according to the present embodiment, a first front-side detection structure FDS1 can connect the first gate electrode GE (1) of two adjacent first transistors TR (1) to a first through-hole detection structure TDS1. A second front-side detection structure FDS2 can connect the second gate electrode GE (2) of two adjacent second transistors TR (2) to a through-hole TV. The first level LV1 at the upper end of the first front-side detection structure FDS1 can be higher than the second level LV2 at the upper end of the second front-side detection structure FDS2. In the present embodiment, the number of transistors TR connected to each of the first front-side detection structure FDS1 and the second front-side detection structure FDS2 is not limited to 2 and is equal to or greater than 3. In addition, each of the first front-side detection structure FDS1 and the second front-side detection structure FDS2 can be connected to at least one of the source / drain patterns SD of the transistors TR. In addition to the features described above, the semiconductor device may have the same characteristics as the referenced Figures 1 to 7C They describe essentially the same characteristics.

[0117] Figure 10 This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention.

[0118] Reference Figure 10 In the semiconductor device 1004 according to the present embodiment, a first front-side detection structure FDS1 can be connected to a first rear-side detection structure BDS1 via a first through-hole TV (1). A second front-side detection structure FDS2 can be connected to a second rear-side detection structure BDS2 via a second through-hole TV (2). In addition to the features described above, the semiconductor device may have the same characteristics as the referenced... Figures 1 to 7C They describe essentially the same characteristics.

[0119] Figure 11 This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention.

[0120] Reference Figure 11 In the semiconductor device 1005 according to the current embodiment, a first front-side detection structure FDS1 can be connected to a first rear-side detection structure BDS1 via a first through-detection structure TDS1. A second front-side detection structure FDS2 can be connected to a second rear-side detection structure BDS2 via a second through-detection structure TDS2. In addition to the features described above, the semiconductor device may have the same characteristics as the referenced... Figures 1 to 7C The second through-detection structure TDS2 may have the same or similar structure as the first through-detection structure TDS1. In addition to the features described above, the semiconductor device may have the same features as the reference structure. Figures 1 to 7C They describe essentially the same characteristics.

[0121] Figure 12This is a conceptual diagram illustrating some embodiments of a semiconductor device according to the present invention.

[0122] Reference Figure 12 In the current embodiment, the semiconductor device 1006 may include a substrate 100, an upper structure FMS on the substrate 100, and a lower structure BMS below the substrate 100. The upper structure FMS may include trigger circuits 310a, 310b, and 310c, buffers 314a and 314b, and cells 312a and 312b connected to each other. The trigger circuits 310a, 310b, and 310c, buffers 314a and 314b, and cells 312a and 312b may form a scan chain. Each of cells 312a and 312b may be a logic cell and / or a memory cell. Each of buffers 314a and 314b may include an inverter.

[0123] Each of the trigger circuits 310a, 310b, and 310c may include a test input terminal SI for inputting a test signal, an enable signal input terminal (SE) for the MUX, a function input terminal D, a clock cycle signal input terminal CK, and an output terminal Q. Each of the trigger circuits 310a, 310b, and 310c may include a reference... Figures 1 to 11 The description includes at least one of the first transistor TR (1) and the second transistor TR (2), the front-side line FT, and the front-side through-hole FV. The test input terminal SI may correspond to at least one of the gate electrodes GE (1) and GE (2) of the first transistor TR (1) and the second transistor TR (2). That is, the test signal may be input to... Figures 1 to 11 At least one of the gate electrodes GE(1) and GE(2).

[0124] For example, the test input terminal SI of the first trigger circuit 310a can be connected to one of the second external connection terminals OB2 via the first front detection structure FDS1, the first through-detection structure TDS1, and the first rear detection structure BDS1. The test input terminal SI of the second trigger circuit 310b can be connected to the other of the second external connection terminals OB2 via the second front detection structure FDS2, the second through-detection structure TDS2, and the second rear detection structure BDS2. The test input terminal SI of the third trigger circuit 310c can be connected to the other of the second external connection terminals OB2 via the third front detection structure FDS3, the through-pass element TV, and the third rear detection structure BDS3.

[0125] In a method for detecting faults in a semiconductor device according to some embodiments of the present invention, an electron beam generating and sensing device 500 may be positioned below a second external connection terminal OB2. In some embodiments, the electron beam generating and sensing device 500 may be configured to irradiate at least one of the second external connection terminals OB2 with a first electron beam E1 and sense a second electron beam E2 reflected or emitted from the second external connection terminal OB2. If a fault occurs in at least one of the trigger circuits 310a, 310b and 310c, buffers 314a and 314b, and units 312a and 312b, the characteristics of the second electron beam E2 (e.g., phase shift, amplitude change of secondary electrons, energy spectrum change, etc.) may differ from those of the first electron beam E1. By using this method, the location of the fault in the semiconductor device can be accurately located.

[0126] According to some embodiments of the present invention, a semiconductor device may include a back-side detection structure connected to a point for detecting faults during testing, and a test signal may be applied to an end of the back-side detection structure adjacent to the back side of the semiconductor device. Therefore, the semiconductor device may have a structure to which testing processes can be easily performed. Furthermore, interconnect wiring steps for arranging the back-side detection structure can be easily performed during the design of the semiconductor device. In this case, a semiconductor device with improved power, performance, and area characteristics can be realized because the voltage drop effect is achieved more effectively.

[0127] In some embodiments of the present invention, the method for detecting faults in a semiconductor device can omit or minimize the process of unpacking the front of the semiconductor device and easily and accurately locate the fault.

[0128] While exemplary embodiments of the inventive concept have been specifically shown and described, one of those skilled in the art should understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims. Figures 1 to 12 The embodiments can be combined to realize the inventive concept.

Claims

1. A semiconductor device, comprising: A substrate, comprising a front side and a back side opposite to each other; A first transistor, adjacent to the front side of the substrate, the first transistor including a first gate electrode and first source / drain patterns on both sides adjacent to the first gate electrode; A first interlayer insulating layer is disposed on the first transistor; A first front-side detection structure is disposed on the first interlayer insulating layer and connected to the first gate electrode; A first rear-side detection structure is located adjacent to the back side of the substrate; and A first through-detection structure connects the first front detection structure to the first rear detection structure. The first through-detection structure includes a front contact that penetrates the first interlayer insulating layer and a first rear contact that penetrates a portion of the substrate.

2. The semiconductor device according to claim 1, wherein, The front contact member overlaps vertically with the first rear contact member.

3. The semiconductor device according to claim 1, wherein, The first penetration detection structure further includes a conductive pattern connecting the front contact and the first rear contact, and The conductive pattern being connected comprises silicon.

4. The semiconductor device according to claim 3, wherein, The conductive pattern and the first source / drain pattern are doped with the same dopant.

5. The semiconductor device according to claim 1, wherein, The front contact element contacts the first rear contact element.

6. The semiconductor device according to claim 1, wherein, The first transistor is included in the first flip-flop circuit.

7. The semiconductor device according to claim 6, wherein, The test signal is input to the first gate electrode of the first transistor through at least the front detection structure, the rear detection structure, and the first through-detection structure.

8. The semiconductor device according to claim 1, further comprising: A second transistor is located adjacent to the front side of the substrate, and the second transistor includes a second gate electrode and second source / drain patterns adjacent to both sides of the second gate electrode. The second front-side detection structure is disposed on the first interlayer insulating layer and connected to the second gate electrode; The second rear-side detection structure is located adjacent to the back side of the substrate; as well as A through-hole member that penetrates the first interlayer insulating layer and the substrate, and connects the second front detection structure to the second rear detection structure.

9. The semiconductor device according to claim 8, wherein, The vertical length of the first rear detection structure is equal to the vertical length of the second rear detection structure.

10. The semiconductor device according to claim 8, wherein, The upper end of the first front detection structure is positioned at the first horizontal level. The upper end of the second front detection structure is positioned at a second level, different from the first level. The lower end of the first rear detection structure is positioned at a third level, lower than the first and second levels, and The lower end of the second rear detection structure is positioned at the third level.

11. The semiconductor device of claim 10, further comprising: Electric power lines, which are adjacent to the back side of the substrate; as well as The rear interconnect structure is adjacent to and connected to the power line. The lower end of the rear interconnect structure is positioned at a fourth level that is equal to or lower than the third level.

12. The semiconductor device of claim 11, further comprising: A third transistor is located adjacent to the front side of the substrate, the third transistor including a third gate electrode and third source / drain patterns on both sides adjacent to the third gate electrode; as well as A second rear contact extends through a portion of the substrate and connects the electric field line to one of the third source / drain patterns. The upper end of the second rear contact is positioned at the same level as the upper end of the first rear contact.

13. A semiconductor device, comprising: A substrate, comprising a front side and a back side opposite to each other; A first transistor, adjacent to the front side of the substrate, the first transistor including a first gate electrode and first source / drain patterns on both sides adjacent to the first gate electrode; A second transistor is located adjacent to the front side of the substrate, and the second transistor includes a second gate electrode and second source / drain patterns adjacent to both sides of the second gate electrode. A first interlayer insulating layer is disposed on the first transistor; A first front-side detection structure is disposed on the first interlayer insulating layer and connected to the first gate electrode; The second front-side detection structure is disposed on the first interlayer insulating layer and connected to the second gate electrode; The first rear-side detection structure is located adjacent to the back side of the substrate; The first through-hole member penetrates the first interlayer insulating layer and the substrate, and connects the first front detection structure to the first rear detection structure. The second rear-side detection structure is located adjacent to the back side of the substrate; as well as The second through-hole member penetrates the first interlayer insulating layer and the substrate, and connects the second front detection structure to the second rear detection structure. Wherein, the first level of the lower end of the first rear detection structure is equal to the second level of the lower end of the second rear detection structure.

14. The semiconductor device according to claim 13, wherein, The first transistor is included in the first flip-flop circuit, and The test signal is input to the first gate electrode of the first transistor through at least the first front detection structure, the first rear detection structure, and the first through-hole.

15. The semiconductor device of claim 13, further comprising: Electric power lines, which are adjacent to the back side of the substrate; as well as A rear interconnect structure is disposed below and connected to the power line. The lower end of the rear interconnect structure is positioned at a third level that is equal to or lower than the first level of the lower end of the first rear detection structure.

16. The semiconductor device according to claim 13, wherein, The upper end of the first front detection structure is positioned at a third level, higher than the first level, and The upper end of the second front detection structure is positioned at a fourth level, which is higher than the first level and different from the third level.

17. A semiconductor device, comprising: A substrate, comprising a front side and a back side opposite to each other; A trigger circuit, which is adjacent to the front side of the substrate; A first transistor, adjacent to the front side of the substrate, the first transistor including a first gate electrode and first source / drain patterns on both sides adjacent to the first gate electrode, the first transistor being included in the trigger circuit; A first interlayer insulating layer is disposed on the first transistor; A first front-side detection structure is disposed on the first interlayer insulating layer and connected to the first gate electrode; The first rear-side detection structure is located adjacent to the back side of the substrate; A first through-detection structure connects the first front detection structure to the first rear detection structure. Electric power lines, which are adjacent to the back side of the substrate; as well as A rear interconnect structure is disposed below and connected to the power line. The first through-detection structure includes a front contact penetrating the first interlayer insulating layer, a first rear contact penetrating a portion of the substrate, and a conductive connection pattern between the front contact and the first rear contact. The conductive pattern and the first source / drain pattern are doped with the same dopant.

18. The semiconductor device according to claim 17, wherein, The conductive pattern being connected comprises silicon.

19. The semiconductor device according to claim 17, wherein, The lower end of the first rear detection structure is positioned at the first horizontal level, and The lower end of the rear interconnect structure is positioned at a second level that is equal to or lower than the first level.

20. The semiconductor device according to claim 17, wherein, The test signal is input to the first gate electrode of the first transistor through at least the first front detection structure, the first rear detection structure, and the first through detection structure.

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