Semiconductor element and forming method thereof
By combining adjacent source/drain contact patterns with directional self-assembly and optical proximity correction techniques, and integrating annealing and etching processes, the problems of pattern resolution and etching control in traditional semiconductor manufacturing are solved, achieving efficient source/drain contact formation and reducing equipment costs and process complexity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NAN YA TECH
- Filing Date
- 2026-01-19
- Publication Date
- 2026-05-15
AI Technical Summary
In traditional semiconductor manufacturing processes, the pattern resolution of adjacent source or drain contacts is limited, etching control is difficult, and high-resolution exposure equipment increases cost and process complexity. Existing optical proximity correction techniques lead to pattern deformation and etching inhomogeneity.
The source/drain contact patterns are merged using directional self-assembly materials and optical proximity correction technology. The source/drain contacts are formed by combining annealing and etching processes. Non-polar organic materials are used as sacrificial layers, and dielectric layers are formed by spin coating and stripping processes to optimize the structure.
It improves pattern resolution, enhances etching controllability, reduces the risk of pattern merging or deformation, simplifies the process, and reduces equipment costs.
Smart Images
Figure CN122054984A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to semiconductor devices and methods for forming the same. Background Technology
[0002] In traditional semiconductor manufacturing processes, the formation of adjacent source or drain contacts still faces many challenges, such as limited pattern resolution and difficulty in etching control. As the minimum feature size continues to shrink, the spacing between contacts is also becoming narrower. Traditional photolithography processes must employ high-resolution exposure equipment, such as immersion lithography systems or extreme ultraviolet (EUV) lithography systems, to achieve the required pattern resolution, thereby increasing equipment costs and process complexity. Summary of the Invention
[0003] One aspect of the present invention provides a method for forming a semiconductor device, comprising: forming a gate structure on a substrate; forming gate spacer layers on opposite sidewalls of the gate structure; forming source / drain regions on opposite sides of the gate structure in the substrate; forming a first sacrificial layer to cover the gate structure and the gate spacer layers; forming an opening in the first sacrificial layer to expose a portion of the gate spacer layer and the substrate; forming a second sacrificial layer in the opening; performing a first annealing process on the second sacrificial layer to separate a first material and a second material of the second sacrificial layer, wherein the first material is arranged along the sidewalls of the gate spacer layer and the source / drain regions; removing the first sacrificial layer and the second material of the second sacrificial layer; forming a dielectric layer on the substrate and covering the gate structure and the first material of the second sacrificial layer; and replacing the first material of the second sacrificial layer with a first source / drain contact.
[0004] In some embodiments, the second sacrificial layer comprises a directed self-assembly material.
[0005] In some embodiments, the first material of the second sacrificial layer extends to a position directly above the gate structure.
[0006] In some embodiments, the method further includes: after replacing the first material of the second sacrificial layer with the first source / drain contact, forming a second source / drain contact in the dielectric layer, wherein the second source / drain contact is separated from the gate spacer layer.
[0007] In some embodiments, the opening is wider than the distance between the gate structures.
[0008] In some embodiments, the method further includes: forming a hard mask over the gate structure, wherein a first material of the second sacrificial layer extends to the top surface of the hard mask.
[0009] In some embodiments, the first material of the second sacrificial layer has two portions that are in contact with the gate spacer layer and separated from each other.
[0010] In some embodiments, removing the first sacrificial layer and the second material further includes: performing a first stripping process to remove the second material; and performing a second stripping process to remove the first sacrificial layer.
[0011] In some embodiments, forming a dielectric layer on a substrate further includes: performing a spin coating process on a material to form a dielectric layer on a substrate; and performing a second annealing process on the material of the dielectric layer to form a dielectric layer.
[0012] In some embodiments, the first sacrificial layer is formed of a nonpolar organic material.
[0013] One aspect of the present invention provides a semiconductor device comprising: a gate structure located on a substrate; source / drain regions located on opposite sides of the gate structure in the substrate; a dielectric layer located on the substrate and covering the gate structure; gate spacers located on opposite sidewalls of the gate structure; and first source / drain contacts electrically coupled to the source / drain regions and extending along the sidewalls of the gate spacers, and extending to a position directly above the gate structure.
[0014] In some embodiments, the semiconductor element further includes: a hard mask, respectively located on the gate structure, wherein first source / drain contacts extend to the top surface of the hard mask, respectively.
[0015] In some embodiments, the top surface of the first source / drain contact is higher than the top surface of the hard shield.
[0016] In some embodiments, the semiconductor element further includes: a second source / drain contact electrically coupled to the source / drain region, wherein the second source / drain contact is separated from the gate spacer layer.
[0017] In some embodiments, the first source / drain contact, the second source / drain contact, and the top surface of the dielectric layer are substantially at the same level.
[0018] In some embodiments, the gate spacer layer comprises a polar dielectric material.
[0019] In some embodiments, the first source / drain contacts have a distance ranging from about 20 nm to about 40 nm.
[0020] In some embodiments, one of the first source / drain contacts has a thickness ranging from about 15 nm to about 30 nm.
[0021] In some embodiments, the semiconductor element further includes: an isolation structure located in the substrate and between first source / drain contacts.
[0022] In some embodiments, one of the first source / drain contacts has a curved inner sidewall and a curved outer sidewall. Attached Figure Description
[0023] The best understanding of the invention will come from the following detailed description, when read with reference to the accompanying drawings. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.
[0024] Figures 1 to 10 Cross-sectional views of various stages in forming a semiconductor device are shown according to some embodiments of the present invention. Detailed Implementation
[0025] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided objective. Specific examples of components and configurations are described below to simplify the content of this invention. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in various instances, references to numbers and / or letters may be repeated. This repetition is for simplicity and clarity and does not, in itself, define the relationship between the various embodiments and / or configurations discussed.
[0026] Additionally, for ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper,” and similar terms, may be used herein to describe the relationship between one element or feature as illustrated in the figures and another. Besides the orientations depicted in the figures, these spatial relative terms are intended to also cover different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.
[0027] In traditional semiconductor manufacturing processes, the formation of adjacent source or drain contacts still faces many challenges, such as limited pattern resolution and difficulty in etching control. As the minimum feature size continues to shrink, the spacing between source / drain contacts is becoming increasingly narrow. Traditional photolithography processes must employ high-resolution exposure equipment, such as immersion lithography systems or extreme ultraviolet (EUV) lithography systems, to achieve the required pattern resolution, thereby increasing equipment costs and process complexity.
[0028] Furthermore, existing optical proximity correction (OPC) techniques often result in pattern distortion, edge inhomogeneity, or partial fusion of adjacent source / drain contact patterns, leading to incomplete or misaligned openings in subsequent etching steps. In the etching process of source / drain contacts, the narrow area between them can cause sidewall weakening, structural distortion, or pattern fusion, reducing etching uniformity. Additionally, the high-energy etching conditions used to ensure sufficient etching depth can induce plasma charging effects, potentially causing device damage or reduced device reliability.
[0029] To address the aforementioned problems, embodiments of the present invention provide a semiconductor device. In some embodiments, the design of the photomask utilizes optical proximity correction (OPC) technology to merge the patterns of two adjacent source / drain contacts into a larger pattern. This merged pattern improves pattern resolution, enhances etching controllability, and reduces the risk of pattern merging or deformation in subsequent processes.
[0030] In some embodiments, the semiconductor device can be formed with directed self-assembly (DSA) materials and related processes (e.g., DSA annealing) to form the source / drain electrodes. In some embodiments, the final dimensions of the source / drain electrodes can be further controlled by adjusting the size of the merged pattern on the photomask and the molecular chain length of the DSA material, thereby optimizing the process and the final structure.
[0031] Figures 1 to 10 Cross-sectional views of various stages in forming a semiconductor element 100 are shown according to some embodiments of the present invention. Figure 1 Semiconductor element 100 is indicated. In some embodiments, semiconductor element 100 may include substrate 110. Isolation structure 120 is formed in substrate 110. In some embodiments, isolation structure 120 may be made of a dielectric material (e.g., silicon oxide) and may also be referred to as shallow trench isolation (STI) structure.
[0032] A gate structure 130 is formed over a substrate 110. In some embodiments, the gate structure 130 may include a gate dielectric layer and a gate electrode located on the gate dielectric layer. In some embodiments, a hard mask 132 is formed over the gate structure 130. The hard mask 132 may be made of a dielectric material (e.g., silicon nitride). For example, a gate material and a hard mask material are deposited over the substrate 110 and patterned according to a predetermined pattern to form the gate structure 130 and the hard mask 132.
[0033] Gate spacer layers 134 are formed on opposite sidewalls of gate structure 130. In some embodiments, gate spacer layers 134 are made of a polar dielectric material (e.g., silicon nitride (SiN)). In some embodiments, the top surface of gate spacer layer 134 is substantially coplanar with the top surface of hard mask 132.
[0034] Source / drain regions 135 are formed in substrate 110 and located on opposite sides of gate structure 130. In some embodiments, source / drain regions 135 may be formed using a suitable implantation process.
[0035] A sacrificial layer 140 is formed on the substrate 110, covering the gate structure 130 and the source / drain region 135. In some embodiments, the sacrificial layer 140 is made of a low-polarity or substantially non-polar non-polar organic material. In some embodiments, this non-polar organic material may include polyethylene or other suitable non-polar organic materials.
[0036] like Figure 1 As shown, a photoresist layer 150 is coated on the sacrificial layer 140. Next, an exposure process is performed to pattern the photoresist layer 150 according to a predetermined pattern S12. After the exposure process, a developing tool can be used to develop and remove a portion of the photoresist layer 150, thereby forming an opening 155 in the photoresist layer 150. In some embodiments, the width of the opening 155 is greater than the shortest distance between the gate structures 130.
[0037] Please refer to Figure 2 The sacrificial layer 140 can be etched through the opening 155 of the patterned photoresist layer 150 to expose a portion of the gate spacer layer 134 and the source / drain region 135 located between the gate structure 130. In other words, the opening 155 extends vertically downward. In some embodiments, this etching process can be an anisotropic etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or other suitable processes, or combinations thereof.
[0038] Please refer to Figure 3After the etching process is completed, the patterned photoresist layer 150 can be removed by an ashing process and / or a stripping process. Next, a sacrificial layer 160 can be deposited within the opening 155 to fill it. In some embodiments, the sacrificial layer 160 is made of a oriented self-assembly material. The sacrificial layer 160 (DSA material) typically contains at least two polymers. When coated onto the substrate 110, for example by spin coating, these polymers are in a mixed state. In some embodiments, the polymer of the sacrificial layer 160 can be polystyrene (PS), polymethyl methacrylate (PMMA), polystyrene-b-polymethyl methacrylate (PS-b-PMMA) block copolymer, other suitable polymers, or combinations thereof. The polymer of the sacrificial layer 160 can be selected to have the desired molecular weight and proportions.
[0039] Please refer to Figure 4 After the sacrificial layer 160 is formed, an annealing process is performed. When the sacrificial layer 160 is annealed at a high temperature for a sufficient time to allow polymer migration, the polymers in the sacrificial layer 160 separate from each other according to their molecular weight. For example, one polymer migrates towards the gate spacer layer 134, forming a contact pattern feature 160A on the sidewall of the gate spacer layer 134; while the other polymer migrates away from the gate structure 130, forming a sacrificial feature 160B. In some embodiments, the contact pattern feature 160A contacts the gate spacer layer 134, the sacrificial layer 140, and the source / drain region 135 in the substrate 110. The contact pattern features 160A are spaced apart from each other by the sacrificial features 160B. In one embodiment, the top surface of the contact pattern feature 160A is higher than the top surface of the gate structure 130, and a portion of the contact pattern feature 160A may extend to a position directly above the corresponding gate structure 130. In some embodiments, one of the contact pattern features 160A has a curved inner sidewall and a curved outer sidewall. Furthermore, the thickness T1 of the contact pattern feature 160A is controlled by the molecular chain length and annealing time of the designed DSA material.
[0040] Please refer to Figure 5 Following the annealing process, a first stripping process is performed using tetramethylammonium hydroxide (TMAH) etchant to remove sacrificial feature 160B. Next, a second stripping process is performed to remove sacrificial layer 140. The second stripping process can be an organic wet stripping process to prevent damage to contact pattern feature 160A.
[0041] Please refer to Figure 6After completely removing the sacrificial feature 160B and the sacrificial layer 140, a dielectric layer 170 is formed on the substrate 110, which covers the gate structure 130 and the contact pattern feature 160A. In some embodiments, the dielectric layer 170 may be a spin-on dielectric layer (SOD) and is formed by spin-on and annealing processes on the substrate 110.
[0042] Please refer to Figure 7 A planarization process is performed to remove the top portion of the dielectric layer 170. In some embodiments, the planarization process may be a chemical mechanical polishing (CMP) process. After the planarization process, the top surface of the dielectric layer 170 is substantially level with the top surface of the contact pattern feature 160A.
[0043] Please refer to Figure 8 The contact pattern features 160A in the dielectric layer 170 can be removed by an etching process to form the space 175. In some embodiments, the etching process can be a wet etching process, such as a plasma etching process.
[0044] Please refer to Figure 9 Conductive material 180 fills space 175. The upper surface of conductive material 180 is higher than the upper surface of dielectric layer 170. In some embodiments, conductive material 180 may include metal.
[0045] Please refer to Figure 10 The conductive material 180 can be partially removed by an etch-back process or a planarization process. After the planarization process, the dielectric layer 170 is exposed. In some embodiments, the planarization process can be a chemical mechanical polishing (CMP) process. Furthermore, the remaining conductive material 180 in the dielectric layer 170 can be referred to as source / drain contacts 182. In this way, contact pattern features 160A can be replaced by source / drain contacts 182, and the source / drain contacts 182 generally inherit the outline of the contact pattern features 160A. The source / drain contacts 182 are arranged along the sidewalls of the gate spacer layer 134 and are electrically coupled to the source / drain regions 135 in the substrate 110. The source / drain contacts 182 are spaced apart by the dielectric layer 170. In some embodiments, an isolation structure 120 is located between the source / drain contacts 182. In some embodiments, the top surface of the source / drain contacts 182 is higher than the top surface of the gate structure 130. In some embodiments, the top surface of the source / drain contact 182 is higher than the top surface of the hard mask 132. The thickness T2 of each source / drain contact 182 is substantially the same as the thickness T1 of each contact pattern feature 160A. In some embodiments, the thickness T2 of each source / drain contact 182 is from about 15 nm to about 30 nm.
[0046] After planarization, source / drain contacts 184 can be formed in dielectric layer 170. Source / drain contacts 184 are located on one side of each gate structure 130, opposite to source / drain contacts 182. Source / drain contacts 184 contact the substrate 110 but not the gate structure 130. Source / drain contacts 184 are electrically coupled to source / drain regions 135 in the substrate 110. In some embodiments, source / drain contacts 184 comprise a conductive material. In some embodiments, the source / drain contacts 184, source / drain contacts 182, and the top surface of dielectric layer 170 are substantially coplanar. In some embodiments, the spacing G1 between source / drain contacts 182 is approximately 20 nm to approximately 40 nm.
[0047] The foregoing summary outlines several features of the embodiments, enabling those skilled in the art to better understand the nature of the invention. Those skilled in the art will understand that the invention can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.
[0048] [Symbol Explanation] 100: Semiconductor components 110: Substrate 120: Isolation structure 130: Gate structure 132: Hard mask 134: Gate spacer layer 135: Source / Drain Region 140: Sacrifice Layer 150: Photoresist layer 155: Opening 160: Sacrificial Layer 160A: Contact pattern characteristics 160B: Sacrifice Characteristics 170: Dielectric layer 175: Space 180: Conductive materials 182: Source / Drain Contact 184: Source / Drain Contacts S12: Pre-ordered pattern T1: Thickness T2: Thickness G1: Spacing.
Claims
1. A method for forming a semiconductor device, characterized in that, Include: Multiple gate structures are formed on the substrate; Multiple gate spacer layers are formed on the opposite sidewalls of the multiple gate structures, respectively; Multiple source / drain regions are formed in the substrate and on multiple opposite sides of the multiple gate structures, respectively; A first sacrificial layer is formed to cover the plurality of gate structures and the plurality of gate spacer layers; An opening is formed in the first sacrificial layer to expose portions of the plurality of gate spacer layers and the substrate; A second sacrificial layer is formed in the opening; A first annealing process is performed on the second sacrificial layer to separate a first material of the second sacrificial layer from a second material of the second sacrificial layer, wherein the first material is arranged along the plurality of sidewalls of the plurality of gate spacers and the plurality of source / drain regions; Remove the second material from the first sacrificial layer and the second sacrificial layer; The first material forms a dielectric layer on the substrate and covers the plurality of gate structures and the second sacrificial layer; as well as The first material of the second sacrificial layer is replaced with a plurality of first source / drain contacts.
2. The method of claim 1, wherein the second sacrificial layer comprises a directional self-assembling material.
3. The method of claim 1, wherein the first material of the second sacrificial layer extends directly above the plurality of gate structures.
4. The method according to claim 1, wherein, Further includes: After replacing the first material of the second sacrificial layer with the plurality of first source / drain contacts, a plurality of second source / drain contacts are formed in the dielectric layer, wherein the plurality of second source / drain contacts are separated from the plurality of gate spacer layers.
5. The method of claim 1, wherein the opening is wider than the distance between the plurality of gate structures.
6. The method according to claim 1, wherein, Further includes: Multiple hard masks are formed above the multiple gate structures, wherein the first material of the second sacrificial layer extends to the top surface of the multiple hard masks.
7. The method of claim 6, wherein the first material of the second sacrificial layer has two portions that are in contact with and separated from each other by the plurality of gate spacer layers.
8. The method of claim 1, wherein removing the first sacrificial layer and the second material further comprises: Perform a first stripping process to remove the second material; and A second stripping process is performed to remove the first sacrificial layer.
9. The method of claim 1, wherein forming the dielectric layer on the substrate further comprises: The material for performing a spin coating process to form the dielectric layer on the substrate; and A second annealing process is performed on the material of the dielectric layer to form the dielectric layer.
10. The method of claim 1, wherein the first sacrificial layer is formed of a nonpolar organic material.
11. A semiconductor element, characterized in that, Include: Multiple gate structures are located on the substrate; Multiple source / drain regions are located in the substrate and on opposite sides of the multiple gate structures, respectively; A dielectric layer is located on the substrate and covers the plurality of gate structures; Multiple gate spacer layers are respectively located on opposite sidewalls of the multiple gate structures; as well as Multiple first source / drain contacts are electrically coupled to the multiple source / drain regions and extend along the sidewalls of the multiple gate spacers, respectively extending to a position directly above the multiple gate structures.
12. The semiconductor device according to claim 11, wherein, Further includes: Multiple hard masks are located on the multiple gate structures, wherein the multiple first source / drain contacts extend to the multiple top surfaces of the multiple hard masks.
13. The semiconductor device of claim 12, wherein the plurality of top surfaces of the plurality of first source / drain contacts are higher than the plurality of top surfaces of the plurality of hard masks.
14. The semiconductor element according to claim 11, wherein, Further includes: Multiple second source / drain contacts are electrically coupled to the multiple source / drain regions, wherein the multiple second source / drain contacts are separated from the multiple gate spacers.
15. The semiconductor device of claim 14, wherein the plurality of first source / drain contacts and the plurality of second source / drain contacts are substantially level with the top surface of the dielectric layer.
16. The semiconductor device of claim 11, wherein the gate spacer layer comprises a polar dielectric material.
17. The semiconductor device of claim 11, wherein the plurality of first source / drain contacts have a distance ranging from 20 nanometers to 40 nanometers between them.
18. The semiconductor device of claim 11, wherein one of the plurality of first source / drain contacts has a thickness ranging from 15 nanometers to 30 nanometers.
19. The semiconductor device according to claim 11, wherein, Further includes: An isolation structure is located in the substrate and between the plurality of first source / drain contacts.
20. The semiconductor device of claim 11, wherein one of the plurality of first source / drain contacts has a curved inner sidewall and a curved outer sidewall.