Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes: an interposer; a first semiconductor device disposed on the interposer; a second semiconductor device on the interposer and spaced apart from the first semiconductor device; and a heat dissipation plate disposed on upper surfaces of the first semiconductor device and the second semiconductor device, and having a dam disposed in an edge portion of the heat dissipation plate.

Description

Technical Field

[0001] The present invention relates to semiconductor packages, and more specifically, to semiconductor packages comprising a semiconductor chip stack structure and a method for manufacturing the same. Background Technology

[0002] With the rapid development of the electronics industry and the demands of users, electronic devices are becoming increasingly compact and lightweight. Correspondingly, semiconductor packages used in electronic devices are also becoming increasingly compact and lightweight. Furthermore, semiconductor packages require high reliability, high performance, and high capacity. To achieve miniaturization, weight reduction, high performance, high capacity, and high reliability, ongoing research and development is being conducted on semiconductor chips, including those with through-silicon via (TSV) structures, and semiconductor packages with chip-stacked structures (where semiconductor chips are stacked). Summary of the Invention

[0003] Various aspects of the present invention provide chip-type semiconductor packages (which include semiconductor devices sealed on an interposer and are capable of improving heat dissipation and warpage) and methods of manufacturing semiconductor packages.

[0004] Furthermore, the inventive concept is not limited to those described above, and other aspects not described herein will be clearly understood by those skilled in the art through the following description.

[0005] According to one aspect of the present invention, a semiconductor package is provided, the semiconductor package comprising: an interposer; a first semiconductor device disposed on the interposer; a second semiconductor device located on the interposer and spaced apart from the first semiconductor device; and a heat sink disposed on the upper surfaces of the first semiconductor device and the second semiconductor device, and having a dam disposed in an edge portion of the heat sink.

[0006] According to another aspect of the present invention, a semiconductor package is provided, the semiconductor package comprising: a package substrate; a chip package disposed on the package substrate; and a heat dissipation structure disposed on the chip package. The chip package comprises: an interposer; a first semiconductor device disposed on the interposer; a second semiconductor device disposed on the interposer and spaced apart from the first semiconductor device; an intermediate heat sink disposed on the upper surfaces of the first semiconductor device and the second semiconductor device, and having a dam disposed along an edge portion of the intermediate heat sink; and a sealant disposed between the interposer and the intermediate heat sink and sealing the first semiconductor device and the second semiconductor device.

[0007] According to another aspect of the present invention, a semiconductor package is provided, the semiconductor package comprising: a package substrate; a chip package disposed on the package substrate; a heat dissipation structure disposed on the chip package; and a thermal interface material (TIM) disposed between the chip package and the heat dissipation structure. The chip package further comprises: an interposer; a first semiconductor device disposed on the interposer; a second semiconductor device located on the interposer and spaced apart from the first semiconductor device; and an intermediate heat sink disposed on the upper surfaces of the first semiconductor device and the second semiconductor device, and having a dam surrounding the TIM in an edge portion of the intermediate heat sink.

[0008] According to another aspect of the present invention, a method for manufacturing a semiconductor package is provided, the method comprising: preparing a package structure comprising a plurality of initial chip packages; forming an intermediate heat sink structure on an upper surface of the package structure; forming a chip package by monolithizing the package structure and the intermediate heat sink structure; and mounting the chip package on a package substrate. The chip package comprises: an interposer; a first semiconductor device disposed on the interposer; a second semiconductor device located on the interposer and spaced apart from the first semiconductor device; and an intermediate heat sink, which is part of the intermediate heat sink structure, disposed on the upper surfaces of the first semiconductor device and the second semiconductor device, and having a dam formed in an edge portion of the intermediate heat sink. Attached Figure Description

[0009] The embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a cross-sectional view of a semiconductor package according to an embodiment; Figures 2A to 2C All are shown Figure 1 A conceptual diagram of the shape of a dam located on the upper surface of an intermediate heat sink in a semiconductor package; Figures 3A to 3C These are conceptual diagrams and photographs illustrating defects in semiconductor packages as comparative examples; Figures 4A to 4C All are shown Figure 1 A cross-sectional view of the structure of the first semiconductor device in the semiconductor package; Figures 5A to 5D This is a cross-sectional view of a semiconductor package according to an embodiment; Figure 6A and Figure 6B This is a cross-sectional view of the system package according to an embodiment; Figure 7A and Figure 7B These are, respectively, a perspective view and a cross-sectional view of the system package according to the embodiment; Figure 8A and Figure 8B This is a cross-sectional view of the system package according to an embodiment; Figures 9A to 9I This is a cross-sectional view schematically illustrating a method for manufacturing a system package according to an embodiment; Figures 10A to 10C It shows the manufacturing process in more detail. Figure 9A A cross-sectional view of the process of the first packaging structure. Detailed Implementation

[0010] The embodiments will be described in detail below with reference to the accompanying drawings. The same elements in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0011] Throughout this specification, when a component is described as “comprising” a particular element or group of elements, it should be understood that the component is formed solely by the element or group of elements, or that the element or group of elements may be combined with other elements to form the component, unless the context clearly and / or explicitly describes otherwise.

[0012] It will be understood that when a component is referred to as being “connected” or “coupled” to another component or “on” another component, it may be directly connected or coupled to the other component or on the other component, or there may be intermediate components. Conversely, when a component is referred to as being “directly connected” or “directly coupled” to another component, or “in contact” or “with” another component (or using any form of the word “in contact”), there are no intermediate components at the point of contact.

[0013] As used herein, components described as “electrically connected” or “electrically coupled” are configured to allow electrical signals to be transmitted from one component to another (although such electrical signals may be attenuated in strength as they are transmitted and may be transmitted selectively).

[0014] Spatial relative terms (such as “below,” “under,” “down,” “above,” “top,” “bottom,” “front,” “back,” etc.) may be used herein for ease of description to describe positional relationships, such as those shown in the accompanying figures. It will be understood that spatial relative terms also encompass different orientations of the device, in addition to those depicted in the figures.

[0015] As used herein, terms such as “identical,” “equal,” “plane,” “coplanar,” “parallel,” “uniform,” and “perpendicular” encompass identity or near-identity (including possible variations, such as those resulting from manufacturing processes). Unless the context or other statements otherwise indicate otherwise, the term “substantially” may be used herein to emphasize this meaning.

[0016] Figure 1 This is a cross-sectional view of a semiconductor package according to an embodiment, and Figures 2A to 2C All are shown Figure 1 A conceptual diagram of the shape of a dam located on the upper surface of a central heat sink in a semiconductor package. Figures 3A to 3C These are conceptual diagrams and photographs illustrating defects in semiconductor packages as comparative examples.

[0017] refer to Figures 1 to 2C The semiconductor package 1000 in this embodiment may include an interposer 1100, a first semiconductor device 1200, a second semiconductor device 1300, an intermediate heat sink 1400, and a sealant 1500.

[0018] Interposer 1100 can mediate signal transmission between the first semiconductor device 1200 and the second semiconductor device 1300, or transmit signals between the first semiconductor device 1200 and the second semiconductor device 1300. For example, the first semiconductor device 1200 and the second semiconductor device 1300 can be mounted on interposer 1100 and electrically connected to each other through interposer 1100. Furthermore, interposer 1100 can also mediate signal transmission between the first semiconductor device 1200 and the package substrate (see [link to package substrate]). Figure 6A The first semiconductor device 1200 and the second semiconductor device 1300 are used to transmit signals, power, etc. between the first semiconductor device 1200 and the package substrate 1600. For example, the interposer 1100 can be mounted on the package substrate 1600, and the first semiconductor device 1200 and the second semiconductor device 1300 can be electrically connected to the package substrate 1600.

[0019] Intermediate layer 1100 may include a body layer 1101, a wiring layer 1110, a through electrode 1120, and a first external connection terminal 1150. Body layer 1101 may include, for example, silicon (Si). Accordingly, intermediate layer 1100 may be a Si intermediate layer. However, intermediate layer 1100 is not limited to a Si intermediate layer.

[0020] Wiring layer 1110 may be disposed on body layer 1101 and may include interlayer insulating layer and wiring. Wiring can electrically connect first semiconductor device 1200 to second semiconductor device 1300. In addition, wiring can electrically connect through electrode 1120 to pads located on interposer layer 1100.

[0021] The through-electrode 1120 can extend longitudinally in the vertical direction to penetrate the body layer 1101. Because the body layer 1101 comprises Si, the through-electrode 1120 can be a through-silicon via (TSV). The through-electrode 1120 can extend into the wiring layer 1110 and can be electrically connected to the wiring of the wiring layer 1110. For example, the through-electrode 1120 can overlap with the wiring layer 1110 in the horizontal direction. Furthermore, the through-electrode 1120 can be electrically connected to the first external connection terminal 1150 via a pad located on the lower surface of the interposer layer 1100. The specific structure of the through-electrode 1120 is described in... Figure 4A The first semiconductor device 1200 is described in more detail in the description of the first semiconductor device.

[0022] A first external connection terminal 1150 may be disposed on a pad located on the lower surface of the interposer layer 1100. The first external connection terminal 1150 may be electrically connected to the through electrode 1120 via the pad. The first external connection terminal 1150 may include a post 1152 and solder 1154. In some embodiments, the first external connection terminal 1150 may consist only of solder 1154. For example, the first external connection terminal 1150 may be formed of solder 1154.

[0023] Pillar 1152 may include, for example, nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), gold (Au), or any combination thereof. In some embodiments, pillar 1152 may serve as a pad and may include Cu. Accordingly, pillar 1152 may be a bump pad, a Cu pad, or a Cu pillar. In some embodiments, when pillar 1152 is used as a pad, a separate pad may not be formed on the lower surface of the interposer 1100. For example, in some embodiments, the pad and pillar 1152 may be integrally formed.

[0024] Solder 1154 may be disposed on post 1152. Solder 1154 may include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), and / or any alloy thereof. For example, solder 1154 may include Sn, Sn-Ag, Sn-Au, Sn-Cu, Sn-Bi, Sn-Zn, Sn-Ag-Cu, Sn-Ag-Bi, Sn-Ag-Zn, Sn-Cu-Bi, Sn-Cu-Zn, Sn-Bi-Zn, etc. In some embodiments, solder 1154 may be a bump or solder bump.

[0025] In the semiconductor package 1000 of this embodiment, the interposer 1100 may be a 2.5D interposer. However, the interposer 1100 is not limited to a 2.5D interposer. For example, the interposer 1100 may be a 2.3D interposer. For reference, the interposer may include both 2.5D and 2.3D interposers. Furthermore, in some embodiments, the interposer may be subdivided based on its structure (e.g., including Si bridges). Accordingly, interposers other than 2.5D interposers may be referred to as 2.xD interposers.

[0026] The 2.5D interposer may be a Si interposer and may include a TSV. The 2.3D interposer may be an organic or inorganic interposer. Organic interposers may use polyimide (PI), benzocyclobutene (BCB), and polybenzoxazole (PBO) as the host layer, while inorganic interposers may use ceramic or glass as the host layer. When the 2.3D interposer includes a through electrode, depending on the material of the host layer, the through electrode may be a through dielectric pathway (TDV) or a through glass pathway (TGV). In some embodiments, the 2.3D interposer may be a panel-level package (PLP) interposer or a redistribution layer (RDL) interposer (e.g., a redistribution interposer with Si bridges).

[0027] The first semiconductor device 1200 can be mounted on the interposer layer 1100 via the first connection terminal 300. Figure 1 The first semiconductor device 1200 is shown arranged on the left side of the interposer 1100 in the x-direction. However, the position of the first semiconductor device 1200 is not limited to this.

[0028] The first semiconductor device 1200 may include a memory device. For example, the first semiconductor device 1200 may include a volatile memory device (such as dynamic random access memory (DRAM) or static random access memory (SRAM)) or a non-volatile memory device (such as flash memory, phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM)). Furthermore, when the first semiconductor device 1200 includes a memory device, the first semiconductor device 1200 may have a single-chip structure or a package structure. In the semiconductor package 1000 of this embodiment, the first semiconductor device 1200 may, for example, include a high-bandwidth memory (HBM) package. (See reference...) Figures 4A to 4C The HBM package structure of the first semiconductor device 1200 is described in more detail. Throughout this application, the structure of an element or device, or the element structure or device structure, can be the element or device itself, or it can be a device or element having a structure substantially the same as that of the device or element. For example, when a wafer or substrate has a chip structure or package structure, the wafer or substrate may include the same structure as the chip or package, except for singulation (e.g., except for the external shape of the chip / package). For example, a chip structure may include all the internal structures of a chip, and a package structure may include all the internal structures of a package. As another example, when a substrate or wafer includes a chip / package structure, the substrate / wafer may include multiple chips / packages.

[0029] The first semiconductor device 1200 is not limited to an HBM package. For example, the first semiconductor device 1200 may have a general package structure. In a general package structure, the first semiconductor device 1200 may include an upper package substrate and a plurality of memory chips stacked on the upper package substrate. Furthermore, the memory chips may be stacked on the upper package substrate and electrically connected to the upper package substrate and / or electrically connected to each other via bonding leads, or they may be stacked on the upper package substrate and electrically connected to the upper package substrate via bumps and TSVs.

[0030] The second semiconductor device 1300 can be mounted on the interposer 1100 via the second connection terminal 1350. Figure 1 The second semiconductor device 1300 is shown to be disposed adjacent to and / or spaced apart from the first semiconductor device 1200 on the right side of the interposer 1100 in the x-direction. However, the position of the second semiconductor device 1300 is not limited to this. For example, the first semiconductor device 1200 may be disposed on the right side of the interposer 1100 in the x-direction, and the second semiconductor device 1300 may be disposed on the left side of the interposer 1100 in the x-direction.

[0031] The second semiconductor device 1300 may have a chip or package structure. In the semiconductor package 1000 of this embodiment, the second semiconductor device 1300 may have a chip structure. For example, the second semiconductor device 1300 may include a logic chip. Accordingly, multiple logic devices may be included in the second semiconductor device 1300. Logic devices may include, for example, AND, NAND, OR, NOR, XOR, XNOR, inverters (INV), adders (ADD), delay units (DLY), filters (FIL), multiplexers (MXT / MXIT), OR / AND / INV (OAI), AND / OR (AO), AND / OR / INV ​​(AOI), D flip-flops, reset flip-flops, master-slave flip-flops, latches, counters, or buffers. Logic devices can perform various signal processing, such as analog signal processing, analog-to-digital (A / D) conversion, or control. The second semiconductor device 1300 may be a central processing unit (CPU) chip, a microprocessor unit (MPU) chip, a graphics processing unit (GPU) chip, a neural processing unit (NPU) chip, a system-on-glass (SOG) chip, an application-specific integrated circuit (ASIC) chip, an application processor (AP) chip, or a control chip, and may have its corresponding functions.

[0032] In the semiconductor package 1000 of this embodiment, the second semiconductor device 1300 may have a chip structure, a system-on-a-chip (SoC) structure, or a chiplet structure. An SoC structure can have a structure that integrates multiple systems into a single chip. Accordingly, the second semiconductor device 1300 with an SoC structure can perform computing functions, data storage, analog and digital signal conversion, etc., within a single chip. On the other hand, a chiplet structure can have a structure that divides logic chips into separate chips for each function and electrically connects the individual chips to each other. The second semiconductor device 1300 with a chiplet structure can overcome the performance limitations of a single chip.

[0033] In some embodiments, the second semiconductor device 1300 may include a communication support device. However, in some embodiments, the communication support device may be provided separately as another chip (e.g., a modem chip) and may be arranged on the interposer 1100 in a configuration electrically coupled to the second semiconductor device 1300.

[0034] The second semiconductor device 1300 may include a chip body and an active layer. The chip body may constitute the body of the second semiconductor device 1300 and may include Si. However, the material of the chip body is not limited to Si. For example, the chip body may include other semiconductor materials (such as germanium (Ge) or Si-Ge) or III-V compounds (such as GaP, GaAs, or GaSb).

[0035] The active layer can be disposed beneath the chip body and may include an integrated circuit layer and a wiring layer. The integrated circuit layer may include multiple integrated devices. The multiple integrated devices may include, for example, the logic devices described above. The wiring layer may be disposed beneath the integrated circuit layer. The wiring layer may include interlayer insulating layers and wiring. The wiring may be arranged in two or more layers, and the wiring in different layers may be electrically connected to each other through vertical paths.

[0036] The lower surface of the second semiconductor device 1300 can be the front surface, which is an active surface, and the upper surface of the second semiconductor device 1300 can be the rear surface, which is a non-active surface. For example, the lower or bottom surface of the chip body where the wiring layer is disposed can correspond to or be the front surface of the second semiconductor device 1300, and the upper or top surface of the chip body can correspond to or be the rear surface of the second semiconductor device 1300.

[0037] An intermediate heat sink 1400 can be disposed on the first semiconductor device 1200, the second semiconductor device 1300, and the sealant 1500. For example, the intermediate heat sink 1400 can completely cover the upper surfaces of the first semiconductor device 1200, the second semiconductor device 1300, and the sealant 1500. The intermediate heat sink 1400 can be in the shape of a flat plate or in the shape of a dam structure formed on a flat plate. For example, as... Figures 2A to 2C As shown, the intermediate heat sink 1400 can be in the shape of a dam formed on a rectangular plate, for example, in a rectangular shape. For example, the thickness of the plate can be less than 10% of both the width and length of the plate, and it can have flat upper and lower surfaces that are parallel to each other.

[0038] The intermediate heat sink 1400 may include a lower metal layer 1420, an intermediate metal layer 1440, and an upper metal layer 1460. For example, the intermediate heat sink 1400 may be simply referred to as a heat sink. Each layer of the intermediate heat sink 1400 may include one of aluminum (Al), copper (Cu), tungsten (W), nickel (Ni), titanium (Ti), or gold (Au). However, the material of each layer of the intermediate heat sink 1400 is not limited to the materials described above. For example, each layer of the intermediate heat sink 1400 may include materials with high thermal conductivity (e.g., greater than 170 or greater than 200 W / m Kelvin). 1 ·K 1 And various other metallic materials that are easy to manufacture.

[0039] Each layer of the intermediate heat sink 1400 can be formed using various processes, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or electroplating. In the case of PVD, sputtering can be used. In the case of electroplating, both electroplating and electroless plating can be used. For reference, electroplating can be a process that uses the principle of electrolysis to deposit a metal film onto the surface of another metal, and / or it can be electrochemical plating. Electroless plating can be electroplating without the use of electrolysis. Electroless plating can be a process that deposits a film by initiating the chemical reduction of metal ions on the surface of the object to be plated. Electroless plating can be chemical electroplating.

[0040] Figure 1 The lower metal layer 1420 of the intermediate heat sink 1400 can be in the shape of a flat plate with uniform thickness. For example, the lower metal layer 1420 can be in the shape of a rectangular flat plate.

[0041] The intermediate metal layer 1440 may include a flat substrate 1440B and a protrusion 1440P located on the peripheral portion of the upper surface of the substrate 1440B. The substrate 1440B may be a rectangular flat plate similar to the lower metal layer 1420. The protrusion 1440P may be of various shapes on the upper surface of the substrate 1440B. For example, as... Figure 2A As shown, the protrusion 1440P can be arranged in a rectangular ring shape (e.g., a continuous rectangular ring shape) on the peripheral portion of the upper surface of the base 1440B. Figure 2B As shown, the protrusion 1440P1 can be L-shaped and can be arranged adjacent to each of the four vertices of the upper surface of the base 1440B. Figure 2C As shown, the protrusion 1440P2 can be linear and can be arranged adjacent to each of the four sides of the upper surface of the base 1440B. On the other hand, the shape of the protrusion 1440P is not limited to the three shapes described above. For example, the protrusion 1440P can be in various shapes surrounding and / or along the peripheral portion of the upper surface of the base 1440B.

[0042] The upper metal layer 1460 can cover the intermediate metal layer 1440 with a uniform thickness. Accordingly, the portion of the upper metal layer 1460 corresponding to or contacting the substrate 1440B of the intermediate metal layer 1440 can be flat, and the portion of the upper metal layer 1460 corresponding to or contacting the protrusion 1440P of the intermediate metal layer 1440 can be protruding. The protrusion 1440P of the intermediate metal layer 1440 and the protruding portion of the upper metal layer 1460 covering the protrusion 1440P can form a dam DAM. Furthermore, the shape of the dam DAM can be determined based on the shape of the protrusion 1440P of the intermediate metal layer 1440. For example, as... Figure 2A As shown, when the protrusion 1440P is in the shape of a rectangular ring, a dam DAM in the shape of a rectangular ring can be formed. Figure 2B As shown, when the protrusion 1440P1 is L-shaped, an L-shaped retaining dam DAM1 can be formed. Figure 2C As shown, when the protrusion 1440P2 is linear, a dam DAM2 in a linear shape can be formed. For example, the upper metal layer 1460 can be conformally formed on the intermediate metal layer 1440 to completely overlap with the intermediate metal layer 1440 in the vertical direction. For example, the dam DAM1 can include a plurality of discrete L-shaped portions, and each L-shaped portion can be arranged to be adjacent to a corresponding vertex of the four vertices of the rectangular upper surface of the heat sink 1400. As another example, the dam DAM2 can include a plurality of linear shaped portions, and each linear shaped portion can extend along a corresponding side of the four sides of the rectangular upper surface of the heat sink 1400.

[0043] For reference, in semiconductor package 1000 and heat dissipation structure (see...) Figure 6A 1700) through thermal interface materials (TIM) (see 1700) Figure 6A In a structure where TIM 1800 and TIM 1800 are coupled together, the dam DAM can surround TIM 1800 and prevent TIM 1800 from being pumped out of the dam during temperature cycling (TC) reliability testing, etc. As a result, because TIM 1800 is not pumped out and remains only inside the dam DAM of the intermediate heat sink 1400, the adhesion strength between the semiconductor package 1000 and the heat dissipation structure 1700 can be increased, and the heat dissipation capacity through TIM 1800 can be improved. When TIM 1800 is pumped out, the amount of TIM 1800 remaining on the heat sink 1400 may be insufficient, and therefore, the adhesion strength between the semiconductor package 1000 and the heat dissipation structure 1700 may decrease. Furthermore, because the space between them is filled with an air layer as much as the amount of TIM 1800 pumped out, the heat dissipation capacity through TIM 1800 may also decrease.

[0044] The semiconductor package 1000 can be mounted on the package substrate via the first external connection terminal 1150 (see...). Figure 6A On the 1600), and the adhesive strength between the heat dissipation structure 1700 and the semiconductor package 1000 can be increased (e.g., because the heat dissipation structure 1700 adheres to the upper surface of the package substrate). Accordingly, warpage of the semiconductor package 1000 can be improved, and defects such as non-wet / short circuits of the first external connection terminal 1150 can be improved.

[0045] refer to Figures 3A to 3C The comparative example semiconductor package Com. shown in the diagram briefly describes defects such as poor wetting / short circuit of the first external connection terminal 1150. The chip-type package structure, in which a semiconductor device (not shown) is mounted on an interposer InP and sealed with a sealant M, can be a molded interposer (MIP) chip or a chip package. In this disclosure, a chip-type package, a chip-type semiconductor package, or a chip package can be a package in which a semiconductor device / chip is mounted on an interposer and sealed on the interposer with a sealant. A chip package, a chip-type package, or a chip-type semiconductor package may include additional structures, such as multiple semiconductor chips / devices, a heat sink, an underfill layer, connection terminals, etc. The comparative example semiconductor package Com. having a chip package structure can be mounted on a package substrate PCB via external connection terminals SB. Each external connection terminal SB may include a pillar P and solder S. Furthermore, although not shown, an underfill may fill the gap between the comparative example semiconductor package Com. and the package substrate PCB.

[0046] The coefficient of thermal expansion of the sealant M and / or the underfill can differ significantly from the coefficient of thermal expansion of the interposer InP and / or the semiconductor device in the comparative example semiconductor package Com. Accordingly, as Figure 3A As shown, warping may occur in the semiconductor package Com. of the comparative example. Accordingly, short-circuit defects may occur (where adjacent external connection terminals SB are electrically connected to each other at the periphery of the interposer InP), and poor wetting defects may occur (where the external connection terminals SB separate from the package substrate PCB or the interposer InP at the center of the interposer InP). For reference, Figure 3B and Figure 3C yes Figure 3A Micrographs of cross sections of regions A and B.

[0047] In contrast, the semiconductor package 1000 of this embodiment may include an intermediate heat sink 1400, and a dammed optical arc device (DAM) may be formed on the upper surface of the intermediate heat sink 1400. Accordingly, in a structure in which the semiconductor package 1000 is mounted on a package substrate 1600 and coupled to a heat dissipation structure 1700 via a TIM 1800, the TIM 1800 may be surrounded by the dammed DAM and held in place during TC reliability testing or other processes without being pumped out. Therefore, the bond strength to the heat dissipation structure 1700 can be increased, and the warpage of the semiconductor package 1000 can be improved. As a result, due to the improvement in the warpage of the semiconductor package 1000, defects such as poor wetting / short circuits of the first external connection terminal 1150 can be significantly improved.

[0048] In the semiconductor package 1000 of this embodiment, a case is shown where the intermediate heat sink 1400 has three layers; however, the number of layers in the intermediate heat sink 1400 is not limited to three. Furthermore, the intermediate metal layer 1440 may not include the substrate 1440B, or the upper metal layer 1460 may be omitted. Figures 5A to 5D The description provides a more detailed account of the various structures of the intermediate heat sink.

[0049] The sealant 1500 can cover and seal the first semiconductor device 1200 and the second semiconductor device 1300 located on the interposer layer 1100. For example... Figure 1 As shown, the sealant 1500 may not cover the upper surfaces of the first semiconductor device 1200 and the second semiconductor device 1300. For example, the upper surface of the sealant 1500 may be coplanar with the upper surfaces of the first semiconductor device 1200 and the second semiconductor device 1300. This structure may originate from a back-side grinding process of the sealant 1500. However, in some embodiments, the upper surface of at least one of the first semiconductor device 1200 and the second semiconductor device 1300 (e.g., the first semiconductor device 1200) may be covered by the sealant 1500.

[0050] Sealant 1500 may include insulating materials, such as thermosetting resins (e.g., epoxy resins), thermoplastic resins (e.g., polyimides), or resins containing reinforcing materials (e.g., inorganic fillers). For example, sealant 1500 may include Ajinomoto ABF (absorbent polymer film), FR-4, BT resin, etc. Furthermore, sealant 1500 may include molding materials (e.g., epoxy molding compounds (EMC)) or photosensitive materials (e.g., photoimaging sealant (PIE)). However, the materials of sealant 1500 are not limited to those described above.

[0051] On the other hand, the bottom filler 1520 can fill the gap between the first semiconductor device 1200 and the interposer 1100, and the gap between the second semiconductor device 1300 and the interposer 1100. Furthermore, the bottom filler 1520 can fill the gap between the first connection terminals 300 and the gap between the second connection terminals 1350. On the other hand, the bottom filler 1520 can protrude from the side surface (e.g., in the horizontal direction) of each of the first semiconductor device 1200 and the second semiconductor device 1300, and can cover at least a portion of the side surface of each of the first semiconductor device 1200 and the second semiconductor device 1300. Furthermore, when the gap between the first semiconductor device 1200 and the second semiconductor device 1300 is narrow, the bottom filler 1520 can fill the gap between the first semiconductor device 1200 and the second semiconductor device 1300, such as... Figure 1 As shown in the image.

[0052] In some embodiments, the underfill 1520 may be replaced by an adhesive layer or adhesive film. The adhesive layer or adhesive film may, for example, comprise a non-conductive film (NCF). For instance, NCF can be used as an adhesive layer when semiconductor chips are bonded using thermocompression bonding (TCB) in a semiconductor chip stacking process. However, the material of the adhesive layer or adhesive film is not limited to NCF.

[0053] The semiconductor package 1000 of this embodiment may have a chip-type package structure in which a first semiconductor device 1200 and a second semiconductor device 1300 are sealed on an interposer 1100 with a sealant 1500. The chip-type package may be a MIP chip or a chip package. The semiconductor package 1000 of this embodiment may have a chip package structure including an intermediate heat sink 1400 on its upper side / upper portion. In addition, a dam DAM may be formed on the peripheral portion of the upper surface of the intermediate heat sink 1400. For example, the dam DAM may be formed in the upper portion of the intermediate heat sink 1400 and along the edge portion of the intermediate heat sink 1400. Accordingly, in the structure in this embodiment where the semiconductor package 1000 is coupled to the heat dissipation structure 1700 via a TIM 1800, the dam DAM can prevent the TIM 1800 from being pumped out. Therefore, the adhesive strength between the semiconductor package 1000 and the heat dissipation structure 1700 can be increased, and the heat dissipation capability via the TIM 1800 can be improved. Furthermore, due to the increased adhesive strength between the heat dissipation structure 1700 and the semiconductor package 1000, the warping of the semiconductor package 1000 can be improved, and defects such as poor wetting / short circuit of the first external connection terminal 1150 can be improved.

[0054] Figures 4A to 4C It is shown Figure 1A cross-sectional view of the structure of the first semiconductor device 1200 in the semiconductor package 1000. (Compared to...) Figure 1 Let's refer to each other. Figures 4A to 4C The following description is given, and the above text is in... Figures 1 to 3C The information provided in the description may be briefly described or omitted.

[0055] refer to Figure 4A In the semiconductor package 1000 of this embodiment, the first semiconductor device 1200 may have an HBM package structure. For example, the first semiconductor device 1200 may include a substrate chip 100, a memory chip 200, a first connection terminal 300, and an internal sealant 400.

[0056] The substrate chip 100 may include a chip body 101, an active layer 110, a through electrode 120, a bonding pad 130, and a protective layer 140. For example... Figure 4A As shown, the size of the substrate chip 100 may be larger than the size of the memory chip 200 disposed thereon. However, the size of the substrate chip 100 is not limited thereto. For example, in some embodiments, the size of the substrate chip 100 may be the same as or substantially the same as the size of the memory chip 200.

[0057] The chip body 101 may include, for example, semiconductor elements such as silicon (Si) or germanium (Ge). In some embodiments, the chip body 101 may include compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The chip body 101 may have a silicon-on-insulator (SOI) structure. For example, the chip body 101 may include a buried oxide (BOX) layer. The chip body 101 may include structures such as conductive regions, for example, doped wells or doped source / drain regions. The chip body 101 may have various device isolation structures, such as shallow trench isolation (STI) structures. The buried structure, layer, or pattern may be a structure, pattern, or layer that is at least partially covered by another layer or pattern. For example, the top surface of the buried layer or pattern may be covered by a capping layer or capping pattern. For example, the top surface of the buried layer or pattern may be at a lower height than the top surface of the capping layer or capping pattern.

[0058] Active layer 110 may include an integrated circuit layer and a wiring layer located on the integrated circuit layer. The integrated circuit layer may include various types of devices. For example, the integrated circuit layer may include various active and / or passive devices, such as transistors, logic devices, memory devices, system-on-a-scale integration (LSI), complementary metal-oxide-semiconductor (CMOS) imaging sensors (CIS), or microelectromechanical systems (MEMS). Transistors may include, for example, bipolar junction transistors (BJTs) or field-effect transistors (FETs), such as planar FETs or FinFETs. Memory devices and logic devices are designed for… Figure 1 The first semiconductor device 1200 and / or the second semiconductor device 1300 of the semiconductor package 1000 are the same as the memory devices and logic devices described.

[0059] The wiring layer can electrically connect at least two devices to each other, connect devices to conductive regions of the chip body 101, or connect devices to the first connection terminal 300. Furthermore, the wiring layer can electrically connect the through electrode 120 and the first connection terminal 300 to each other. The wiring layer may include, for example, wiring and contacts and / or vias. In the first semiconductor device 1200 of this embodiment, the active layer 110 may be disposed below the chip body 101 and the through electrode 120. However, in some embodiments, the active layer 110 may be disposed above the chip body 101 and the through electrode 120.

[0060] In the first semiconductor device 1200 of this embodiment, the substrate chip 100 may include multiple logic devices in the integrated circuit layer of the active layer 110. The substrate chip 100 may be disposed below the memory chip 200 and configured to integrate signals of the memory chip 200, transmit integrated signals to the outside, and transmit external signals and power to the memory chip 200. For example, the substrate chip 100 may be a buffer chip or an interface chip.

[0061] In some embodiments, the base chip 100 may include a controller configured to control signal transmission between the memory chip 200 and external devices. When the base chip 100 includes a controller, the base chip 100 may be a logic chip or a control chip. Furthermore, in some embodiments, the base chip 100 may include a power management integrated circuit (PMIC) configured to manage power or clock. For reference, when the base chip 100 is a buffer chip or the like, the memory chip 200 may be a core chip.

[0062] In the first semiconductor device 1200 of this embodiment, the substrate chip 100 is not limited to a buffer chip or a logic chip. For example, the substrate chip 100 may include multiple memory devices in the integrated circuit layer of the active layer 110. Accordingly, in some embodiments, the substrate chip 100 may include a memory chip.

[0063] The through electrode 120 can penetrate the chip body 101 and extend longitudinally from the upper surface to the lower surface of the chip body 101 in a vertical direction. In some embodiments, the through electrode 120 can extend into the interior of the active layer 110. In the first semiconductor device 1200 of this embodiment, the chip body 101 may include Si, therefore, the through electrode 120 may be a TSV.

[0064] The through-electrode 120 may be columnar and may include a barrier layer on its outer surface and a buried conductive layer therein. The barrier layer may include at least one material selected from Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, and NiB. The buried conductive layer may include at least one material selected from Cu, Cu alloys (such as CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, or CuW), W, W alloys, Ni, Ru, and Co. In some embodiments, an insulating layer may be disposed between the through-electrode 120 and the chip body 101 and / or between the through-electrode 120 and the active layer 110. The insulating layer may include, for example, an oxide layer, a nitride layer, a carbide layer, a polymer, or any combination thereof.

[0065] Connection pads 130 may be disposed on the upper surface of the chip body 101 and may be electrically connected to and / or contact the through electrode 120. Connection pads 130 may include at least one of aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), or gold (Au). In the first semiconductor device 1200 of this embodiment, the connection pads 130 of the substrate chip 100 may include Cu. However, the material of the connection pads 130 is not limited to Cu.

[0066] The protective layer 140 may be disposed on the upper surface of the chip body 101. The protective layer 140 may include, for example, an oxide layer, a nitride layer, a carbide layer, a polymer, or any combination thereof. In the first semiconductor device 1200 of this embodiment, the protective layer 140 may have a single-layer or multi-layer structure.

[0067] The connection pads 130 may be arranged in a configuration that penetrates at least a portion of the protective layer 140. For example, the connection pads 130 may have a configuration that (e.g., in the vertical direction) completely penetrates the protective layer 140 or penetrates the upper side / upper portion of the protective layer 140, and may be arranged in a configuration that is embedded in the protective layer 140. The connection pads 130 may be electrically connected to and / or contact the through electrode 120 on the upper surface of the chip body 101 or inside the protective layer 140. In some embodiments, although not shown, the protective layer may also be arranged on the lower surface of the active layer 110.

[0068] Memory chips 200 can be stacked on substrate chip 100. In the first semiconductor device 1200 of this embodiment, eight memory chips 200 (e.g., first to eighth memory chips 200-1 to 200-8) can be stacked on substrate chip 100. However, the number of memory chips 200 stacked on substrate chip 100 is not limited to eight. For example, two to seven memory chips 200 or nine or more memory chips 200 can be stacked on substrate chip 100.

[0069] For reference, in the first semiconductor device 1200, the number of memory chips 200 can be 4n (where n is a natural number). Accordingly, the first semiconductor device 1200 may include multiples of 4 (such as 4, 8, or 12) of memory chips 200. Furthermore, four memory chips 200 may have the same stack ID and can be tested and operated together. For example, when the first semiconductor device 1200 includes eight memory chips 200, the first to fourth memory chips 200-1 to 200-4 may have a first stack ID, and the fifth to eighth memory chips 200-5 to 200-8 may have a second stack ID. However, the first semiconductor device 1200 is not limited to multiples of 4 of memory chips 200 and the stack IDs described above. For example, the first semiconductor device 1200 may include a multiple of 2 memory chips 200 and corresponding stack IDs (e.g., each pair of memory chips 200 has the same stack ID), or may include a multiple of 8 memory chips 200 and corresponding stack IDs (e.g., each group of eight memory chips 200 has the same stack ID).

[0070] The first to eighth memory chips 200-1 to 200-8 may have the same or substantially the same horizontal dimensions (e.g., the same dimensions in a plan view) and internal structure. However, the eighth memory chip 200-8, arranged on top, may not include a through electrode. Furthermore, as... Figure 4AAs shown, the eighth memory chip 200-8 may be thicker than the other memory chips 200. In some embodiments, the overall height of the first semiconductor device 1200 can be controlled by adjusting the thickness of the eighth memory chip 200-8. Hereinafter, for convenience, the specific structure of the memory chip 200 will be described with reference to the first memory chip 200-1.

[0071] The first memory chip 200-1 may include a chip body 201, an active layer 210, a through electrode 220, a bonding pad 230, and a protective layer 240. The chip body 201 may be the same as the chip body 101 of the substrate chip 100 (e.g., except for the size and thickness of the chip body 201).

[0072] Active layer 210 may include multiple memory devices. For example, active layer 210 may include volatile memory devices (such as DRAM or SRAM) or non-volatile memory devices (such as PRAM, MRAM, FeRAM, or RRAM). For example, in the first semiconductor device 1200, the first memory chip 200-1 may include DRAM in active layer 210. Accordingly, the first memory chip 200-1 may be a DRAM chip. Furthermore, because the first semiconductor device 1200 is an HMB package, the first memory chip 200-1 may be a DRAM chip for HMB.

[0073] The through electrode 220 can penetrate the chip body 201, or it can penetrate the chip body 201 and extend into the interior of the active layer 210. For example, in the case where the first memory chip 200-1 is divided into cell regions and pad regions and the through electrode 220 is formed only in the pad regions, the through electrode 220 can penetrate the chip body 201 and extend into the interior of the active layer 210. Other details regarding the through electrode 220 may be the same as those regarding the through electrode 120 of the substrate chip 100, unless the context otherwise requires.

[0074] The connection pads 230 may include a lower connection pad 230d disposed on the lower surface of the active layer 210 and an upper connection pad 230u disposed on the upper surface of the chip body 201. In general semiconductor chips, chip pads may be disposed on the lower surface of the active layer. Accordingly, the lower connection pad 230d may correspond to the chip pads of the first memory chip 200-1.

[0075] The lower connection pad 230d can be electrically connected to and / or contact the wiring of the wiring layer of the active layer 210 on the lower surface of the active layer 210. Furthermore, the lower connection pad 230d can be electrically connected to the through electrode 220 via the wiring of the wiring layer. The upper connection pad 230u can be electrically connected to and / or contact the through electrode 220 on the upper surface of the chip body 201. The materials of the lower connection pad 230d and the upper connection pad 230u can be the same as the materials described for the connection pad 130 for the substrate chip 100.

[0076] The protective layer 240 may include a lower protective layer 240d disposed on the lower surface of the active layer 210 and an upper protective layer 240u disposed on the upper surface of the chip body 201. Each protective layer 240 may include, for example, an oxide layer, a nitride layer, a carbide layer, a polymer, or any combination thereof. The upper protective layer 240u may be the same as the protective layer 140 of the substrate chip 100 described above, unless the context otherwise requires.

[0077] The upper connection pad 230u can be arranged in a structure that penetrates at least a portion of the upper protective layer 240u (e.g., in the vertical direction). For example, the upper connection pad 230u can have a structure that completely penetrates the upper protective layer 240u or penetrates a portion of the upper side / upper part of the upper protective layer 240u (e.g., in the vertical direction), and can be arranged in a structure embedded in the upper protective layer 240u. The upper connection pad 230u can be electrically connected to and / or contact the through electrode 220.

[0078] The lower connection pad 230d can be arranged in a structure that penetrates at least a portion of the lower protective layer 240d (e.g., in the vertical direction). For example, a thick pad metal layer can be disposed inside the lower protective layer 240d, and the lower connection pad 230d can penetrate a portion of the lower protective layer 240d and be electrically connected to and / or contact the pad metal layer. On the other hand, the pad metal layer can be electrically connected to and / or contact the wiring of the wiring layer of the active layer 210. The pad metal layer can, for example, include aluminum (Al). Accordingly, the lower connection pad 230d can be electrically connected to the wiring of the wiring layer through the pad metal layer, and can also be electrically connected to the through electrode 220 through the wiring of the wiring layer.

[0079] In the first semiconductor device 1200 of this embodiment, memory chips 200 can be stacked on or below the substrate chip 100 via inter-chip interconnect terminals 260. For example, each inter-chip interconnect terminal 260 can be arranged between the connection pad 130 of the substrate chip 100 and the lower connection pad 230d of the first memory chip 200-1. Furthermore, in two adjacent memory chips 200, the inter-chip interconnect terminals 260 can be arranged between the upper connection pad 230u of the lower memory chip 200 and the lower connection pad 230d of the upper memory chip 200. The inter-chip interconnect terminals 260 can be the same as those described above for the first external connection terminal 1150 of the interposer layer 1100. For example, the inter-chip interconnect terminals 260 can include solder, or can include pillars and solder.

[0080] In the first semiconductor device 1200 of this embodiment, when memory chips 200 are stacked via inter-chip interconnect terminals 260, an adhesive layer 510 can be disposed between the substrate chip 100 and the first memory chip 200-1, and between two adjacent memory chips 200. For example, the adhesive layer 510 can fill the gap between the substrate chip 100 and the first memory chip 200-1, and the gap between two adjacent memory chips 200, and cover the side surface of the inter-chip interconnect terminals 260. Furthermore, the adhesive layer 510 can protrude from the side surface of the memory chip 200 (e.g., in the horizontal direction) and cover the side surface of the memory chip 200, such as... Figure 4A As shown in the diagram. On the other hand, in some embodiments, the adhesive layer 510 may protrude from the side surface of the memory chip 200 (e.g., in the horizontal direction) and only cover a portion of the side surface of each memory chip 200. In this case, the adhesive layer 510 located on the upper / upper surface of each memory chip 200 and the adhesive layer 510 located on the lower / lower surface may not be attached to each other and may be separable from each other (e.g., on the side surface of each memory chip 200). For example, in some embodiments, the internal sealant 400 may contact the side surface of the memory chip 200. The adhesive layer 510 may, for example, comprise NCF. However, the material of the adhesive layer is not limited to NCF.

[0081] The first connection terminal 300 may be disposed on the lower surface of the substrate chip 100. The first connection terminal 300 may be electrically connected to and / or contact the wiring of the wiring layer of the active layer 110. In addition, the first connection terminal 300 may be electrically connected to the through electrode 120 through the wiring of the wiring layer. On the other hand, although not shown, chip pads may be disposed on the lower surface of the substrate chip 100, and the first connection terminal 300 may be disposed on and / or contact the chip pads.

[0082] The first connection terminal 300 may have the same or similar structure as the inter-chip connection terminal 260. For example, the first connection terminal 300 may include solder. In some embodiments, the first connection terminal 300 may include pillars and solder. The pillars and solder of the first connection terminal 300 may be compatible with those for... Figure 1 The first external connection terminal 1150 of the interposer layer 1100 in the semiconductor package 1000 describes the same pillar and solder.

[0083] An internal sealant 400 may surround the side surface of the memory chip 200 located on the substrate chip 100. For example... Figure 4A As shown, the internal sealant 400 may not cover the upper surface of the uppermost memory chip (e.g., the eighth memory chip 200-8). Accordingly, the upper surface of the eighth memory chip 200-8 may be exposed from the internal sealant 400. However, in some embodiments, the internal sealant 400 may cover the upper surface of the uppermost memory chip (e.g., the eighth memory chip 200-8). The internal sealant 400 may, for example, include EMC. However, the material of the internal sealant 400 is not limited to EMC.

[0084] refer to Figure 4B In the semiconductor package 1000 of this embodiment, the first semiconductor device 1200a may have an HBM package structure, but... Figure 4A The difference between the first semiconductor device 1200a and the first semiconductor device 1200a may be that the first semiconductor device 1200a also includes a top dummy chip 500. For example, the first semiconductor device 1200a may include a substrate chip 100, a memory chip 200, a first connection terminal 300, an internal sealant 400, and a top dummy chip 500. The substrate chip 100, the memory chip 200, the first connection terminal 300, and the internal sealant 400 may be compatible with... Figure 4A The first semiconductor device 1200 describes the same substrate chip 100, memory chip 200, first connection terminal 300, and internal sealant 400. However, when a top dummy chip 500 is added, the internal sealant 400 may have a structure that covers the side surfaces up to the top dummy chip 500.

[0085] In the first semiconductor device 1200a, a top dummy chip 500 can be stacked on the memory chip 200 via an adhesive layer 520. The top dummy chip 500 can be added to meet the height specifications of the first semiconductor device 1200a. For example, in the case of an HBM package, the height, area, etc., can be determined by the Joint Electronic Devices Committee (JEDEC) standards. When the first semiconductor device 1200a is an HBM package, the height of the first semiconductor device 1200a can meet JEDEC standards by arranging a top dummy chip 500 with an appropriate height on the memory chip 200.

[0086] On the other hand, when the top dummy chip 500 is added to the first semiconductor device 1200a, the eighth memory chip 200-8 may have the same or similar thickness as each of the other memory chips 200. However, the inventive concept is not limited thereto. In some embodiments, even with the top dummy chip 500 included, the thickness of the eighth memory chip 200-8 may be greater than the thickness of each of the other memory chips 200. However, when the total height of the first semiconductor device 1200a is controlled by adjusting the thickness of the eighth memory chip 200-8, the top dummy chip 500 may be omitted.

[0087] refer to Figure 4C In the semiconductor package 1000 of this embodiment, the first semiconductor device 1200b may have an HBM package structure, but... Figure 4A The first semiconductor device 1200 differs in that the memory chip 200a is stacked via a hybrid copper bonding (HCB) connection. For example, the first semiconductor device 1200b may include a substrate chip 100, the memory chip 200a, a first connection terminal 300, and an internal sealant 400. The substrate chip 100, the first connection terminal 300, and the internal sealant 400 can be configured with... Figure 4A The first semiconductor device 1200 describes the same substrate chip 100, first connection terminal 300, and internal sealant 400. However, since the memory chips 200a are stacked via HCB without inter-chip connection terminals 260, there is no need for an adhesive layer to fill the gaps between the memory chips 200a and the substrate chip 100, as well as between adjacent memory chips 200a.

[0088] In the first semiconductor device 1200b, the memory chip 200a can be stacked on the substrate chip 100 or on the memory chip 200a directly below it via HCB. HCB can be a combination of pad-to-pad bonding and insulator-to-insulator bonding. On the other hand, since the pads are typically formed of Cu, the pad-to-pad bonding can be Cu-to-Cu bonding.

[0089] More specifically, as described above, connection pads 130 and a protective layer 140 can be arranged on the upper surface of the substrate chip 100. Furthermore, connection pads 230 and a protective layer 240 can be arranged on each of the lower and upper surfaces of each memory chip 200a. On the other hand, the connection pads 130 of the substrate chip 100 can be arranged in a buried structure within the protective layer 140, and the upper surface of the connection pads 130 can be exposed from the protective layer 140. Similarly, the connection pads 230 of the memory chip 200a can be arranged in a buried structure within the protective layer 240, and either the upper or lower surface of the connection pads 230 can be exposed from the protective layer 240. Each protective layer 140 and 240 can, for example, include an insulating layer, such as SiO2 or SiN.

[0090] The connection pads 130 of the substrate chip 100 can be electrically coupled to and contact the lower connection pads 230d of the first memory chip 200a-1, and the protective layer 140 of the substrate chip 100 can be coupled to the lower protective layer 240d of the first memory chip 200a-1, so that an HCB can be formed between the substrate chip 100 and the first memory chip 200a-1. Furthermore, an HCB can be formed between two adjacent memory chips 200a by coupling the upper connection pads 230u and the upper protective layer 240u on the upper surface of the lower memory chip 200a to the lower connection pads 230d and the lower protective layer 240d on the lower surface of the upper memory chip 200a.

[0091] Figures 5A to 5D This is a cross-sectional view of a semiconductor package according to an embodiment. Figure 1 Let's refer to each other. Figures 5A to 5D The following description is given, and the above text is in... Figures 1 to 4C The information provided in the description may be briefly described or omitted.

[0092] refer to Figure 5A In this embodiment, the semiconductor package 1000a can be integrated with the structure of the intermediate heat sink 1400a. Figure 1 The semiconductor package 1000 is different. For example, the semiconductor package 1000a of this embodiment may include an interposer 1100, a first semiconductor device 1200, a second semiconductor device 1300, an intermediate heat sink 1400a, and a sealant 1500. The interposer 1100, the first semiconductor device 1200, the second semiconductor device 1300, and the sealant 1500 may be adapted to... Figure 1 The semiconductor package 1000 describes the same interposer 1100, first semiconductor device 1200, second semiconductor device 1300, and sealant 1500.

[0093] In the semiconductor package 1000a of this embodiment, the intermediate heat sink 1400a may have a single-layer structure. For example, the intermediate heat sink 1400a may have a structure similar to... Figure 1 The intermediate metal layer 1440 of the intermediate heat sink 1400 in the semiconductor package 1000 has the same or substantially the same structure as the intermediate metal layer 1440 of the intermediate heat sink 1400a. Accordingly, the intermediate heat sink 1400a may include a substrate 1400B and a protrusion 1400P located on a peripheral portion of the upper surface of the substrate 1400B. The substrate 1400B and the protrusion 1400P may be the same as the substrate 1400B and the protrusion 1400P described for the intermediate metal layer 1440 of the intermediate heat sink 1400. However, the substrate 1400B may be thicker than the substrate 1440B of the intermediate metal layer 1440.

[0094] On the other hand, since the intermediate heat sink 1400a does not include a lower metal layer and an upper metal layer, the protrusions 1400P of the intermediate heat sink 1400a can form their own dams (DAM). The protrusions 1400P can be in various shapes, such as... Figures 2A to 2C As shown in the figure. In addition, the shape of the retaining dam DAM can also be determined based on the shape of the protrusion 1400P.

[0095] refer to Figure 5B In this embodiment, the semiconductor package 1000b can be integrated with the structure of the intermediate heat sink 1400b. Figure 1 The semiconductor package 1000b differs from the semiconductor package 1000b in this embodiment. For example, the semiconductor package 1000b in this embodiment may include an interposer 1100, a first semiconductor device 1200, a second semiconductor device 1300, an intermediate heat sink 1400b, and a sealant 1500. The interposer 1100, the first semiconductor device 1200, the second semiconductor device 1300, and the sealant 1500 may be adapted to... Figure 1 The semiconductor package 1000 describes the same interposer 1100, first semiconductor device 1200, second semiconductor device 1300, and sealant 1500.

[0096] In the semiconductor package 1000b of this embodiment, the intermediate heat sink 1400b may include a lower metal layer 1420, an intermediate metal layer 1440a, and an upper metal layer 1460. The lower metal layer 1420 may be connected to... Figure 1 The intermediate metal layer 1440a is the same as the lower metal layer 1420 of the intermediate heat sink 1400 in the semiconductor package 1000. The intermediate metal layer 1440a may have a structure consisting only of protrusions. For example, the intermediate metal layer 1440a may correspond to or may be in Figure 1 The intermediate metal layer 1440 of the intermediate heat sink 1400 in the semiconductor package 1000 does not contain the structure of the substrate 1440B. The upper metal layer 1460 can be connected to... Figure 1The upper metal layer 1460 of the intermediate heat sink 1400 in the semiconductor package 1000 is the same. However, because the intermediate metal layer 1440a has a structure that includes only protrusions, the upper metal layer 1460 can cover the upper surfaces of the intermediate metal layer 1440a and the lower metal layer 1420 with a uniform thickness. On the other hand, the dam DAM can include the intermediate metal layer 1440a and the protruding portion of the upper metal layer 1460 covering the intermediate metal layer 1440a. Furthermore, the intermediate metal layer 1440a can be in various shapes, such as Figures 2A to 2C As shown, the shape of the dam DAM can also be determined based on the shape of the intermediate metal layer 1440a.

[0097] refer to Figure 5C In this embodiment, the semiconductor package 1000c can be integrated with the structure of the intermediate heat sink 1400c. Figure 1 The semiconductor package 1000c differs from the semiconductor package 1000c in this embodiment. For example, the semiconductor package 1000c in this embodiment may include an interposer 1100, a first semiconductor device 1200, a second semiconductor device 1300, an intermediate heat sink 1400c, and a sealant 1500. The interposer 1100, the first semiconductor device 1200, the second semiconductor device 1300, and the sealant 1500 may be adapted to... Figure 1 The semiconductor package 1000 describes the same interposer 1100, first semiconductor device 1200, second semiconductor device 1300, and sealant 1500.

[0098] In the semiconductor package 1000c of this embodiment, the intermediate heat sink 1400c may include a lower metal layer 1420a, an intermediate metal layer 1440a, and an upper metal layer 1460. The intermediate metal layer 1440a and the upper metal layer 1460 may be respectively coupled to… Figure 5B The intermediate metal layer 1440a and the upper metal layer 1460 of the intermediate heat sink 1400b in the semiconductor package 1000b are the same.

[0099] The lower metal layer 1420a can have a multilayer structure. For example, the lower metal layer 1420a in the semiconductor package 1000c of this embodiment can have a three-layer structure. However, the number of layers in the lower metal layer 1420a is not limited to three. For example, the lower metal layer 1420a can have a structure with two, four, or more layers. Each of the three layers of the lower metal layer 1420a can be in the shape of a flat plate. Furthermore, each of the three layers of the lower metal layer 1420a can include one of the metal materials described above. On the other hand, because the three layers of the lower metal layer 1420a include different metal materials, or even if they include the same material but are formed under different process conditions, the three layers of the lower metal layer 1420a can be distinguished from each other.

[0100] refer to Figure 5DIn this embodiment, the semiconductor package 1000d can be structurally integrated with the sealant 1500a. Figure 1 The semiconductor package 1000d differs from the semiconductor package 1000d in this embodiment. Specifically, the semiconductor package 1000d in this embodiment may include an interposer 1100, a first semiconductor device 1200, a second semiconductor device 1300, an intermediate heat sink 1400, and a sealant 1500a. The interposer 1100, the first semiconductor device 1200, the second semiconductor device 1300, and the intermediate heat sink 1400 may be adapted to... Figure 1 The semiconductor package 1000 describes the same interposer 1100, first semiconductor device 1200, second semiconductor device 1300, and intermediate heat sink 1400.

[0101] In the semiconductor package 1000d of this embodiment, the sealant 1500a may also be disposed between the first semiconductor device 1200 and the second semiconductor device 1300. Specifically, the first semiconductor device 1200 and the second semiconductor device 1300 may be disposed on the interposer 1100 at a certain interval. Correspondingly, the underfill 1520a may not completely fill the gap between the first semiconductor device 1200 and the second semiconductor device 1300, and may only cover / contact at least a portion of the side surfaces of the first semiconductor device 1200 and the second semiconductor device 1300. As a result, there may be a space between the first semiconductor device 1200 and the second semiconductor device 1300 that is not filled by the underfill 1520a, and this space may be filled by the sealant 1500a. For example, a sealant 1500a may be formed between the first semiconductor device 1200 and the second semiconductor device 1300, such that the sealant 1500a disposed between the first semiconductor device 1200 and the second semiconductor device 1300 overlaps with the first semiconductor device 1200 and the second semiconductor device 1300 in the horizontal direction.

[0102] In addition, Figure 1 and Figures 5A to 5D In the semiconductor packages 1000 and 1000a to 1000d, underfills 1520 and 1520a are shown to completely cover the side surfaces of the first semiconductor device 1200 and the second semiconductor device 1300; however, the structure of the underfills 1520 and 1520a is not limited thereto. For example, the underfills 1520 and 1520a may only cover / contact the lower portion of the side surfaces of the first semiconductor device 1200 and the second semiconductor device 1300.

[0103] Figure 6A and Figure 6B This is a cross-sectional view of the system package according to an embodiment. Figure 1 Let's refer to each other. Figure 6A and Figure 6BThe following description is given, and the above text is in... Figures 1 to 5D The information provided in the description may be briefly described or omitted.

[0104] refer to Figure 6A The system package 2000 in this embodiment may include a semiconductor package 1000, a package substrate 1600, and a heat dissipation structure 1700. The semiconductor package 1000 may be, for example, a... Figure 1 The semiconductor package 1000 may include an interposer 1100, a first semiconductor device 1200, a second semiconductor device 1300, an intermediate heat sink 1400, and a sealant 1500. However, the semiconductor package 1000 in the system package 2000 of this embodiment is not limited to... Figure 1 Semiconductor package 1000. For example, replacing Figure 1 The semiconductor package 1000 can... Figures 5A to 5D Semiconductor packages 1000a to 1000d are used in system package 2000. Furthermore, the first semiconductor device 1200 is not limited to... Figure 4A The first semiconductor device 1200 has an HBM package structure and can have Figure 4B and Figure 4C The first semiconductor devices 1200a and 1200b have HBM package structures. Furthermore, the first semiconductor device 1200 may have a general-purpose package structure other than an HBM package, or it may have a single memory chip structure.

[0105] In the system package 2000 of this embodiment, the package substrate 1600 can be used as or can be a support substrate, and the semiconductor package 1000 and the heat dissipation structure 1700 can be stacked on the package substrate 1600. The semiconductor package 1000 can be mounted on the package substrate 1600 through a first external connection terminal 1150 and a bottom filler 1160. The package substrate 1600 may include a substrate body 1601 and a substrate protective layer 1620. The substrate body 1601 may include one or more wiring layers. When the wiring is formed in multiple layers, the conductive patterns of different wiring layers can be electrically connected to each other through vertical paths. Depending on the material of the substrate body 1601, the package substrate 1600 may include or may be, for example, a ceramic substrate, a printed circuit board (PCB), an organic substrate, an interposer substrate, etc.

[0106] The package substrate 1600 may include two substrate protective layers 1620, including an upper substrate protective layer 1620u located on the upper surface of the substrate body 1601 and a lower substrate protective layer 1620d located on the lower surface of the substrate body 1601. The substrate protective layers 1620 may include, for example, solder resist (SR). However, the material of the substrate protective layers 1620 is not limited to SR. On the other hand, a second external connection terminal 1650 may be disposed on the lower surface of the package substrate 1600. The system package 2000 can be stacked on an external system board or motherboard via the second external connection terminal 1650.

[0107] The heat dissipation structure 1700 may include a top plate 1710 and a side plate 1730. The top plate 1710 may have a flat plate shape. The side plate 1730 may extend vertically downward from the outer end of the top plate 1710. The lower end of the side plate 1730 may contact the upper surface of the packaging substrate 1600. The top plate 1710 and the side plate 1730 may be integrally connected as a single unit. The heat dissipation structure 1700 may include a metallic material with high thermal conductivity and relatively lightweight. For example, the heat dissipation structure 1700 may include an aluminum alloy. However, the material of the heat dissipation structure 1700 is not limited to aluminum alloy. The heat dissipation structure 1700 may, for example, be a heat sink.

[0108] The heat dissipation structure 1700 can be bonded to the semiconductor package 1000 via the TIM 1800. Specifically, the top plate 1710 of the heat dissipation structure 1700 can be bonded to the intermediate heat sink 1400 via the TIM 1800. The TIM 1800 may include a gel-type material with high thermal conductivity, such as a material with low thermal resistance, such as grease, tape, elastomeric pad, or phase change material. The TIM 1800 may be, for example, gel-type. However, the TIM 1800 is not limited to gel-type. On the other hand, as described above, the TIM 1800 can be surrounded by the dam DAM of the intermediate heat sink 1400. Accordingly, during TC reliability testing, the TIM 1800 can be prevented from being pumped out to the outside, and the TIM 1800 can be maintained on the intermediate heat sink 1400, thus improving the heat dissipation efficiency through the TIM 1800. Furthermore, because the adhesive strength between the heat dissipation structure 1700 and the intermediate heat sink 1400 is strongly maintained by the TIM 1800, warpage of the semiconductor package 1000 can be reduced. As a result, defects such as poor wetting / short circuits in the first external connection terminal 1150 of the semiconductor package 1000 can be minimized.

[0109] The system package 2000 of this embodiment can be a 2.5D package structure. A 2.5D package structure is a concept relative to a 3D package structure, in which all semiconductor chips are stacked together and there is no interposer. Each of the 2.5D and 3D package structures can be included in or can be a system-in-package (SIP) structure. Furthermore, the system package 2000 of this embodiment can be a semiconductor package (e.g., in a broad sense), but as described in this disclosure, the system package can be distinguished from the semiconductor package 1000, which is a component of the system package 2000. Similarly, other system packages described below can also be semiconductor packages (e.g., in a broad sense).

[0110] refer to Figure 6B In this embodiment, the system package 2000a can be integrated with the structure of the heat dissipation structure 1700a. Figure 6A The system package 2000 is different from the system package 2000 in this embodiment. Specifically, the system package 2000a in this embodiment may include a semiconductor package 1000, a package substrate 1600, and a heat dissipation structure 1700a. The semiconductor package 1000 and the package substrate 1600 can be designed for use with... Figure 6A The system package 2000 describes the same semiconductor package 1000 and package substrate 1600.

[0111] In the system package 2000a of this embodiment, the heat dissipation structure 1700a may include a heat sink 1720 and a stiffener 1740. The heat sink 1720 may be in the form of a thick flat plate. For example, the thickness of the heat sink 1720 may be 15% to 25% of the smaller of its width and length. The heat sink 1720 may include components with high thermal conductivity (e.g., greater than 170 or greater than 200 W / m Kelvin). 1 ·K 1 And it can be made of relatively lightweight metallic materials. For example, heat sink 1720 may include aluminum alloy. However, the material of heat sink 1720 is not limited to aluminum alloy. Heat sink 1720 may be, for example, a radiator.

[0112] A reinforcing layer 1740 may be disposed between the heat sink 1720 and the package substrate 1600, and may support the heat sink 1720. The reinforcing layer 1740 can improve the thermal characteristics of the package substrate 1600, such as its warpage characteristics, by mechanically supporting the package substrate 1600 and the heat sink 1720 between them. The reinforcing layer 1740 may comprise a metal, such as steel or Cu, which has excellent mechanical strength. However, the material of the reinforcing layer 1740 is not limited to this. The materials of the reinforcing layer 1740 and the heat sink 1720 may be different from each other. Therefore, the reinforcing layer 1740 and the heat sink 1720 may not be integrally coupled to each other. However, in some embodiments, the reinforcing layer 1740 and the heat sink 1720 may comprise the same metal.

[0113] Figure 7A and Figure 7B These are perspective and cross-sectional views of the system package according to the embodiment. Figure 7B It can be along Figure 7A The cross-sectional view taken by line I-I'. (And...) Figure 1 and Figure 6A Let's refer to each other. Figure 7A and Figure 7B The following description is given, and the above text is in... Figures 1 to 6B The information provided in the description may be briefly described or omitted. Figure 7A For simplicity, the intermediate heat sink 1400, sealant 1500, heat dissipation structure 1700, and TIM 1800 have been omitted. Figure 7B For convenience, heat dissipation structures 1700 and TIM 1800 have been omitted. Therefore, components not shown in the accompanying drawings and / or not described in the following description should be referenced to the above description and the preceding drawings (e.g., Figures 1 to 6B ).

[0114] refer to Figure 7A and Figure 7B In this embodiment, the system package 2000b and Figure 6A The system package 2000 differs in that the semiconductor package 1000e includes four first semiconductor devices 1200c. Specifically, the system package 2000b of this embodiment may include the semiconductor package 1000e, a package substrate 1600, and a heat dissipation structure 1700. The package substrate 1600 and the heat dissipation structure 1700 can be customized for use with semiconductor packages 1000e, 1600, and 1700. Figure 6A The system package 2000 describes the same packaging substrate 1600 and heat dissipation structure 1700.

[0115] In the system package 2000b of this embodiment, the semiconductor package 1000e may include an interposer 1100, a first semiconductor device 1200c, a second semiconductor device 1300, an intermediate heat sink 1400, and a sealant 1500. The interposer 1100, the second semiconductor device 1300, the intermediate heat sink 1400, and the sealant 1500 can be used with... Figure 1 The semiconductor package 1000 describes the same interposer 1100, second semiconductor device 1300, intermediate heat sink 1400, and sealant 1500.

[0116] In the system package 2000b of this embodiment, the semiconductor package 1000e may include four first semiconductor devices 1200c, such as... Figure 7A As shown in the diagram. For example, four first semiconductor devices 1200c can be arranged on the interposer layer 1100 via first connection terminals 300, two on each side opposite the second semiconductor device 1300. Specifically, the lower left first semiconductor device 1200-1 and the upper left first semiconductor device 1200-3 can be arranged on the left side of the second semiconductor device 1300, and the lower right first semiconductor device 1200-2 and the upper right first semiconductor device 1200-4 can be arranged on the right side of the second semiconductor device 1300. However, in the system package 2000b of this embodiment, the number of first semiconductor devices 1200c is not limited to four. For example, one to three first semiconductor devices 1200c or five or more first semiconductor devices 1200c can be arranged on the interposer layer 1100.

[0117] The first semiconductor device 1200c can be, for example, Figure 4A The first semiconductor device 1200c may include a substrate chip 100, a memory chip 200, a first connection terminal 300, and an internal sealant 400. However, the first semiconductor device 1200c is not limited to... Figure 4A The first semiconductor device 1200. For example, it can be... Figure 4B or Figure 4C The first semiconductor device 1200a or 1200b is applied to the first semiconductor device 1200c of the semiconductor package 1000e of the system package 2000b.

[0118] Figure 8A and Figure 8B This is a cross-sectional view of the system package according to an embodiment. (See above reference) Figures 1 to 7B The described elements may be briefly described or omitted. For reference, Figure 8A and Figure 8B It corresponds to Figure 7BThe cross-sectional view is shown from the perspective of the connection structure between the first semiconductor device 1200 and the second semiconductor device 1300. Only the interposer 1100 (1100a), the first semiconductor device 1200c, the second semiconductor device 1300 and the package substrate 1600 are schematically shown, and the second external connection terminal, sealant, etc. are not shown.

[0119] refer to Figure 8A The system package 2000b in this embodiment can be used with... Figure 7B The system package 2000b is the same as or substantially the same as the system package 2000b in this embodiment. Accordingly, the system package 2000b in this embodiment may include a semiconductor package 1000e, a package substrate 1600, and a heat dissipation structure (not shown). The package substrate 1600 and the heat dissipation structure 1700 are the same as those for the system package 2000b. Figure 6A The system package 2000 describes the same packaging substrate 1600 and heat dissipation structure 1700. The semiconductor package 1000e is similar to... Figure 7A and Figure 7B The system package 2000b is the same as the semiconductor package 1000e.

[0120] In semiconductor package 1000e, a first semiconductor device 1200c can be mounted on an interposer 1100 via a first connection terminal 300, and a second semiconductor device 1300 can be mounted on the interposer 1100 via a second connection terminal 1350. For example... Figure 8A As shown, in the system package 2000b of this embodiment, the first semiconductor device 1200c and the second semiconductor device 1300 can be electrically connected through the first connection wiring In1 of the interposer layer 1100. On the other hand, the first connection wiring In1 may include wiring of the wiring layer 1110 of the interposer layer 1100 and through electrode 1120, or may include wiring of the wiring layer 1110 of the interposer layer 1100 but not through electrode 1120.

[0121] refer to Figure 8B The system package 2000c in this embodiment may include a semiconductor package 1000e, a package substrate 1600, a heat dissipation structure (not shown), and a Si bridge 1900. Figure 8A Compared to the system package 2000b, the system package 2000c of this embodiment may further include a Si bridge 1900. Furthermore, the interposer 1100a may be based on an organic material, plastic, or glass substrate instead of Si. However, the material of the interposer 1100a is not limited to the materials described above. In some embodiments, the interposer 1100a may be, for example, a panel interposer, a PLP interposer, or an RDL interposer (redistribution layer interposer or redistribution interposer).

[0122] Si bridge 1900 can be arranged inside intermediate layer 1100a, such as Figure 8B As shown in the diagram, the Si bridge 1900 can be disposed within the interposer 1100a at a corresponding location between the first semiconductor device 1200c and the second semiconductor device 1300. Furthermore, the Si bridge 1900 can overlap with a portion of the first semiconductor device 1200c and a portion of the second semiconductor device 1300 (e.g., in the vertical direction). In the system package 2000c of this embodiment, the first semiconductor device 1200c can be disposed on both sides of the second semiconductor device 1300 in the x-direction. Accordingly, the Si bridge 1900 can be disposed on both sides of the second semiconductor device 1300 in the x-direction.

[0123] The Si bridge 1900 may include a second connection wiring In2. The Si bridge 1900 can electrically connect the first semiconductor device 1200c and the second semiconductor device 1300 to each other via the second connection wiring In2. As a result, in the system package 2000c of this embodiment, the first semiconductor device 1200c and the second semiconductor device 1300 can be electrically connected to each other using the Si bridge 1900, which is separately arranged inside the interposer layer 1100a.

[0124] Figures 9A to 9I This is a cross-sectional view schematically illustrating a method for manufacturing a system package according to an embodiment. Figure 1 Let's refer to each other. Figures 9A to 9I The following description is given, and the above text is in... Figures 1 to 8B The information provided in the description may be briefly described or omitted.

[0125] refer to Figure 9A The method for manufacturing a package according to this embodiment may include preparing a first package structure PKGS1 comprising a plurality of initial chip packages PKGi. The first package structure PKGS1 may be bonded and fixed to a carrier substrate 3000 via an adhesive layer 3500, such as... Figure 9A As shown in the image.

[0126] The first package structure PKGS1 may include an interposer structure 1100S, a plurality of first semiconductor devices 1200, a plurality of second semiconductor devices 1300, and a sealant structure 1500S. The interposer structure 1100S may include a plurality of interposers corresponding to the initial chip package PKGi. For example, the interposer structure 1100S may have a wafer-level dimension (e.g., wafer size) and include a plurality of interposers.

[0127] The sealant structure 1500S can seal all the first semiconductor devices 1200 and second semiconductor devices 1300 located on the interposer structure 1100S. For example, the sealant structure 1500S can seal the first semiconductor devices 1200 and second semiconductor devices 1300 at the wafer level (e.g., on a wafer-scale substrate). On the other hand, as... Figure 9A As shown, the underfill 1520 can cover / fill the gap between the first semiconductor device 1200 and the interposer structure 1100S, and the gap between the second semiconductor device 1300 and the interposer structure 1100S, and can cover / contact the side surfaces of each of the first semiconductor device 1200 and the second semiconductor device 1300, and the sealant structure 1500S can cover / contact the side surfaces of the underfill 1520. However, in some embodiments, a portion of the side surface of each of the first semiconductor device 1200 and the second semiconductor device 1300 may be exposed from the underfill 1520, and the sealant structure 1500S can cover / contact the side surfaces of the underfill 1520 and the exposed portions of the side surfaces of each of the first semiconductor device 1200 and the second semiconductor device 1300. On the other hand, the sealant structure 1500S may not cover the top surfaces of each of the first semiconductor device 1200 and the second semiconductor device 1300. Furthermore, the upper surface of the sealant structure 1500S and the upper surfaces of each of the first semiconductor device 1200 and the second semiconductor device 1300 may be coplanar or substantially coplanar, for example, formed on the same plane. This may be due to the back-side grinding process of the sealant structure 1500S during the fabrication of the first package structure PKGS1 (see...). Figure 10C (B / G). In Figures 10A to 10C The description provides a more detailed account of the process for manufacturing the first package structure, PKGS1.

[0128] On the other hand, each first semiconductor device 1200 can be with Figure 1 The first semiconductor device 1200 of the semiconductor package 1000 corresponds to (e.g., the same) the second semiconductor device 1300, and each second semiconductor device 1300 may be associated with Figure 1 The second semiconductor device 1300 corresponds to (e.g., is the same as) the semiconductor package 1000. Each first semiconductor device 1200 may have an HBM package structure. Accordingly, each first semiconductor device 1200 may have Figures 4A to 4C One of the HBM package structures of the first semiconductor devices 1200, 1200a and 1200b.

[0129] The first semiconductor device 1200 and the second semiconductor device 1300 can be paired or grouped and mounted on corresponding portions of the interposer structure 1100S. For example, as Figure 9AAs shown, a first semiconductor device 1200 and a second semiconductor device 1300 can be paired and mounted on corresponding portions of the interposer structure 1100S. However, the inventive concept is not limited thereto, and the first semiconductor device 1200 and the second semiconductor device 1300 can be paired / grouped in various combinations. For example, as... Figure 7A As shown, a second semiconductor device 1300 and four first semiconductor devices 1200 can be grouped and mounted on corresponding portions of the interposer structure 1100S. Accordingly, each initial chip package PKGi may include: paired / grouped first semiconductor devices 1200 and second semiconductor devices 1300, corresponding portions of the interposer structure 1100S on which the paired / grouped devices are mounted, and corresponding portions of the sealant structure 1500S sealing the paired / grouped devices.

[0130] refer to Figure 9B After the first package structure PKGS1 is fabricated, a lower metal layer structure 1420S can be formed on the upper surface of the first package structure PKGS1. The lower metal layer structure 1420S may include multiple lower metal layers corresponding to the initial chip package PKGi. For example, the lower metal layer structure 1420S may be formed to completely cover the first package structure PKGS1 at the wafer level (e.g., on the wafer or on a wafer-sized substrate). On the other hand, as Figure 9B As shown, the lower metal layer structure 1420S can have the same characteristics as... Figure 5C The semiconductor package 1000c has a multilayer structure corresponding to the lower metal layer 1420a of the intermediate heat sink 1400c. However, the structure of the lower metal layer structure 1420S is not limited to this. For example, the lower metal layer structure 1420S can have a single-layer structure, such as... Figure 1 The lower metal layer 1420 of the intermediate heat sink 1400 in the semiconductor package 1000. In some embodiments, the lower metal layer structure 1420S may be omitted. In this case, the intermediate metal layer may be formed directly on the upper surface of the first package structure PKGS1.

[0131] The lower metal layer structure 1420S can be formed by various processes, such as PVD, CVD, or electroplating. For example, in the method of manufacturing a system package according to this embodiment, the lower metal layer structure 1420S can be formed by PVD sputtering. However, the process for forming the lower metal layer structure 1420S is not limited to sputtering. On the other hand, each layer of the lower metal layer structure 1420S can include one of the various metallic materials described above.

[0132] refer to Figure 9CAfter forming the lower metal layer structure 1420S, an intermediate metal layer 1440a can be formed on the lower metal layer structure 1420S. The intermediate metal layer 1440a may consist only of protrusions, such as... Figure 5B The intermediate metal layer 1440a in the intermediate heat sink 1400b of the semiconductor package 1000b. For example, the intermediate metal layer 1440a can be formed by a raised pattern. The intermediate metal layer 1440a can be shaped as follows: Figures 2A to 2C The shape shown can be formed on the region corresponding to each initial chip package PKGi. On the other hand, the structure of the intermediate metal layer 1440a is not limited to only including a raised structure. For example, an intermediate metal layer having a structure including a substrate 1440B and a raised structure 1440P can be formed, such as... Figure 1 The semiconductor package 1000 has an intermediate metal layer 1440 structure. The intermediate metal layer having the structure described above can completely cover the upper surface of the lower metal layer structure 1420S.

[0133] The intermediate metal layer 1440a can be formed using various patterning processes. For example, the intermediate metal layer 1440a can be formed by forming a metal material layer of uniform thickness on the lower metal layer structure 1420S and etching the metal material layer using photolithography (e.g., a patterning process for a photosensitive layer) and etching processes. Alternatively, a photoresist (PR) pattern including a trench pattern exposing the lower metal layer structure 1420S can be formed on the lower metal layer structure 1420S using photolithography (e.g., exposure and development processes). The intermediate metal layer 1440a can then be formed by filling the trench pattern using an electroplating process.

[0134] refer to Figure 9D After forming the intermediate metal layer 1440a, an upper metal layer structure 1460S can be formed to cover the lower metal layer structure 1420S and the intermediate metal layer 1440a with a uniform thickness. The upper metal layer structure 1460S may also include multiple upper metal layers corresponding to the initial chip package PKGi. That is, the upper metal layer structure 1460S can be formed in a structure that completely covers the first package structure PKGS1 at the wafer level. The upper metal layer structure 1460S can be formed by various processes, such as PVD, CVD, or electroplating. For example, the upper metal layer structure 1460S can be formed by PVD sputtering. However, the process for forming the upper metal layer structure 1460S is not limited to sputtering. On the other hand, the upper metal layer structure 1460S may include one of the various metal materials described above.

[0135] The intermediate heat sink structure 1400cS can be formed by forming the upper metal layer structure 1460S. Furthermore, the second package structure PKGS2 can be formed by forming the intermediate heat sink structure 1400cS. The second package structure PKGS2 may include multiple semiconductor packages PKG. Each semiconductor package PKG may correspond to... Figure 5C 1000c semiconductor package.

[0136] However, the inventive concept is not limited thereto, and can be further developed in... Figures 9B to 9D Different intermediate heat sink structures are formed during the process. In this case, the second package structure PKGS2 may include semiconductor package PKGs with different structures. For example, each semiconductor package PKG may include... Figure 1 , Figure 5A , Figure 5B and Figure 5D Any one of the semiconductor packages 1000, 1000a, 1000b and 1000d.

[0137] refer to Figure 9E After forming the second package structure PKGS2, the second package structure PKGS2 can be attached to the ring mounting device 4000. For example, as Figure 9E As shown, the intermediate heat sink structure 1400cS located on the rear side of the second packaging structure PKGS2 can be attached to the annular mounting device 4000. For reference, the annular mounting device 4000 may include a support ring and cut adhesive tape covering the opening of the support ring. Figure 9E For simplicity, only the cutting of the tape is shown in the image, and this also applies to... Figure 9F and Figure 9G .

[0138] refer to Figure 9F After attaching the second packaging structure PKGS2 to the annular mounting device 4000, the carrier substrate 3000 can be removed from the second packaging structure PKGS2. When removing the carrier substrate 3000, the adhesive layer 3500 can also be removed.

[0139] refer to Figure 9G The semiconductor package 1000c can be manufactured by single-unitizing the second packaging structure PKGS2 through a dicing process. The semiconductor package 1000c can be combined with... Figure 5C This corresponds to the semiconductor package 1000c. However, when the intermediate heat sink structure of the second package structure PKGS2 has a different structure, it can be manufactured by monolithically dividing the second package structure PKGS2. Figure 1 , Figure 5A , Figure 5B and Figure 5DAny one of the semiconductor packages 1000, 1000a, 1000b and 1000d.

[0140] refer to Figure 9H After manufacturing the semiconductor package 1000c, the semiconductor package 1000c can be mounted on the packaging substrate 1600 via the first external connection terminal 1150. The packaging substrate 1600 can be used with... Figure 6A The system package is the same as the packaging substrate described in System Package 2000.

[0141] refer to Figure 9I The heat dissipation structure 1700 can be stacked on the semiconductor package 1000c and the package substrate 1600. The system package 2000d can be manufactured by stacking the heat dissipation structure 1700. The heat dissipation structure 1700 can be... Figure 6A The system package 2000 includes a heat dissipation structure 1700. Accordingly, the heat dissipation structure 1700 may include a top plate 1710 and a side plate 1730. However, the inventive concept is not limited thereto, and may include... Figure 6B The heat dissipation structure 1700a of the system package 2000a is applied to the system package 2000d.

[0142] The heat dissipation structure 1700 can be bonded to the semiconductor package 1000c via a TIM 1800. For example, the TIM 1800 can be arranged between the top plate 1710 and the intermediate heat sink 1400c of the heat dissipation structure 1700, allowing the heat dissipation structure 1700 to be bonded to the semiconductor package 1000c. Furthermore, the TIM 1800 can be held in place by a dam DAM located on the upper surface of the intermediate heat sink 1400c, thus preventing the TIM 1800 from being pumped out during TC reliability testing. Accordingly, the heat dissipation capacity and adhesive strength of the TIM 1800 can be increased. Moreover, due to the increased adhesive strength of the TIM 1800, warpage of the semiconductor package 1000c can be improved, and defects such as poor wetting / short circuits in the first external connection terminal 1150 of the semiconductor package 1000c can be mitigated.

[0143] Figures 10A to 10C It shows the manufacturing process in more detail. Figure 9A A cross-sectional view of the process of the first packaging structure. (Compared to...) Figure 1 Let's refer to each other. Figures 10A to 10C The following description is given, and the above text is in... Figures 1 to 9G The information provided in the description may be briefly described or omitted.

[0144] refer to Figure 10AThe process of manufacturing the first package structure may include mounting a first semiconductor device 1200 and a second semiconductor device 1300 onto an interposer structure 1100S. The first semiconductor device 1200 and the second semiconductor device 1300 may be mounted onto the interposer structure 1100S via connection terminals 300 and 1350 and underfill 1520. As shown, the first semiconductor device 1200 and the second semiconductor device 1300 may be paired / grouped and mounted onto the interposer structure 1100S. Accordingly, the paired / grouped first semiconductor devices 1200 and 1300 may be arranged with a narrow gap, and the pairing / grouping may be arranged with a wide gap from other pairs / groups. The underfill 1520 may surround and contact the side surfaces of the first semiconductor device 1200 and the second semiconductor device 1300. For example, a plurality of first semiconductor devices 1200 and a plurality of second semiconductor devices 1300 can be arranged on an interposer structure 1100S to form a plurality of semiconductor device groups, such that the distance between adjacent semiconductor devices 1200 / 1300 in each group is closer than the distance between semiconductor devices 1200 / 1300 in different groups, and each of the plurality of groups may include at least one first semiconductor device from the plurality of first semiconductor devices 1200 and at least one second semiconductor device from the plurality of second semiconductor devices 1300.

[0145] On the other hand, although Figure 10A Although not shown, the interposer structure 1100S can be fixed to the carrier substrate by an adhesive layer. In some embodiments, the thickness of the interposer structure can be greater than the length of the through electrode, and the first external connection terminal may not be disposed on the lower surface of the interposer structure. In this case, the first external connection terminal can be disposed on the through electrode after a thinning process of the interposer structure.

[0146] refer to Figure 10BAfter the first semiconductor device 1200 and the second semiconductor device 1300 are installed, the first semiconductor device 1200 and the second semiconductor device 1300 located on the interposer structure 1100S can be sealed with an initial sealant structure 1500Si. The initial sealant structure 1500Si can cover / contact the side surfaces of the underfill 1520 and the upper surfaces of the first semiconductor device 1200 and the second semiconductor device 1300. In some embodiments, the underfill 1520 can only cover / contact a portion of the side surfaces of each of the first semiconductor device 1200 and the second semiconductor device 1300, and can expose other portions of the side surfaces of each of the first semiconductor device 1200 and the second semiconductor device 1300. In this case, the initial sealant structure 1500Si can cover / contact the exposed side surfaces of each of the first semiconductor device 1200 and the second semiconductor device 1300. When the initial sealant structure 1500Si covers the upper surfaces of the first semiconductor device 1200 and the second semiconductor device 1300, the thickness of the initial sealant structure 1500Si can be greater than Figure 9A The sealant structure has a thickness of 1500S.

[0147] refer to Figure 10C A back-side polishing process (B / G) can be performed to remove the upper portion of the initial sealant structure 1500Si. The upper surfaces of the first semiconductor device 1200 and the second semiconductor device 1300 can be exposed from the sealant structure 1500S via the back-side polishing process (B / G). Furthermore, the upper surfaces of the first semiconductor device 1200 and the second semiconductor device 1300 and the upper surface of the sealant structure 1500S can be coplanar and can be formed on substantially the same plane. After performing the back-side polishing process (B / G) on the initial sealant structure 1500Si, a [fabrication / manufacturing process] can be manufactured. Figure 9A The first packaging structure is PKGS1.

[0148] Although the different figures illustrate variations of exemplary embodiments and different embodiments disclose features that differ from one another, these figures and embodiments are not intended to be mutually exclusive. Rather, features depicted in different figures and / or described in the different embodiments above may be combined with other features in other figures / embodiments to produce additional variations of the embodiments when the related descriptions of the figures and embodiments are considered as a whole. For example, unless the context clearly indicates otherwise, components and / or features of the different embodiments described above may be combined interchangeably or additionally with components and / or features of other embodiments to form additional embodiments, and this disclosure includes additional embodiments.

[0149] Although the inventive concept has been specifically shown and described with reference to various embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, the semiconductor package comprising: Intermediate layer; A first semiconductor device, wherein the first semiconductor device is disposed on the interposer layer; A second semiconductor device, which is located on the interposer layer and spaced apart from the first semiconductor device; as well as A heat sink is disposed on the upper surfaces of the first semiconductor device and the second semiconductor device, and has a dam disposed in the edge portion of the heat sink.

2. The semiconductor package according to claim 1, wherein, The heat sink is in the shape of a rectangular flat plate, and The dam is in the shape of a rectangular ring and is arranged in the edge portion of the upper surface of the heat sink.

3. The semiconductor package according to claim 1, wherein, The heat sink is rectangular in shape in the plan view, and The dam is formed into multiple L-shaped sections, and each L-shaped section is arranged to be adjacent to a corresponding vertex among the four vertices of the rectangular upper surface of the heat sink.

4. The semiconductor package according to claim 1, wherein, The heat sink is rectangular in shape, and The dam has multiple linear shaped portions, and each of the linear shaped portions extends along one of the four sides of the rectangular upper surface of the heat sink.

5. The semiconductor package according to claim 1, wherein, The heat sink includes: A lower metal layer, the lower metal layer being in the shape of a flat plate and comprising at least one layer; An intermediate metal layer disposed on the lower metal layer and including protrusions forming the dam; and An upper metal layer, which covers the upper surface of the intermediate metal layer with a uniform thickness.

6. The semiconductor package according to claim 1, wherein, The first semiconductor device includes a high-bandwidth memory package, and The second semiconductor device includes a logic chip.

7. The semiconductor package according to claim 1, wherein, The intermediate layer is a Si-intermediate layer or a redistributed intermediate layer with Si bridges.

8. A semiconductor package, the semiconductor package comprising: Packaging substrate; A chip package, wherein the chip package is disposed on the packaging substrate; as well as A heat dissipation structure is disposed on the chip package. The chip package includes: Intermediate layer; A first semiconductor device, wherein the first semiconductor device is disposed on the interposer layer; A second semiconductor device is disposed on the interposer layer and spaced apart from the first semiconductor device; An intermediate heat sink is disposed on the upper surfaces of the first semiconductor device and the second semiconductor device, and has dams arranged along the edge portions of the intermediate heat sink; and A sealant is disposed between the intermediary layer and the intermediate heat sink and seals the first semiconductor device and the second semiconductor device.

9. The semiconductor package of claim 8, wherein, The intermediate heat sink is rectangular in shape in the plan view, and The dam is in the shape of a rectangular ring, an L-shape, or a straight line, and is arranged in the edge portion of the upper surface of the intermediate heat dissipation plate.

10. The semiconductor package according to claim 8, wherein, The intermediate heat dissipation plate includes: A lower metal layer, the lower metal layer being in the shape of a flat plate and comprising at least one layer; An intermediate metal layer disposed on the lower metal layer and including protrusions forming the dam; and An upper metal layer, which covers the upper surface of the intermediate metal layer with a uniform thickness.

11. The semiconductor package according to claim 8, wherein, The intermediate layer includes a Si-intermediate layer or a redistributed intermediate layer with Si bridges. The first semiconductor device includes a high-bandwidth memory package, and The second semiconductor device includes a logic chip.

12. The semiconductor package of claim 8, wherein, The heat dissipation structure is bonded to the upper surface of the chip package via a thermal interface material, and The thermal interface material is surrounded by the dam.

13. The semiconductor package of claim 12, wherein, The heat dissipation structure includes one of the following: A first structure includes a top plate bonded to the thermal interface material and a side plate extending vertically downward from the top plate, wherein the side plate contacts the upper surface of the encapsulation substrate; or The second structure includes a heat sink bonded to the thermal interface material and a reinforcing layer supporting the heat sink, wherein the reinforcing layer is in contact with the upper surface of the packaging substrate.

14. A semiconductor package, the semiconductor package comprising: Packaging substrate; A chip package, wherein the chip package is disposed on the packaging substrate; A heat dissipation structure is disposed on the chip package; as well as A thermal interface material is disposed between the chip package and the heat dissipation structure. The chip package includes: Intermediate layer; A first semiconductor device, wherein the first semiconductor device is disposed on the interposer layer; A second semiconductor device, the second semiconductor device being located on the interposer and spaced apart from the first semiconductor device; and An intermediate heat sink is disposed on the upper surfaces of the first semiconductor device and the second semiconductor device, and has a dam surrounding the thermal interface material in the edge portion of the intermediate heat sink.

15. The semiconductor package of claim 14, wherein, The intermediate heat sink is rectangular in shape in the plan view, and The dam is formed as one of a continuous rectangular ring shape, multiple discrete L-shaped portions, or multiple linear shape portions, and is arranged in the edge portion of the upper surface of the intermediate heat sink.

16. The semiconductor package of claim 14, wherein, The intermediate heat dissipation plate includes: A lower metal layer, the lower metal layer being in the shape of a flat plate and comprising at least one layer; An intermediate metal layer disposed on the lower metal layer and including protrusions forming the dam; and An upper metal layer, which covers the upper surface of the intermediate metal layer with a uniform thickness.

17. The semiconductor package of claim 14, wherein, The intermediate layer includes a Si-intermediate layer or a redistributed intermediate layer with Si bridges. The first semiconductor device includes a high-bandwidth memory package, and The second semiconductor device includes a logic chip.

18. A method for manufacturing a semiconductor package, the method comprising: Fabricate a package structure comprising multiple initial chip packages; An intermediate heat sink structure is formed on the upper surface of the encapsulation structure; A chip package is formed by individually separating the packaging structure and the intermediate heat sink structure. as well as The chip package is mounted on the packaging substrate. The chip package includes: Intermediate layer; A first semiconductor device, wherein the first semiconductor device is disposed on the interposer layer; A second semiconductor device, the second semiconductor device being located on the interposer and spaced apart from the first semiconductor device; and An intermediate heat sink, which is part of the intermediate heat sink structure, is disposed on the upper surfaces of the first semiconductor device and the second semiconductor device, and has a dam formed in the edge portion of the intermediate heat sink.

19. The method according to claim 18, wherein, The intermediate heat sink structure includes: A lower metal layer is formed on the upper surface of the packaging structure, the lower metal layer comprising at least one layer in the shape of a flat plate; An intermediate metal layer is formed on the lower metal layer, the intermediate metal layer including protrusions constituting the dam; and An upper metal layer is formed to cover the upper surface of the intermediate metal layer with a uniform thickness.

20. The method according to claim 18, further comprising: The heat dissipation structure is attached to the chip package using a thermal interface material. The thermal interface material is surrounded by the dam.

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