Rapid authentication anti-counterfeiting system, anti-counterfeiting authentication system and electronic cigarette

Abstract

The invention discloses a quick authentication anti-counterfeiting system which comprises a host and a terminal side, the terminal side comprises a quick erasing storage medium, and the quick erasing storage medium is used for receiving and storing random information sent by the host side so as to perform quick authentication anti-counterfeiting. The quick authentication anti-counterfeiting system can realize identity authentication based on the characteristics of the quick erasing storage medium, and is simple to operate and high in efficiency.

Description

Technical Field

[0001] This invention relates to the field of encryption technology, and in particular to a rapid authentication and anti-counterfeiting system, an anti-counterfeiting authentication system, and an electronic cigarette. Background Technology

[0002] In order to control costs and reduce product size, existing anti-counterfeiting authentication systems for consumable products such as e-cigarettes often use basic encryption verification methods, which often require a separate decoding chip or a high-speed comparator, making the overall structure relatively complex. Summary of the Invention

[0003] To address some or all of the problems in existing technologies, and in order to improve anti-counterfeiting authentication efficiency while simplifying product structure, this invention provides a rapid authentication and anti-counterfeiting system, comprising: On the terminal side, it includes a fast-write storage medium; and The host is used to send random information to the terminal after it connects, and read the data received and saved by the terminal after a limited time. Based on the read content, it determines the authenticity of the terminal.

[0004] Furthermore, based on the read content, determining the authenticity of the information on the terminal side includes: The system determines whether the read content contains valid data. If it does not, it assumes that the terminal does not have a fast write / erase storage medium, and thus determines that the terminal is fake.

[0005] Furthermore, based on the read content, determining the authenticity of the information on the terminal side also includes: The valid data in the read content is compared with the sent random information. If they match, the terminal side is considered to be true.

[0006] Based on the rapid authentication and anti-counterfeiting system described above, a second aspect of the present invention provides an anti-counterfeiting authentication system, comprising: On the terminal side, it includes an authentication chip, which includes a storage module and a computing module. The storage module includes a fast-write storage medium and is used to store a key, user ID information, and received random information. The computing module is communicatively connected to the storage module and is configured to generate an authentication code based on the key, user ID information, specified data, and random code, and send it to the host for comparison to achieve identity authentication.

[0007] Furthermore, the anti-counterfeiting authentication system also includes: The host side includes a microcontroller unit and two MOSFETs. The microcontroller unit includes several I / O ports, a ground terminal, and a power supply terminal. The gate of the first MOSFET is connected to the first I / O port of the microcontroller unit, the source is connected to the power supply terminal of the microcontroller unit, and the drain is connected to the third I / O port through a resistor. The gate of the second MOSFET is connected to the second I / O port of the microcontroller unit, the source is connected to the power supply terminal of the microcontroller unit, and the drain is connected to the third I / O port.

[0008] Furthermore, the terminal side is pluggably connected to the host. After the terminal side is inserted into the host, the two pins of the authentication chip are respectively connected to the ground terminal of the microcontroller unit of the host and the third IO port.

[0009] Furthermore, the computing module integrates a 512-bit input SHA-1 algorithm engine for calculating a 160-bit information authentication code, which enables dual authentication for writing and reading with the control unit.

[0010] Based on the anti-counterfeiting authentication system described above, a third aspect of the present invention provides an electronic cigarette that includes the anti-counterfeiting authentication system described above.

[0011] This invention provides a rapid authentication and anti-counterfeiting system that achieves rapid authentication by leveraging the characteristics of the storage medium used on the terminal side. The overall method is simple, easy to operate, and time-efficient. Combined with traditional authentication methods such as encrypted computation, it can quickly achieve multi-factor authentication with high security. Attached Figure Description

[0012] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0013] Figure 1 This diagram illustrates the structure of a rapid authentication and anti-counterfeiting system according to an embodiment of the present invention. Figure 2 This diagram illustrates the structure of an anti-counterfeiting authentication system according to an embodiment of the present invention. Figure 3 The diagram shows a flowchart of an anti-counterfeiting authentication method according to an embodiment of the present invention. Figure 4 A flowchart illustrating an anti-counterfeiting authentication method according to another embodiment of the present invention is shown; Figure 5 This diagram illustrates the pulse waveform sent by the host side when writing data "1" to the terminal side according to an embodiment of the present invention. Figure 6 This diagram illustrates the pulse waveform sent by the host side when writing data "0" to the terminal side according to an embodiment of the present invention. Figure 7 This diagram illustrates a pulse waveform sent by the host terminal when reading data "0" from the terminal side, according to an embodiment of the present invention; and Figure 8 This diagram illustrates the pulse waveform sent during power-on reset on the host control terminal side according to an embodiment of the present invention. Detailed Implementation

[0014] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or with other alternatives and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific quantities, materials, and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0015] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0016] To improve the efficiency of anti-counterfeiting authentication, this invention provides a rapid authentication anti-counterfeiting system, which is based on the characteristics of storage media, is simple to operate, highly efficient, and can be combined with other traditional anti-counterfeiting authentication methods to form multiple anti-counterfeiting measures.

[0017] The technical solution of the present invention will be further described below with reference to the accompanying drawings of the embodiments.

[0018] Figure 1 A schematic diagram of a rapid authentication and anti-counterfeiting system according to an embodiment of the present invention is shown. Figure 1 As shown, a rapid authentication anti-counterfeiting system includes a host 101 and a terminal 102, wherein the terminal 102 includes a fast-write storage medium 121, and rapid authentication anti-counterfeiting can be achieved on the terminal side based on the fast-write storage medium 121. In one embodiment of the present invention, the rapid authentication anti-counterfeiting includes: First, after the terminal connects to the host, the host sends random information to the terminal. In one embodiment of the present invention, since the actual terminal includes a fast-write storage medium, it stores the received random information in the fast-write storage medium. After sending the information, the host immediately sends a read request after a limited time to read the information received and stored in the fast-write storage medium by the terminal. In one embodiment of the present invention, when sending random information, the write instruction includes a specified address; therefore, during reading, the data at the corresponding specified positions can be read sequentially. Finally, the host determines the authenticity of the terminal based on the read content. In one embodiment of the invention, it first determines whether the read content contains valid data. If it does not contain valid data, i.e., an empty packet is received, the terminal is considered to lack a fast-write storage medium, and thus the terminal is deemed fake. If it contains valid data, the valid data is further compared with the sent random information. If they match, the terminal is considered genuine. The threshold is determined based on the physical characteristics of the fast-write storage medium. In one embodiment of the invention, the time limit is no more than 100 microseconds, preferably 1 microsecond.

[0019] The rapid authentication and anti-counterfeiting system described above can be applied to the anti-counterfeiting authentication of e-cigarette cartridges. The e-cigarette cartridge, as the terminal side, includes an authentication module, which includes a fast-write storage medium. The e-cigarette stick, as the host, includes a control module. The control module is used to communicate with the authentication module to achieve anti-counterfeiting authentication and to obtain relevant information about the e-cigarette cartridge.

[0020] As mentioned earlier, traditional encryption algorithms can be further added to the host and terminal sides to achieve multi-factor authentication and improve security. Specifically, an authentication module can be set up on the terminal side. The authentication module includes a storage module and a computing module. The storage module includes at least a fast-write storage medium for storing information such as user ID, key, and received random information. The computing module includes an encryption algorithm that can calculate an authentication code based on the user ID, key, specified data, and random code after fast authentication and anti-counterfeiting are passed, and compare it with the authentication code calculated by the host to achieve dual authentication.

[0021] Figure 2 A schematic diagram of an anti-counterfeiting authentication system according to an embodiment of the present invention is shown. Figure 2As shown, an anti-counterfeiting authentication system includes a host terminal 201 and a terminal terminal 202. The host terminal includes a microcontroller unit 211, a first MOSFET 212, and a second MOSFET 213, while the terminal terminal includes an authentication chip 221. When verification is required, the authentication chip 221 is communicatively connected to the microcontroller unit 211. By controlling the on / off state of the first MOSFET 212 and the second MOSFET 213, the microcontroller unit 211 can read and write to the authentication chip 221, thereby completing the encryption authentication. Furthermore, in this embodiment, the authentication chip 221 includes a fast-write storage medium, such as a ferroelectric memory cell. Therefore, when the terminal terminal 202 connects to the host terminal 201, the aforementioned fast authentication anti-counterfeiting can also be performed, thus achieving dual anti-counterfeiting protection.

[0022] like Figure 2 As shown, the microcontroller unit 211 includes several I / O ports, a ground terminal GND, and a power supply terminal V. BAT The gate of the first MOSFET 212 is connected to the first I / O port of the microcontroller 211, and the source is connected to the power supply terminal V of the microcontroller 211. BAT The drain of the second MOSFET 213 is connected to the third IO port via resistor 214, the gate of the second MOSFET 213 is connected to the second IO port of the microcontroller unit, the source is connected to the power supply terminal of the microcontroller unit 211, and the drain is connected to the third IO port.

[0023] In one embodiment of the present invention, the authentication chip 221 includes a storage module and a computing module. The storage module includes a ferroelectric storage unit for storing information such as keys and user IDs. The computing module is communicatively connected to the storage module and is used to generate an authentication code based on the key, user ID information, and a received random code, and send it to the host terminal. In one embodiment of the present invention, the terminal side 202 is pluggably connected to the host terminal 201. When the terminal side 202 is inserted into the host terminal 201, two pins of the authentication chip 221 are electrically connected to the ground terminal GND and the third I / O port of the microcontroller unit 211, respectively. The microcontroller unit 211 reads data from the authentication chip through the built-in ADC function of the third I / O port. In one embodiment of the present invention, the computing module integrates a 512-bit input SHA-1 algorithm engine, which can be used to calculate a 160-bit Authentication Code (MAC) to achieve dual authentication for writing and reading.

[0024] Meanwhile, since the authentication chip 221 uses a fast-write storage medium such as a ferroelectric storage unit, it can also perform fast authentication and anti-counterfeiting when the terminal 202 is connected to the host 201, so as to achieve the first layer of identity authentication with the microcontroller unit.

[0025] Based on the anti-counterfeiting authentication system described above, Figure 3 This diagram illustrates a flowchart of an anti-counterfeiting authentication method according to an embodiment of the present invention. Figure 3 As shown, an anti-counterfeiting authentication method includes: First, in step 301, rapid authentication is performed. After the terminal connects to the host, the host writes a random code to a specific area of ​​the fast-write storage medium on the terminal through the microcontroller unit. Then, after a specified time, it reads the corresponding address data and quickly verifies it to determine whether the read and write data are consistent, thus achieving the first layer of authentication. If the read and write data are consistent, the authentication is successful; otherwise, it is determined to be a fake terminal. Next, in step 302, the key is obtained. In one embodiment of the present invention, the terminal side pre-stores user ID information and a key. After the first layer of authentication is passed, the host side reads the user ID information of the terminal side and calculates the key of the terminal side based on a preset built-in formula. Next, in step 303, the authentication code is calculated. Before the host needs to perform read / write operations on the terminal, secondary authentication is required. Specifically, firstly, the terminal and the host calculate the authentication code using the same algorithm. The terminal calculates the authentication code based on its stored user ID information, key, specified data, and random code. The host calculates the authentication code based on its calculated key, the read user ID information, specified data, and random code. It should be understood that the information used by the terminal and the host to calculate the authentication code is consistent. In one embodiment of the present invention, the terminal and the host calculate the ciphertext based on the SHA encryption algorithm; in other embodiments of the present invention, other common key calculation methods can also be used, as long as the methods used by the terminal and the host are consistent. Finally, in step 304, identity authentication is performed. The authentication codes calculated by the terminal and the host are compared for a second layer of authentication. If they match, the second layer of verification passes; otherwise, the terminal is considered a fake terminal.

[0026] Figure 4 This diagram illustrates a flowchart of an anti-counterfeiting authentication method according to another embodiment of the present invention. It is related to... Figure 3 The difference between the anti-counterfeiting authentication methods shown lies in the acquisition of the key. Specifically, as... Figure 4 As shown, an anti-counterfeiting authentication method includes: First, in step 401, rapid authentication is performed. After the terminal connects to the host, the host writes a random code to a specific area of ​​the fast erase / write storage medium on the terminal through the microcontroller unit. Then, after a specified time, it reads the corresponding address data and quickly verifies it to determine whether the read and write data are consistent, thus achieving the first layer of authentication. If the read and write data are consistent, the authentication is successful; otherwise, it is determined to be a fake terminal. Next, in step 402, the key is written. In this embodiment, the terminal side pre-stores user ID information, but does not store the key. Instead, after the first authentication is successful, the host side writes the key to the terminal side, that is, the key is pre-stored on the host side. Next, in step 403, the authentication code is calculated. Before the host needs to perform read / write operations on the terminal, secondary authentication is required. Specifically, firstly, both the terminal and the host calculate the authentication code using the same algorithm. The terminal calculates the authentication code based on the key received from its stored user ID information, specified data, and a random code. The host calculates the authentication code based on its stored key, the read user ID information, specified data, and a random code. It should be understood that the information used by the terminal and the host to calculate the authentication code is consistent. In one embodiment of the present invention, the terminal and the host calculate the authentication code based on the SHA encryption algorithm; in other embodiments of the present invention, other common key calculation methods can also be used, as long as the methods used by the terminal and the host are consistent. Finally, in step 404, identity authentication is performed. The authentication codes calculated by the terminal and the host are compared for a second layer of authentication. If they match, the second layer of verification passes; otherwise, the terminal is considered a fake terminal. After the second layer of verification passes, read and write operations can be performed. In one embodiment of the present invention, the host acquires data through the built-in ADC function of the microcontroller unit. The data transmission includes CRC verification, resulting in fast transmission speed and high security.

[0027] As described above, in one embodiment of the present invention, the microcontroller unit 211 is controlled to read and write to the authentication chip 221 by controlling the on / off state of the first MOSFET 212 and the second MOSFET 213. Specifically, when sending an instruction to the authentication chip, the first MOSFET 212 is first turned off, and then the on / off state of the second MOSFET 213 is controlled based on the instruction code to form a set of level signals representing the instruction code, which are sent to the authentication chip through the third I / O port. After receiving the instruction, the authentication chip makes a judgment. If it is a write instruction, the data contained in the write instruction is written to the address specified in the write instruction. If there is a lot of data to be written, it can be written in multiple times, with a maximum of 8 bytes written each time. If a read command is received, the authentication chip starts reading data from the address specified in the read command and provides feedback based on the read data. When receiving feedback data, the second MOSFET 213 needs to be turned off and the first MOSFET 212 turned on, pulling the level low. Then, it waits for feedback from the authentication chip. Based on the feedback from the authentication chip, it confirms the read value. In one embodiment of the present invention, if the read value is 0, the authentication chip will further pull the level low; if it is 1, the level remains unchanged. Finally, the second MOSFET 213 is turned on and the first MOSFET 212 is turned off to complete the reading. If a large amount of data needs to be read, it can be read in stages, such as reading subsequent address data after reading one byte of data. Figure 5 This diagram illustrates the pulse waveform sent by the host side when writing data "1" to the terminal side according to an embodiment of the present invention. Figure 5 As shown, when data 1 (bit 1) needs to be sent to the terminal side, the first MOSFET 212 is first turned off, and then the second MOSFET 213 is turned off, so as to form a time period longer than a preset value t. LOW A low pulse is emitted, then the second MOSFET 213 is turned on to pull up the voltage, thus completing the transmission of data 1. In one embodiment of the present invention, the preset value t LOW The value is 1 microsecond, and the total duration t required to send data 1 is... SLOT The transmission time is approximately 10 microseconds, a significant improvement over the 25 microseconds of existing chip designs. Similarly, Figure 6 This diagram illustrates the pulse waveform sent by the host side when writing data "0" to the terminal side according to an embodiment of the present invention. Figure 6 As shown, when data 0 (bit 0) needs to be sent to the terminal side, the first MOSFET 212 is first turned off, and then the second MOSFET 213 is turned off, so as to form a time period longer than a preset value t. LOW A low pulse is emitted, followed by the activation of the second MOSFET 213, which pulls the voltage high and holds for a period of time. GAPThe duration is such that the second MOSFET 213 is turned off again, forming a duration greater than the preset value t. LOW A low pulse is then continuously sent, followed by two pulses with a duration greater than a preset value t. LOW A low pulse is emitted, followed by the activation of the second MOSFET 213 to pull up the voltage, thus completing the transmission of data 0. The interval between the two low pulses is no greater than the second preset value t. GAP In one embodiment of the present invention, the preset value t LOW The value is 1 microsecond, and the second preset value t GAP The value is 1 microsecond. The total duration t required to send the data 0 is... SLOT The transmission time is approximately 10 microseconds, a significant improvement over the 50 microseconds of existing chip designs. Correspondingly, when data needs to be read from the terminal side, the second MOSFET 213 is first turned off, and the first MOSFET 212 is turned on, pulling the voltage down to the bus voltage V for receiving data 1 on the host side. DC1 After waiting for the first duration t1, ADC sampling begins to receive data fed back from the terminal side. If the data on the terminal side is 0, the terminal side will pull the bus voltage down to the bus voltage value V at which the host side receives data 0. DC0 and continue for a specified duration t READ0 After the feedback signal ends, the voltage returns to V. DC1 After a second duration t2, the first MOSFET 212 is turned off, and the second MOSFET 213 is turned on, causing the voltage to return to the single-bus pull-up voltage value V. PUP ,like Figure 7 As shown. If the data on the terminal side is 1, the terminal side will not pull the voltage low, and thus the bus voltage will always remain at V. DC1 After a specified time, the first MOSFET 212 is turned off, and the second MOSFET 213 is turned on, returning to the single-bus pull-up voltage value V. PUP In one embodiment of the present invention, the first duration t1 is 4 to 6 microseconds, preferably 5.5 microseconds, and the specified duration t READ The first duration is 5 microseconds. The second duration t2 is adjusted according to actual needs, thus controlling when to turn off the first MOSFET 212 and turn on the second MOSFET 213, thereby controlling the overall read duration. In one embodiment of the invention, the second duration t2 can be 5 microseconds or longer. The overall read duration for one bit of data is no more than 30 microseconds, far lower than the 50 microseconds for data read in existing chips. The read / write mechanism is compatible with microcontrollers with a maximum ADC sampling rate ≥200kHz, exhibiting strong compatibility.

[0028] Furthermore, in one embodiment of the present invention, in order to ensure stability on the terminal side, a power-on reset is performed after intervention on the terminal side, such as... Figure 8 As shown, during the power-on reset process of the authentication chip on the terminal side, the first MOSFET 212 is kept off at all times, and then the second MOSFET 213 is controlled to turn off, pulling the voltage of the authentication chip down to 0V, and maintaining this state for t. RSTL The time is determined to ensure the authentication chip is completely powered down, then the second MOSFET 213 is turned on to restore power, and then wait for t. STD During this period, the authentication chip stabilizes, and the host segment can begin sending commands to it. In one embodiment of the present invention, the t... RSTL The value is 300 microseconds, t STD The value is 200 microseconds, which is much smaller than the 8000us + 4000us of existing common chip designs.

[0029] As mentioned earlier, the high-speed communication design features relatively fast reset instructions and unit bit write / read speeds, and can write 8 bytes or read any number of bytes at a time. In particular, the ferroelectric memory cell itself has an ultra-fast erase / write speed, in the nanosecond range, which makes the communication time of the operating chip relatively short.

[0030] The anti-counterfeiting authentication system and method described above can be applied, for example, to electronic cigarettes. The cigarette device serves as the main unit, internally housing the microcontroller and MOSFET. The cartridge, equipped with an authentication chip, serves as the terminal side. The heating wire of the cartridge is connected in parallel with the authentication chip, and the second MOSFET controls the heating wire to ignite the cigarette. Simultaneously, through the aforementioned communication mechanism, the cigarette device can quickly read the cartridge's e-liquid level and control parameters such as heating power based on the e-liquid level.

[0031] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A rapid authentication and anti-counterfeiting system, characterized in that, include: On the terminal side, it includes a fast-write storage medium; as well as The host is configured to send random information to the terminal after it connects, and read the data received and saved by the terminal after a limited time, and determine the authenticity of the terminal based on the read content.

2. The rapid authentication and anti-counterfeiting system as described in claim 1, characterized in that, Based on the read content, determining the authenticity of the data on the terminal side includes: The system determines whether the read content contains valid data. If it does not, it assumes that the terminal does not have a fast write / erase storage medium, and thus determines that the terminal is fake.

3. The rapid authentication and anti-counterfeiting system as described in claim 2, characterized in that, Based on the content read, determining the authenticity of the data on the terminal side also includes: The valid data in the read content is compared with the sent random information. If they match, the terminal side is considered to be true.

4. An anti-counterfeiting authentication system, characterized in that, include: On the terminal side, it includes an authentication chip, which includes a storage module and a computing module. The storage module includes a fast-write storage medium and is configured to store a key, user ID information, and received random information. The computing module is communicatively connected to the storage module and is configured to generate an authentication code based on the key, user ID information, specified data, and random code, and send it to the host for comparison to achieve identity authentication.

5. The anti-counterfeiting authentication system as described in claim 4, characterized in that, Also includes: The host side includes a microcontroller unit and two MOSFETs. The microcontroller unit includes several I / O ports, a ground terminal, and a power supply terminal. The gate of the first MOSFET is connected to the first I / O port of the microcontroller unit, the source is connected to the power supply terminal of the microcontroller unit, and the drain is connected to the third I / O port through a resistor. The gate of the second MOSFET is connected to the second I / O port of the microcontroller unit, the source is connected to the power supply terminal of the microcontroller unit, and the drain is connected to the third I / O port.

6. The anti-counterfeiting authentication system as described in claim 5, characterized in that, The terminal side is pluggably connected to the host. After the terminal side is inserted into the host, the two pins of the authentication chip are respectively connected to the ground terminal of the microcontroller unit of the host and the third IO port.

7. The anti-counterfeiting authentication system as described in claim 5, characterized in that, The computing module integrates a 512-bit input SHA-1 algorithm engine and is configured to calculate a 160-bit information authentication code, enabling dual authentication for writing and reading with the microcontroller unit.

8. An electronic cigarette, characterized in that, This includes the rapid authentication and anti-counterfeiting system as described in any one of claims 1 to 3, or the anti-counterfeiting authentication system as described in any one of claims 4 to 7.

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