An on-chip temperature sensing method for integrated circuit thermal profile monitoring

Abstract

The application discloses a kind of on-chip temperature sensing methods for integrated circuit heat distribution monitoring, belong to semiconductor technical field, to solve the problems such as insufficient space-time resolution, large thermal field reconstruction deviation and high hardware overhead in prior art.The method is embedded by microstructure thermal response unit consisting of high thermal conductivity metal layer and low thermal capacity dielectric layer in chip, to its thermal time constant as dynamic perception parameter, and constructs the three-level architecture of basic perception layer, regional aggregation layer and global coordination layer;Combining pulse heating-cooling time sequence measurement, weighted fusion based on heat flow continuity constraint and data assimilation algorithm based on partial differential equation constraint, high-precision real-time reconstruction of three-dimensional temperature field is realized.The scheme does not need additional process mask, and the area overhead is less than 0.5%, with sub-millimeter spatial and microsecond temporal resolution.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically, it relates to an on-chip temperature sensing method for monitoring the thermal distribution of integrated circuits. Background Technology

[0002] As integrated circuit manufacturing processes continue to evolve towards deeper submicron and even nanometer scales, chip integration and computing density are increasing exponentially, leading to increasingly prominent localized thermal effects. In complex system-on-a-chip (SoC) applications such as high-performance computing, artificial intelligence accelerators, and multi-core processors, the power consumption distribution exhibits high non-uniformity due to significant differences in the load of different functional modules during operation, resulting in a complex three-dimensional temperature gradient field within the chip. This dynamically changing thermal distribution not only directly affects key electrical parameters such as carrier mobility and threshold voltage, inducing timing violations and even logic errors, but may also accelerate electromigration in metal interconnects due to accumulated thermal stress, seriously threatening the long-term reliability and service life of the chip. Therefore, real-time monitoring of the internal thermal distribution of integrated circuits with high spatiotemporal resolution has become an indispensable technical aspect for ensuring stable chip performance and safe operation.

[0003] To address these challenges, the industry has long relied on on-chip integrated temperature sensor arrays for heat distribution sensing. This approach typically embeds several miniature temperature sensing units based on bandgap references or ring oscillators in key hotspot areas of the chip layout. It reconstructs a global thermal map by periodically sampling temperature data at each point and combining this with interpolation algorithms. This method offers advantages such as simple structure and controllable area overhead at early process nodes, and can meet static or quasi-static thermal management requirements to a certain extent. Specifically, bandgap sensors utilize the complementary properties of positive and negative temperature coefficient voltages in silicon to generate an output signal proportional to absolute temperature, while ring oscillator sensors indirectly reflect local temperature rise through the effect of temperature on the propagation delay of the inverter. Both have been validated and applied in multiple generations of commercial processors.

[0004] However, with the continuous development of related technologies and the increasingly stringent performance requirements of application scenarios, some inherent characteristics of the aforementioned technical solutions at the principle level have gradually revealed their limitations in addressing new challenges. Fundamentally, this stems from a profound inherent contradiction between the "discrete sampling-post-reconstruction" paradigm relied upon by existing on-chip sensing architectures and the highly dynamic nature of modern chip thermal behavior. On the one hand, to control hardware resource consumption, sensor deployment density is typically much lower than the actual spatial variation frequency of the thermal gradient, resulting in a large number of unobserved "thermal blind zones" between adjacent sensing points. Especially during sudden high-load switching of heterogeneous computing units, local hotspots may rapidly generate and migrate within milliseconds, making it difficult for sparsely deployed sensors to capture the precise location and intensity of such transient thermal events. On the other hand, traditional interpolation algorithms (such as bilinear or radial basis function interpolation) generally assume that the temperature field is smooth and continuous within local regions. However, under the influence of multiple factors such as high-frequency switching noise, power supply ground bounce, and thermal resistance coupling in packaging, the thermal distribution of actual chips often exhibits nonlinear, non-stationary, or even abrupt characteristics, causing the reconstruction results based on smooth priors to deviate significantly from the real physical field, introducing a non-negligible systematic bias.

[0005] In summary, existing on-chip temperature sensing methods face a dilemma in balancing high spatial resolution and low system overhead. The core issue lies in the mismatch between the sensing mechanism and the dynamic characteristics of the thermal field in the spatiotemporal dimension: discrete, static sensing modes cannot effectively characterize continuous, transient thermophysical processes, while forcibly increasing sampling density or frequency triggers a chain reaction of secondary constraints such as area, power consumption, and signal integrity deterioration. Therefore, how to break through the traditional mindset of "point sampling-surface interpolation" and construct a new paradigm for on-chip temperature sensing that can balance high spatiotemporal resolution, low hardware overhead, and strong environmental adaptability has become a key challenge and an urgent technical problem for those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide an on-chip temperature sensing method for monitoring the thermal distribution of integrated circuits, aiming to solve the problems of insufficient spatiotemporal resolution, significant thermal blind zone and excessive system overhead caused by discrete sampling and static interpolation in the prior art.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] An on-chip temperature sensing method for monitoring thermal distribution in integrated circuits includes the following steps:

[0009] S1, multiple distributed microstructure thermal response units are embedded in the chip layout of the integrated circuit;

[0010] S2, the thermal time constant of the microstructure thermal response unit is used as a dynamic characterization parameter of the local thermal environment. The thermal time constant is defined as the time scale required for the unit to reach a new steady state from the initial steady state after being subjected to external thermal disturbance.

[0011] S3, the microstructure thermal response unit is divided into three functional layers: a basic sensing layer, a regional aggregation layer, and a global coordination layer. The basic sensing layer covers the entire logical region in the form of a regular grid. The regional aggregation layer is divided according to the boundaries of functional modules. Each aggregation node receives the thermal response signals of all basic sensing units in its region and performs a weighted fusion operation based on the thermal flow continuity constraint. The global coordination layer integrates the outputs of each regional aggregation node and drives the thermal field reconstruction engine to run. The thermal field reconstruction engine adopts a data assimilation algorithm based on partial differential equation constraints and dynamically estimates the three-dimensional temperature field inside the chip by combining the physical heat conduction equation and the measured thermal response data.

[0012] Furthermore, in step S1, each of the microstructure thermal response units is composed of alternating stacks of high thermal conductivity metal layers and low thermal capacity dielectric layers, and is electrically connected through an interconnect structure compatible with standard CMOS processes.

[0013] Further, in step S2, the thermal time constant is obtained by pulse heating-cooling timing measurement method: a current pulse with fixed amplitude and fixed width is applied to the target microstructure thermal response unit to generate Joule heating, then the excitation power supply is cut off and the cooling stage is started; the characteristic voltage signal is monitored by a voltage comparator integrated in the unit, and when the voltage crosses the stable reference threshold provided by the on-chip bandgap reference circuit due to temperature drop, the time interval from the excitation cut-off time to the threshold crossing time is recorded as the effective thermal time constant under the current local thermal environment.

[0014] Furthermore, in this invention, the characteristic voltage is taken from both ends of the metal segment in the microstructure thermal response unit, and it exhibits a monotonically decreasing characteristic as the temperature changes. During the cooling process, the voltage rises, and when it reaches the reference threshold, it triggers the comparator to flip and generate a time stamp signal.

[0015] Furthermore, in this invention, the microstructure thermal response units in the basic sensing layer are arranged in a two-dimensional regular grid with a fixed spacing. The grid spacing is set according to the spatial frequency of the chip's maximum expected thermal gradient, satisfying the Nyquist sampling criterion. Each basic sensing unit includes an independent pulse excitation circuit, a voltage comparator, a time-to-digital converter, and a local storage register, which can perform thermal time constant measurement in parallel under the scheduling of the central controller and temporarily store the results in the local register.

[0016] Furthermore, in this invention, the division of the region aggregation layer is strictly aligned with the functional module boundaries of the chip, including CPU cores, GPU computing units, cache arrays, memory controllers, or I / O interfaces; each region aggregation node is connected to the local register output of all basic sensing units within its region via an on-chip bus, and performs weighted fusion operations. Integrated thermal response parameters of each functional area From the formula The calculation yields the weights. , For position The estimated value of the temperature gradient magnitude at a given location is obtained by approximating the difference in thermal time constants between adjacent cells. The preset gradient sensitivity parameters are: T represents temperature, N represents the total number of basic sensing units, and s represents the s-th functional region. This represents the thermal time constant.

[0017] Furthermore, in this invention, the global coordination layer includes a central coordinating controller and a thermal field reconstruction engine; the central coordinating controller schedules the measurement timing of the entire chip, sequentially activates the basic sensing units of each region to avoid power supply noise coupling, and receives the fused thermal response parameters output by the aggregation nodes of each region; the thermal field reconstruction engine runs on a dedicated coprocessor, and based on the data assimilation framework, uses the three-dimensional unsteady heat conduction equation as the state evolution model, uses the measured thermal time constant as the observation data, and iteratively solves for the optimal estimate of the three-dimensional temperature field inside the chip.

[0018] Furthermore, in this invention, the three-dimensional unsteady-state heat conduction equation is:

[0019]

[0020] in For temperature, For material density, For specific heat capacity, Location-dependent thermal conductivity The power density of the local heat source is represented by the equation, which is then discretized within the chip's geometric domain to form a state transition matrix.

[0021] Furthermore, in this invention, the thermal time constant... The relationship between the local thermal property parameters is satisfied as follows:

[0022]

[0023] in The equivalent heat capacity of the microstructure thermal response unit. Equivalent thermal conductivity; given the known unit structure parameters, by measurement Inversion of local thermal diffusivity It is used to constrain the material parameter field in the heat conduction equation.

[0024] Furthermore, in this invention, the data assimilation algorithm adopts an extended Kalman filter framework. Its prediction step advances the temperature field state based on the discretized heat conduction equation, and the update step uses the measured thermal time constant to map to the state space through the observation operator. The observation operator is defined as a nonlinear mapping from the temperature field to the thermal time constant, and its Jacobian matrix is ​​calculated online through the adjoint method to ensure numerical stability.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] (1) This invention breaks through the limitations of the traditional “discrete sampling-post-reconstruction” paradigm by embedding a microstructure thermal response unit composed of a high thermal conductivity metal layer and a low thermal capacity dielectric layer in the chip, using the thermal time constant as a dynamic sensing parameter, and combining it with the pulse heating-cooling timing measurement method. The basic sensing layer covers the entire logical area in the form of a regular grid, follows the Nyquist sampling criterion, and eliminates thermal blind spots; the thermal time constant measurement with microsecond-level time resolution can accurately capture the transient generation and migration process of local hot spots, solve the problem of insufficient spatiotemporal resolution and inability to effectively characterize continuous transient thermophysical processes in the prior art, and realizes real-time monitoring of three-dimensional temperature field with sub-millimeter-level spatial and microsecond-level temporal resolution.

[0027] (2) This invention constructs a three-level architecture of “basic perception layer - regional aggregation layer - global coordination layer”, which improves the accuracy of thermal field reconstruction through layered processing. The regional aggregation layer performs weighted fusion operation based on the heat flow continuity constraint, giving higher weight to regions with significant temperature gradient changes, and adapting to the nonlinear and non-stationary characteristics of chip thermal distribution. The global coordination layer adopts a data assimilation algorithm based on partial differential equation constraints, takes the three-dimensional unsteady heat conduction equation as the state evolution model, and combines the measured thermal time constant to iteratively solve the optimal temperature field estimate, avoiding the systematic bias caused by the smooth prior of the traditional interpolation algorithm, and greatly improving the accuracy and physical consistency of thermal field reconstruction.

[0028] (3) The microstructure thermal response unit of the present invention fully reuses the metal interconnect layer and interlayer dielectric of the existing CMOS process, without the need for additional process masks, and the area overhead is less than 0.5%, achieving seamless integration with advanced process nodes such as 28nm and 14nm. At the same time, through the three-level architecture of layered computing and parallel measurement mechanism, while ensuring high spatiotemporal resolution, it avoids the problem of a sharp increase in power consumption and area overhead caused by blindly increasing sensor density, effectively balancing performance requirements and hardware resource constraints, and providing feasibility for large-scale mass production applications. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the process structure of the method of the present invention. Detailed Implementation

[0030] The present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0031] like Figure 1 As shown, this invention discloses an on-chip temperature sensing method for monitoring thermal distribution in integrated circuits. During the chip manufacturing stage, multiple distributed microstructure thermal response units are first embedded in the back-end interconnect process of the integrated circuit. These units are not independent devices, but rather functional structures naturally formed through metal interconnect layers and interlayer dielectrics compatible with standard CMOS processes. Each microstructure thermal response unit is composed of alternating stacks of high thermal conductivity metal layers and low thermal capacity dielectric layers in the vertical direction. The high thermal conductivity metal layers are made of copper or aluminum, and the low thermal capacity dielectric layers are made of silicon dioxide or low dielectric constant materials. This stacked structure physically exhibits a periodic multilayer composite morphology, typically containing three to five pairs of metal-dielectric layers, with each layer thickness controlled on the order of tens to hundreds of nanometers to ensure that the overall thermal response characteristics are within a measurable range. Electrical connections between the metal layers are achieved through vias, forming a current path that runs through the height of the unit. This path also serves as a Joule thermal excitation channel and a characteristic voltage sampling point. The entire structure fully reuses the metal layers Mx to My (x, y are the number of metal layers defined by the process node) in the existing back-end process, without introducing any additional masking steps, thus ensuring seamless integration with mainstream 28nm, 14nm and even more advanced process nodes.

[0032] The thermal time constant of a microstructure thermal response unit is defined as the time scale required for it to transition from an initial steady state to a new steady state under external thermal disturbance. This parameter directly reflects the thermal diffusion capability of the local thermal environment. To accurately obtain this parameter, a pulse heating-cooling timing measurement method is employed. Specifically, a current pulse of fixed amplitude and width is applied to the target unit, generated by a pulse excitation circuit integrated near the unit. The current flows through the metal path inside the unit, generating controllable Joule heating in a short time, causing the local temperature of the unit to rise instantaneously. Subsequently, the excitation power supply is cut off, and the unit enters the natural cooling phase. During this process, a voltage comparator integrated within the unit continuously monitors its characteristic voltage signal. This characteristic voltage is taken from both ends of a metal segment of a specific length within the unit, whose resistance changes monotonically with temperature. Therefore, under constant bias conditions, its voltage also changes monotonically with temperature. During the cooling phase, as the temperature decreases, the resistance of this metal segment decreases, causing the characteristic voltage to rise. When this voltage rises to a preset threshold, the voltage comparator output flips, generating a precise time stamp signal. The time interval between the self-excitation cutoff moment and the flip moment is recorded as the fusion thermal response parameter under the current local thermal environment.

[0033] In this embodiment, the reference threshold of the voltage comparator is provided by an on-chip integrated bandgap reference circuit. This bandgap reference circuit employs a classic Brokaw structure or a modified version thereof, and its output voltage has an extremely low temperature coefficient, typically less than 10 ppm / °C, thereby ensuring that the reference threshold remains stable throughout the entire operating temperature range. This design eliminates time measurement errors caused by reference voltage drift, significantly improving the long-term reliability and repeatability of the thermal time constant extraction.

[0034] Each microstructure thermal response unit is equipped with a complete local signal processing chain, including a pulse excitation circuit, a voltage comparator, a time-to-digital converter (TDC), and a local memory register. The pulse excitation circuit preferably employs a current-controlled structure, with its output current amplitude set by a 10-bit digital-to-analog converter (DAC), typically ranging from 100μA to 1mA to accommodate power consumption constraints at different process nodes. The pulse width is controlled by a programmable delay chain, achieving sub-nanosecond accuracy to ensure highly consistent energy input for each heating event. The time-to-digital converter uses a ring oscillator-based TDC architecture, achieving a time resolution below 50ps, sufficient to distinguish minute differences in the thermal time constant on the nanosecond scale. The local memory register is implemented using a single-port static random access memory (SRAM) cell, with an area controlled to 20μm. 2 Within this range, the measured thermal time constant value is temporarily stored until it is read by the upper layer.

[0035] All microstructure thermal response units are arranged in a two-dimensional regular grid within the chip's logic region, forming the basic sensing layer. The grid spacing is set according to the spatial frequency of the chip's maximum expected thermal gradient, following the Nyquist sampling criterion. For example, in high-performance computing chips, if the maximum thermal gradient change period is expected to be 200 μm, the grid spacing should not exceed 100 μm. This layout ensures that spatial information of the thermal field is captured without aliasing. The basic sensing layer covers all logical functional areas, including the computing core, cache, interconnects, etc., but avoids noise-sensitive areas such as analog circuits and RF modules to prevent mutual interference.

[0036] A region aggregation layer is set up above the basic sensing layer. This layer is strictly aligned with the physical functional module boundaries of the chip, including but not limited to CPU cores, GPU computing units, final cache (LLC), memory controllers, and high-speed I / O interfaces. Each functional module corresponds to a region aggregation node, which is composed of dedicated hardware logic, typically implemented as a small state machine or configurable logic block. The region aggregation node is connected to the local register outputs of all basic sensing units within its region via an on-chip bus (such as AXI or a custom lightweight bus). Under the scheduling of the central coordinating controller, the region aggregation node periodically reads the thermal time constant data of all basic sensing units within its jurisdiction and performs weighted fusion operations to generate the fused thermal response parameters for that region.

[0037] The weighted fusion operation is designed based on the heat flow continuity constraint: Let the first... Each functional area contains Each basic sensing unit has the following position coordinates: (i=1,2,…,Ns), the measured thermal time constant is Then the fusion thermal response parameters of this region Calculated using the following formula:

[0038]

[0039] Among them, weight Determined by the following formula:

[0040]

[0041] Here Indicates the location The estimated value of the temperature gradient magnitude at a given location. Since the temperature gradient cannot be directly measured, this value is approximated by the difference of the thermal time constants of adjacent basic sensing units. Specifically, for unit i located inside the mesh, its gradient magnitude can be calculated by the difference of the τ values ​​of its four or eight neighborhoods; for boundary units, a one-sided difference or mirror filling strategy is used. The preset gradient sensitivity parameter is calibrated based on the typical thermal behavior of the chip and is usually between 0.1 and 1.0. This exponential weighting mechanism assigns higher weights to high gradient regions, making the fusion results more sensitive to regions with abrupt changes in thermal flux, thereby improving the ability to characterize non-uniform thermal fields.

[0042] Data transmission between the regional aggregation layer and the global coordination layer employs differential signaling and clock-embedded signaling techniques. Differential signaling uses LVDS or similar low-swing differential pairs to effectively suppress common-mode noise; clock-embedded signaling embeds clock information into the data stream using 8b / 10b or 64b / 66b encoding, avoiding jitter and timing skew introduced by individual clock lines. This design ensures signal integrity is maintained even when reading large amounts of sensor data at high speed.

[0043] The global coordination layer consists of a central coordinating controller and a thermal reconstruction engine. The central coordinating controller is responsible for the measurement timing scheduling across the entire chip. Its operating mode is time-sharing polling: it sequentially activates the basic sensing units of each functional area for measurement, avoiding power network voltage drop coupling and thermal crosstalk caused by simultaneous Joule thermal excitation in multiple areas. The controller synchronizes the measurement start time of each unit using a global clock and uniformly triggers TDC latching and data writing after the cooling phase. After completing one round of full-chip scanning, the controller collects the outputs from the aggregation nodes of each area. The value is then passed to the thermal field reconstruction engine.

[0044] The thermal field reconstruction engine runs on a dedicated coprocessor and is implemented based on a data assimilation framework. This engine uses the physical heat conduction equations as the state evolution model and the measured thermal time constant as the observation data, iteratively optimizing the solution to obtain the three-dimensional temperature field inside the chip. The optimal estimate. The physical heat conduction equation is in three-dimensional unsteady-state form:

[0045]

[0046] in For position With time The temperature at that location For material density, For specific heat capacity, It is a location-dependent thermal conductivity tensor (simplified to a scalar field under the isotropic assumption). The local heat source power density primarily originates from transistor switching activity and leakage current. This partial differential equation is discretized within the chip's geometric domain using a finite volume approach, dividing the entire chip into several control volumes, each corresponding to a state variable. The discretized result forms a state transition matrix, used for predictive step calculations.

[0047] Thermal time constant There is a deterministic mapping relationship between the parameters and local thermal properties. For a microstructure thermal response unit, its integrated thermal response parameters can be modeled as follows:

[0048]

[0049] in The equivalent heat capacity of the unit. This is the equivalent thermal conductivity. It is determined by the unit volume, material density, and specific heat capacity; This depends on the thermal contact area between the element and the surrounding medium, the interfacial thermal resistance, and the thermal conductivity of the surrounding material. Given the element's geometry and material parameters, the measured value of τ can be used to invert the local thermal diffusivity. This inversion process is achieved through a pre-calibrated lookup table or analytical model, thereby providing constraints on the material parameter field for the heat conduction equation.

[0050] The data assimilation algorithm employs the Extended Kalman Filter (EKF) framework. In the prediction step, the engine advances the temperature field state based on the discretized heat conduction equation to obtain a priori estimates; in the update step, it utilizes measured data... Values ​​are obtained through the observation operator. Mapped to the state space. Observation operator. Defined as a nonlinear mapping from the temperature field T to the thermal time constant τ, its specific form is as described above. Model and The dependence on the surrounding temperature field jointly determines this. Due to the highly nonlinear nature of this mapping, its Jacobian matrix is ​​calculated online using the adjoint method to ensure numerical stability. The Kalman gain is calculated accordingly and used to correct prediction errors, yielding the posterior temperature field estimate.

[0051] The thermal field reconstruction engine outputs a three-dimensional temperature field at a fixed time step (e.g., 10 μs). The system provides a real-time estimate of the thermal field. This estimate is transmitted to the thermal management controller via an on-chip communication network (such as NoC or a dedicated thermal management bus). Based on this high-resolution thermal field information, the thermal management controller can dynamically adjust the dynamic voltage frequency scaling (DVFS) strategy, trigger task migration to avoid hotspot areas, or adjust the operating status of package-level heat dissipation devices (such as thermoelectric coolers or fans), thereby achieving proactive thermal protection.

[0052] To verify the effectiveness of the present invention, the following examples and comparative experiments were conducted.

[0053] In one specific embodiment, the present invention is implemented on a multi-core processor chip manufactured using a 28nm process. The chip has an area of ​​12 mm × 12 mm and includes 8 CPU cores, 4MB of final-level cache, and a high-speed memory controller. The basic sensing layer deploys 1024 microstructure thermal response units, covering the entire logic area with a 120μm × 120μm grid. Each unit has an area of ​​15μm. 2The total area overhead is 0.107%. The region aggregation layer is divided into 13 regions (8 cores + 1 cache + 1 memory controller + 3 I / O regions). The thermal reconfiguration engine runs on a dedicated RISC-V coprocessor with a clock frequency of 200MHz, and completes a full-chip thermal update every 10μs.

[0054] In the comparative example, a traditional diode-based on-chip temperature sensor solution is used. Sixty-four diode sensors are deployed on the same chip, evenly distributed at the center of each functional module, conforming to common industrial configurations. The sensors are sampled via an ADC with an update period of 1ms.

[0055] Under a typical workload (SPEC CPU2017 intspeed), the response capabilities of the two schemes to sudden hotspot events were recorded. In the experiment, a high-density computing task was artificially triggered within a CPU core for 500 μs, causing the local temperature to rise by 40°C within 200 μs. The experimental results are shown in Table 1.

[0056] Table 1 Results of Response Capability to Sudden Hotspot Events

[0057]

[0058] Data shows that this invention significantly outperforms traditional methods in both spatial and temporal resolution, particularly in capturing rapid, localized thermal events. Although dynamic power consumption is slightly higher, static power consumption is lower, and area overhead remains within acceptable limits. The substantial improvement in temperature estimation accuracy stems directly from the sensitivity of the thermal time constant to thermal diffusion dynamics and the full utilization of the physical model by the data assimilation algorithm.

[0059] Furthermore, in non-stationary thermal event testing, such as multi-core alternating high-load switching scenarios, this invention demonstrates stronger adaptability. Traditional solutions, due to their low sampling rate and only sensing steady-state temperature, cannot track the rapid migration of the thermal field; while this invention, by continuously monitoring the changing trend of the thermal time constant, can predict the location of hotspot formation in advance, providing an early warning window of at least 200μs for thermal management strategies.

[0060] In a preferred embodiment of the present invention, the pulse excitation energy of the microstructure thermal response unit is limited to no more than 10 pJ per pulse to avoid thermal interference to adjacent circuits. The time-to-digital converter employs a multi-phase calibration mechanism, periodically performing self-calibration via an on-chip oscillator to compensate for process variations and aging effects. The weight calculation module in the regional aggregation node uses a combination of lookup tables and linear interpolation to implement an exponential function, thereby reducing hardware complexity.

[0061] As another preferred implementation, the thermal field reconstruction engine supports multi-scale modeling: under steady-state or slowly varying conditions, coarse-grid discretization is used to reduce computational load; when high gradients or rapid changes are detected, it automatically switches to fine-grid mode, focusing on hotspot regions for localized fine-scale reconstruction. This adaptive mechanism optimizes computational resource allocation while ensuring accuracy.

[0062] In summary, this invention constructs a complete on-chip thermal distribution monitoring system through an embedded microstructure thermal response unit, a three-layer hierarchical sensing architecture, and a data assimilation algorithm based on a physical model. This system uses the thermal time constant as a dynamic sensing parameter, overcoming the limitations of traditional steady-state temperature sensing; it balances spatial coverage and semantic relevance through regular grid sampling and functional region aggregation; and it achieves an organic unity of physical consistency and data-driven operation through a reconstruction engine constrained by partial differential equations. The entire solution provides real-time three-dimensional thermal field estimation capabilities with sub-millimeter spatial resolution and microsecond temporal resolution without significantly increasing area or power consumption, laying a solid technical foundation for intelligent thermal management of advanced integrated circuits.

[0063] The above embodiments are merely one of the preferred embodiments of the present invention and should not be used to limit the scope of protection of the present invention. Any modifications or refinements made to the main design concept and spirit of the present invention that are not of substantial significance, but solve the same technical problem as the present invention, should be included within the scope of protection of the present invention.

Claims

1. An on-chip temperature sensing method for monitoring thermal distribution in integrated circuits, characterized in that, Includes the following steps: S1, multiple distributed microstructure thermal response units are embedded in the chip layout of the integrated circuit; S2, the thermal time constant of the microstructure thermal response unit is used as a dynamic characterization parameter of the local thermal environment. The thermal time constant is defined as the time scale required for the unit to reach a new steady state from the initial steady state after being subjected to external thermal disturbance. S3, the microstructure thermal response unit is divided into three functional layers: a basic sensing layer, a regional aggregation layer, and a global coordination layer. The basic sensing layer covers the entire logical region in the form of a regular grid. The regional aggregation layer is divided according to the boundaries of functional modules. Each aggregation node receives the thermal response signals of all basic sensing units in its region and performs a weighted fusion operation based on thermal flow continuity constraints. The global coordination layer integrates the outputs of each regional aggregation node and drives the thermal field reconstruction engine to run. The thermal field reconstruction engine adopts a data assimilation algorithm based on partial differential equation constraints and dynamically estimates the three-dimensional temperature field inside the chip by combining the physical heat conduction equation and measured thermal response data. The regional aggregation layer is strictly aligned with the functional module boundaries of the chip, including CPU cores, GPU computing units, cache arrays, memory controllers, or I / O interfaces. Each regional aggregation node is connected to the local register outputs of all basic sensing units within its region via an on-chip bus and performs weighted fusion operations. Integrated thermal response parameters of each functional area From the formula The calculation yields the weights. , For position The estimated value of the temperature gradient magnitude at a given location is obtained by approximating the difference in thermal time constants between adjacent cells. The preset gradient sensitivity parameters are: T represents temperature, N represents the total number of basic sensing units, and s represents the s-th functional region. Indicates the thermal time constant; The global coordination layer includes a central co-controller and a thermal field reconstruction engine. The central co-controller schedules the measurement timing of the entire chip, sequentially activates the basic sensing units of each region to avoid power supply noise coupling, and receives the fused thermal response parameters output by the aggregation nodes of each region. The thermal field reconstruction engine runs on a dedicated coprocessor, and based on the data assimilation framework, uses the three-dimensional unsteady heat conduction equation as the state evolution model and the measured thermal time constant as the observation data to iteratively solve for the optimal estimate of the three-dimensional temperature field inside the chip.

2. The on-chip temperature sensing method for monitoring thermal distribution in integrated circuits according to claim 1, characterized in that, In step S1, each of the microstructure thermal response units is composed of alternating stacks of high thermal conductivity metal layers and low thermal capacity dielectric layers, and is electrically connected through an interconnect structure compatible with standard CMOS processes.

3. The on-chip temperature sensing method for monitoring thermal distribution in integrated circuits according to claim 2, characterized in that, In step S2, the thermal time constant is obtained by pulse heating-cooling timing measurement method: a current pulse with fixed amplitude and fixed width is applied to the target microstructure thermal response unit to generate Joule heating, then the excitation power supply is cut off and the cooling stage is started; the characteristic voltage signal is monitored by a voltage comparator integrated in the unit, and when the voltage crosses the stable reference threshold provided by the on-chip bandgap reference circuit due to temperature drop, the time interval from the excitation cut-off time to the threshold crossing time is recorded as the effective thermal time constant under the current local thermal environment.

4. The on-chip temperature sensing method for monitoring thermal distribution in integrated circuits according to claim 3, characterized in that, The characteristic voltage is taken from both ends of the metal segment in the microstructure thermal response unit. It exhibits a monotonically decreasing characteristic as the temperature changes. The voltage rises during the cooling process, and when it reaches the reference threshold, it triggers the comparator to flip and generate a time stamp signal.

5. The on-chip temperature sensing method for monitoring thermal distribution in integrated circuits according to claim 4, characterized in that, The microstructure thermal response units in the basic sensing layer are arranged in a two-dimensional regular grid with a fixed spacing. The grid spacing is set according to the spatial frequency of the chip's maximum expected thermal gradient and satisfies the Nyquist sampling criterion. Each basic sensing unit includes an independent pulse excitation circuit, a voltage comparator, a time-to-digital converter, and a local storage register. It can perform thermal time constant measurement in parallel under the scheduling of the central controller and temporarily store the results in the local register.

6. The on-chip temperature sensing method for monitoring thermal distribution in integrated circuits according to claim 1, characterized in that, The three-dimensional unsteady heat conduction equation is: in For temperature, For material density, For specific heat capacity, Location-dependent thermal conductivity The power density of the local heat source is represented by the equation, which is then discretized into a state transition matrix within the chip's geometric domain using a finite volume.

7. The on-chip temperature sensing method for monitoring thermal distribution in integrated circuits according to claim 6, characterized in that, The thermal time constant The relationship between the local thermal property parameters is satisfied as follows: in The equivalent heat capacity of the microstructure thermal response unit. Equivalent thermal conductivity; given the known unit structure parameters, by measurement Inversion of local thermal diffusivity It is used to constrain the material parameter field in the heat conduction equation.

8. The on-chip temperature sensing method for monitoring thermal distribution in integrated circuits according to claim 7, characterized in that, The data assimilation algorithm employs an extended Kalman filter framework. Its prediction step advances the temperature field state based on the discretized heat conduction equation, and the update step uses the measured thermal time constant to map to the state space through the observation operator. The observation operator is defined as a nonlinear mapping from the temperature field to the thermal time constant, and its Jacobian matrix is ​​calculated online using the adjoint method to ensure numerical stability.

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