Interconnected chip-oriented low-power-consumption control system
By incorporating low-dropout linear regulators and power detection modules into the interconnect chips, and combining these with isolation devices to isolate floating signals, the problem of balancing low power consumption and stability in multi-chip interconnect systems is solved, achieving both low power consumption and stable operation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING TSINGTENG MICROSYSTEM CO LTD
- Filing Date
- 2026-01-26
- Publication Date
- 2026-05-19
AI Technical Summary
How can we achieve low-power design in a multi-chip interconnect system while ensuring that the communication interface between chips is not affected by the floating state, thus ensuring the stability of system operation?
By setting low-dropout linear regulators and normally open devices in the first and second chips respectively, combined with power detection modules and isolation devices, the control of the interactive bus is realized, floating signals are isolated, and normal operation is avoided.
It achieves an independent low-power design, improves the stability of chip operation, reduces software development complexity and production costs, and ensures that the system does not affect normal operation when floating.
Smart Images
Figure CN122064221A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of chip technology, and more particularly to a low-power control system for interconnect chips. Background Technology
[0002] Multi-chip interconnect designs have been applied to various types of chips, such as multi-chip heterogeneous computing system architectures. These architectures integrate computing units (such as CPUs, GPUs, and NPUs) with I / O and memory through high-speed interconnects, creating a "system-in-package" similar to a "system-on-a-chip." This multi-chip interconnect enables efficient data sharing and task collaboration. Beyond complex heterogeneous computing architectures, similar applications exist in consumer-grade chips. In mobile phone NFC (Near Field Communication) technology, the contactless system and security authentication system are typically distributed across different chips with different functionalities and security requirements. Each chip has its own power consumption characteristics and power states.
[0003] Therefore, how to achieve cross-chip interconnection, control the entire system to achieve low-power design, and protect the inter-chip communication interface from being affected by the floating state, and ensure the stable operation of the system, is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0004] To address the aforementioned technical problems, this disclosure provides a low-power control system for interconnect chips, thereby resolving the issue that the existing technology cannot adequately balance low-power design and operational stability for interconnect chips.
[0005] This disclosure provides a low-power control system for interconnected chips, including at least a first chip and a second chip interconnected via an interactive bus; The first chip is powered by a first external power supply. The normally open region of the first chip includes a first low-dropout linear regulator and a first normally open device. The first low-dropout linear regulator is configured to output a first power supply to the first normally open device according to the first external power supply. The second chip is powered by a second external power supply. The normally open region of the second chip includes a second low-dropout linear regulator and a second normally open device. The second low-dropout linear regulator is configured to output a second power supply to the second normally open device according to the second external power supply. The interactive bus is configured at least to control communication between the first normally open device and the second normally open device via the first interactive channel; The second chip also includes a first power detection module. The detection terminal of the first power detection module is electrically connected to the first power supply, and the output terminal of the first power detection module is electrically connected to the control terminal of the first isolation device. The first isolation device is disposed on the first interaction channel. The first power detection module is configured to control the first isolation device to isolate the first interaction channel when the voltage of the first power supply is detected to be less than or equal to a first threshold.
[0006] Optionally, the interactive bus is also configured to control the second normally open device to communicate with the first normally open device via the second interactive channel; The first chip also includes a second power detection module. The detection terminal of the second power detection module is electrically connected to the second power supply, and the output terminal of the second power detection module is electrically connected to the control terminal of the second isolation device. The second isolation device is disposed on the second interaction channel. The second power detection module is configured to control the second isolation device to isolate the second interaction channel when the voltage of the second power supply is detected to be less than or equal to a second threshold.
[0007] Alternatively, the first power detection module may be powered by a second power supply. The second power detection module is powered by the first power supply.
[0008] Further optionally, the first threshold is less than or equal to 90% of the first power supply voltage, and the second threshold is less than or equal to 90% of the second power supply voltage.
[0009] Optionally, the on / off region of the first chip includes a first power supply region and a second power supply region; The first power supply area includes a third low-dropout linear regulator and a low-voltage logic device. The third low-dropout linear regulator is configured to receive the first control power output from the first normally open device and control the third low-dropout linear regulator to output a third power supply to the low-voltage logic device. The second power supply area includes a fourth low-dropout linear regulator and a high-voltage logic device. The fourth low-dropout linear regulator is configured to receive the second control power supply output from the first normally open device and control the fourth low-dropout linear regulator to output a fourth power supply to the high-voltage logic device.
[0010] Optionally, a third isolation device is provided between the on / off region of the first chip and the normally open region of the first chip, and the control terminal of the third isolation device is electrically connected to the output terminal of the normally open device. The on / off region of the first chip is configured such that, after the first power area and / or the second power area cease to operate for a first time, the first normally open device controls the first power area and / or the second power area to power down, and controls the third isolation device to isolate the on / off region of the first chip from the normally open region of the first chip.
[0011] Optionally, the first chip further includes a level shifting device, which is disposed between the second power supply area and the normally open area of the first chip, and is powered by the first power supply.
[0012] Optionally, the on / off region of the second chip includes a third power supply region; The third power supply area includes a fifth low-dropout linear regulator and a functional logic device. The fifth low-dropout linear regulator is configured to receive the third control power output from the second normally open device and control the fifth low-dropout linear regulator to output the fifth power supply to the functional logic device.
[0013] Optionally, a fourth isolation device is provided between the on / off region of the second chip and the normally open region of the second chip, and the control terminal of the fourth isolation device is electrically connected to the output terminal of the normally open device. The on / off region of the second chip is configured such that after the third power region is inactive for a second time, the second normally open device controls the third power region to power off and controls the fourth isolation device to isolate the on / off region of the second chip from the normally open region of the second chip.
[0014] Optionally, a power gating device is also included between the second external power supply and the second low-dropout linear regulator. The power gating device is configured to be powered through the output of the first normally open device, and actively shut down the second external power supply to power the second chip.
[0015] The technical solution provided in this disclosure has the following advantages compared with the prior art: 1. In this disclosure, the first chip is powered by a first external power supply. The normally open region of the first chip includes a first low-dropout linear regulator and a first normally open device. The first low-dropout linear regulator receives the first external power supply and outputs a stable, lower first power supply to the first normally open device. The first power supply powers the first normally open device and is the main power supply for the normally open region of the first chip. The first low-dropout linear regulator can be an LDO device, used to provide a stable, low-noise DC voltage output, converting unstable input voltages into a lower, stable output voltage, and suppressing input voltage fluctuations or noise to ensure reliable operation of subsequent circuits.
[0016] 2. The first chip in this disclosure can also typically be provided with a switchable region, which is used to set some of the main functional logic devices of the first chip. The logic devices in the switchable region can run when they need to work normally and can be powered off and not run when they are in sleep mode. In this way, by setting certain modules in the switchable region, the power consumption of the first chip can be reduced, and the low power consumption design effect of the first chip can be achieved.
[0017] 3. In this disclosure, the second chip is powered by a second external power supply. The normally open region of the second chip includes a second low-dropout linear regulator and a second normally open device. The second low-dropout linear regulator receives the second external power supply and outputs a stable, lower second power supply to the second normally open device. The second power supply powers the second normally open device and is the main power supply for the normally open region of the second chip. The second low-dropout linear regulator can also be an LDO device, used to provide a stable, low-noise DC voltage output, converting unstable input voltages into a lower, stable output voltage, and suppressing input voltage fluctuations or noise to ensure reliable operation of subsequent circuits.
[0018] 4. The second chip in this disclosure can also typically be provided with a switchable region, which is used to set some of the main functional logic devices of the second chip. The logic devices in the switchable region can run when they need to work normally and can be powered off and not run when they are in sleep mode. In this way, by setting certain modules in the switchable region, the power consumption of the second chip can be reduced, and the low power consumption design effect of the second chip can be achieved.
[0019] 5. The first chip and the second chip disclosed herein can achieve independent low-power design. Only when there is a task to be processed, the corresponding on / off area is controlled to wake up and enter the power-on working state. At other times, they can be controlled to enter the standby and sleep state, thereby achieving the low-power design effect of the entire system after the first chip and the second chip are interconnected.
[0020] 6. This disclosure interconnects the first chip and the second chip via an interactive bus. The second chip further includes a first power detection module and a first isolation device. The first isolation device is located on the first interactive channel of the interactive bus. When the on / off region of the first chip is in a power-down sleep state to save power, while the on / off region of the second chip is in a power-on normal operating state, the first power detection module can detect when the voltage of the first power supply is less than or equal to a first threshold. This indicates that the first chip is in a power-down sleep state, and the communication signal from the first normally open device to the second normally open device is a floating signal. At this time, the first isolation device can be enabled to isolate the first interactive channel, thereby isolating the floating signal from the first normally open device to the second normally open device. This avoids affecting the normal operation of the second chip, improves the operational stability of the second chip, and effectively protects the second chip.
[0021] 7. The above design of this disclosure can be carried out without the need for software participation, which reduces the complexity of software development and debugging, shortens the product development cycle, and achieves power consumption reduction through hardware architecture optimization. It does not require additional software development costs, which is conducive to saving production costs. The isolation effect of floating signals is directly guaranteed by hardware such as the first power detection module and the first isolation device, avoiding the impact of instability on the stable operation of the entire system. Attached Figure Description
[0022] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.
[0023] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 This is a schematic diagram of a low-power control system for interconnect chips provided in an embodiment of this disclosure; Figure 2 This is another schematic diagram of the low-power control system for interconnect chips provided in the embodiments of this disclosure; Figure 3 This is another schematic diagram of the low-power control system for interconnect chips provided in the embodiments of this disclosure; Figure 4 This is another schematic diagram of the low-power control system for interconnect chips provided in the embodiments of this disclosure; Figure 5 This is another schematic diagram of the low-power control system for interconnect chips provided in the embodiments of this disclosure; Figure 6 This is another schematic diagram of the low-power control system for interconnect chips provided in the embodiments of this disclosure; Figure 7 This is another schematic diagram of the low-power control system for interconnect chips provided in the embodiments of this disclosure; Figure 8 This is another schematic diagram of a low-power control system for interconnect chips provided in an embodiment of this disclosure. Detailed Implementation
[0025] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.
[0026] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.
[0027] Please refer to Figure 1 , Figure 1This is a schematic diagram of a low-power control system for interconnect chips provided in an embodiment of the present disclosure. The low-power control system 000 for interconnect chips provided in this embodiment includes at least a first chip 10 and a second chip 20 interconnected via an interaction bus 30. The first chip 10 is powered by the first external power supply VDD1. The normally open region of the first chip 10 includes a first low dropout linear regulator 101 and a first normally open device 102. The first low dropout linear regulator 101 is configured to output a first power supply Vddc1 to the first normally open device 102 according to the first external power supply VDD1. The second chip 20 is powered by the second external power supply VDD2. The normally open region of the second chip 20 includes the second low dropout linear regulator 201 and the second normally open device 202. The second low dropout linear regulator 201 is configured to output the second power supply Vddc2 to the second normally open device 202 according to the second external power supply VDD2. The interactive bus 30 is configured to control the first normally open device 102 to communicate with the second normally open device 202 via the first interactive channel 30A. The second chip 20 also includes a first power detection module 203. The detection terminal of the first power detection module 203 is electrically connected to the first power supply Vddc1, and the output terminal of the first power detection module 203 is electrically connected to the control terminal of the first isolation device 204. The first isolation device 204 is disposed on the first interaction channel 30A. The first power detection module 203 is configured to control the first isolation device 204 to isolate the first interaction channel 30A when the voltage of the first power supply Vddc1 is detected to be less than or equal to a first threshold.
[0028] Specifically, the low-power control system 000 for interconnect chips provided in this embodiment can be applied to multi-chip interconnect design schemes to achieve low-power design requirements. The low-power control system 000 for interconnect chips in this embodiment may include at least a first chip 10 and a second chip 20. Figure 1 The example uses two chips, but in actual implementation, the number of chips in the entire interconnect system includes, but is not limited to, these.
[0029] It is understood that the first chip 10 and the second chip 20 in this embodiment can be bare chips or packaged chips, and this embodiment does not limit this. The first chip 10 and the second chip 20 in this embodiment are interconnected through an interaction bus 30. It is understood that if the first chip 10 and the second chip 20 are bare chips, the interaction bus 30 can be a die-to-die bus, that is, a direct high-bandwidth, low-latency interconnection communication between bare chips implemented by the interconnection structure within the same package; if the first chip 10 and the second chip 20 are independently packaged chips, the interaction bus 30 can be an interconnection communication structure between two independent chips. In specific implementation, it can be selected and set according to the type of chip. This embodiment will not elaborate on this, as long as the interaction bus 30 can realize the interconnection communication between the first chip 10 and the second chip 20.
[0030] In this embodiment, the first chip 10 is powered by a first external power supply VDD1. The first external power supply VDD1 (e.g., a standard voltage of 3.6V with a 50% tolerance) can be an external input power supply used to power the first chip 10. The first chip 10 may include a normally open region, which refers to the always-on power supply region of the first chip 10. Figure 1 The first chip 10 includes a first normally open region 10A, used to configure devices in the first chip 10 that maintain constant-active logic. The normally open region of the first chip 10 includes a first low-dropout linear regulator 101 and a first normally open device 102. The first low-dropout linear regulator 101 is configured to output a first power supply Vddc1 to the first normally open device 102 based on a first external power supply VDD1. After receiving the first external power supply VDD1, the first low-dropout linear regulator 101 outputs a stable, lower first power supply Vddc1 to the first normally open device 102. The first power supply Vddc1 powers the first normally open device 102 and is the main power supply for the normally open region of the first chip 10. Optionally, the first low-dropout linear regulator 101 can be an LDO device, used to provide a stable, low-noise DC voltage output, converting unstable input voltages into a lower, stable output voltage, and suppressing input voltage fluctuations or noise to ensure reliable operation of subsequent circuits.
[0031] Optionally, the first chip 10 can also typically be configured with a power-down region, which refers to the power-down domain of the first chip 10, such as... Figure 1The first chip 10 includes a first switchable region 10B, which is used to set some of the main functional logic devices of the first chip 10. The logic devices in the switchable region can run when they need to work normally and can be powered off and not run when they are in sleep mode. By setting certain modules in the switchable region, the power consumption of the first chip 10 can be reduced, and the low power consumption design effect of the first chip 10 can be achieved.
[0032] In this embodiment, the first chip 10 can achieve a low-power design for a single chip. When the first chip 10 has a task, it is in working state, and both its normally open and switchable regions are energized and working normally. When the first chip 10 has no task, it is in standby sleep state, with its normally open region energized and working normally, while its switchable region can be controlled to be in power-down sleep state, thereby reducing the static power consumption of the first chip 10. Furthermore, the power consumption of the first low-dropout linear regulator 101 and the first normally open device 102 in the normally open region of the first chip 10 is very small compared to the power consumption of the entire system, thus ensuring that the first chip 10 has an ultra-low power consumption effect in standby sleep state.
[0033] Similarly, the second chip 20 is powered by a second external power supply VDD2. This second external power supply VDD2 (e.g., a standard voltage of 3.6V with a 50% tolerance) can be an external input power supply used to power the second chip 20. The second chip 20 may also include a normally open region, which refers to the always-on power supply region of the second chip 20. Figure 1 The second chip 20 includes a second normally open region 20A, used to configure devices in the second chip 20 that maintain constant-active logic. The normally open region of the second chip 20 includes a second low-dropout linear regulator 201 and a second normally open device 202. The second low-dropout linear regulator 201 is configured to output a second power supply Vddc2 to the second normally open device 202 based on a second external power supply VDD2. After receiving the second external power supply VDD2, the second low-dropout linear regulator 201 outputs a stable, lower second power supply Vddc2 to the second normally open device 202. The second power supply Vddc2 powers the second normally open device 202 and is the main power supply for the normally open region of the second chip 20. Optionally, the second low-dropout linear regulator 201 can also be an LDO device, used to provide a stable, low-noise DC voltage output, converting unstable input voltages into a lower, stable output voltage, and suppressing input voltage fluctuations or noise to ensure reliable operation of subsequent circuits.
[0034] Optionally, the second chip 20 can also typically be configured with a power-down region, which refers to the power-down domain of the second chip 20. Figure 1 The second chip 20 includes a second on / off region 20B, which is used to set some of the main functional logic devices of the second chip 20. The logic devices in the on / off region can run when they need to work normally and can be powered off and not run when they are in sleep mode. By setting certain modules in the on / off region, the power consumption of the second chip 20 can be reduced, and the low power consumption design effect of the second chip 20 can be achieved.
[0035] In this embodiment, the second chip 20 can achieve a low-power design on a single chip. When the second chip 20 has a task, it is in working state, and both its normally open and switchable regions are energized and working normally. When the second chip 20 has no task, it is in standby sleep state, with its normally open region energized and working normally, while its switchable region can be controlled to be in power-down sleep state, thereby reducing the static power consumption of the second chip 20. Furthermore, the power consumption ratio of the second low-dropout linear regulator 201 and the second normally open device 202 in the normally open region of the second chip 20 is very small compared to the power consumption ratio of the entire system, thus ensuring that the second chip 20 has an ultra-low power consumption effect in standby sleep state.
[0036] In this embodiment, the first chip 10 and the second chip 20 can achieve independent low-power design. Only when there is a task to be processed, the corresponding on / off area is controlled to wake up and enter the power-on working state. At other times, they can be controlled to enter the standby and sleep state, thereby achieving the low-power design effect of the entire system after the first chip 10 and the second chip 20 are interconnected.
[0037] In this embodiment, the first chip 10 and the second chip 20 are also interconnected through an interactive bus 30. The interactive bus 30 that enables the first chip 10 and the second chip 20 to communicate with each other includes at least a first interactive channel 30A. The first normally open device 102 is controlled to communicate with the second normally open device 202 through the first interactive channel 30A, thereby enabling the first chip 10 to transmit communication signals to the second chip 20.
[0038] When the first chip 10 and the second chip 20 are interconnected, due to their different power-down states, such as the power-on / off area of the first chip 10 being in a power-down sleep state to save power, while the power-on / off area of the second chip 20 is in a power-on normal working state, the floating state of the first chip 10 will affect the normal and stable operation of the second chip 20 through the first interaction channel 30A of the interaction bus 30.
[0039] To address the aforementioned issues, this embodiment further includes a first power detection module 203 for the second chip 20. The detection terminal of the first power detection module 203 is electrically connected to the first power supply Vddc1, and the output terminal of the first power detection module 203 is electrically connected to the control terminal of the first isolation device 204. The first isolation device 204 is located on the first interactive channel 30A. When the on / off region of the first chip 10 is in a power-down sleep state to save power, while the on / off region of the second chip 20 is in a power-on normal operating state, the first power detection module 203 can detect when the voltage of the first power supply Vddc1 is less than or equal to a first threshold, thus considering the first chip 10 to be in a power-down sleep state. The communication signal between the first normally open device 102 and the second normally open device 202... If the signal is a floating signal, the first isolation device 204 can be enabled to isolate the first interaction channel 30A, thereby isolating the floating signal communicating between the first normally open device 102 and the second normally open device 202. This avoids affecting the normal operation of the second chip 20, improves the operational stability of the second chip 20, and effectively protects the second chip 20. Furthermore, the above design in this embodiment does not require software involvement, reducing the complexity of software development and debugging, shortening the product development cycle, and achieving power consumption reduction through hardware architecture optimization without additional software development costs, which helps save production costs. The isolation effect of the floating signal is directly guaranteed by hardware such as the first power detection module 203 and the first isolation device 204, avoiding the impact of instability on the stable operation of the entire system.
[0040] Optional, such as Figure 2 As shown, Figure 2 This is another schematic diagram of a low-power control system for interconnect chips provided in this embodiment. In this embodiment, the interaction bus 30 is also configured to control the second normally open device 202 to communicate with the first normally open device 102 through the second interaction channel 30B. The first chip 10 also includes a second power detection module 103. The detection terminal of the second power detection module 103 is electrically connected to the second power supply Vddc2, and the output terminal of the second power detection module 103 is electrically connected to the control terminal of the second isolation device 104. The second isolation device 104 is disposed on the second interaction channel 30B. The second power detection module 103 is configured to control the second isolation device 104 to isolate the second interaction channel 30B when the voltage of the second power supply Vddc2 is detected to be less than or equal to a second threshold.
[0041] This embodiment further includes a second power detection module 103 for the first chip 10. The detection terminal of the second power detection module 103 is electrically connected to the second power supply Vddc2, and the output terminal of the second power detection module 103 is electrically connected to the control terminal of the second isolation device 104. The second isolation device 104 is disposed on the second interaction channel 30B. This explains that when the on / off region of the second chip 20 is in a power-down sleep state to save power, while the on / off region of the first chip 10 is in a power-on normal operating state, the second power detection module 103 can detect that the voltage of the second power supply Vddc2 is less than or equal to a second threshold, thus considering that the second chip 20 is in a power-down sleep state. The communication signal from the second normally open device 202 to the first normally open device 102 is... If a floating signal is detected, the second isolation device 104 can be enabled to isolate the second interaction channel 30B, thereby isolating the floating signal communicating between the second normally open device 202 and the first normally open device 102. This avoids affecting the normal operation of the first chip 10, improves the operational stability of the first chip 10, and effectively protects the first chip 10. Furthermore, the above design in this embodiment does not require software involvement, reducing the complexity of software development and debugging, shortening the product development cycle, and achieving power consumption reduction through hardware architecture optimization without additional software development costs, which helps save production costs. The isolation effect of the floating signal is directly guaranteed by the second power detection module 103 and the second isolation device 104, avoiding the impact of instability on the stable operation of the entire system.
[0042] Optionally, the low-power control system for interconnect chips provided in this embodiment can be applied to NFC chip architecture. The NFC chip architecture typically includes the design of CLF (Contactless Front end) and SE (Secure Element) functions. The CLF and SE functions perform different functions. CLF is for contactless communication, and SE is a collection of security authentication algorithm modules. CLF and SE are independent buses and power systems. CLF and SE functions can be designed in different wafer dies. For example, CLF function is designed in the first chip 10 of this embodiment, and SE function is designed in the second chip 20 of this embodiment. Dies are connected by metal wires and communicate with each other using a dedicated communication protocol (interaction bus 30 of this embodiment).
[0043] The CLF function is designed into the first chip 10 of this embodiment, and the SE function is designed into the second chip 20 of this embodiment. According to their respective usage scenarios, different single-die low-power designs can be implemented to adapt to the low-power requirements of different scenarios, and can also ensure that the entire NFC chip system can operate stably without affecting system stability due to instability.
[0044] Optional, please refer to the following: Figure 1 and Figure 2 In this embodiment, the second chip 20 further includes a first power detection module 203, which is powered by the second power supply Vddc2. The first chip 10 also includes a second power detection module 103, which is powered by the first power supply Vddc1.
[0045] This embodiment explains that when the first power detection module 203 is set in the second chip 20 to detect the value of the first power supply Vddc1 in real time, since the first power detection module 203 is in a power-down sleep state in the on / off region of the first chip 10 to save power consumption, while the on / off region of the second chip 20 is in a power-on normal working state, when the voltage of the first power supply Vddc1 is detected to be less than or equal to the first threshold, it is considered that the first chip 10 has been in a power-down sleep state. Therefore, the first power detection module 203 can be powered by the second power supply Vddc2 generated by the second chip 20 to perform detection. Similarly, when the second power detection module 103 is set in the first chip 10 to detect the value of the second power supply Vddc2 in real time, since the second power detection module 103 is in a power-down sleep state in the on / off area of the second chip 20 to save power consumption, while the on / off area of the first chip 10 is in a power-on normal working state, when the voltage of the second power supply Vddc2 is detected to be less than or equal to the second threshold, it is considered that the second chip 20 has been in a power-down sleep state. Therefore, the second power detection module 103 can be powered by the first power supply Vddc1 generated by the first chip 10 to perform detection, thereby avoiding the need for an external power supply to power the power detection module, which helps to reduce the number of external input lines connected to the system.
[0046] Optionally, the low-power control system 000 for interconnect chips provided in this embodiment includes a first power detection module 203 in the second chip 20 that detects the value of the first power supply Vddc1 in real time. When the voltage of the first power supply Vddc1 is detected to be less than or equal to a first threshold, and the first threshold is less than or equal to 90% of the voltage of the first power supply Vddc1 (e.g., the first power supply Vddc1 that enables the first chip 10 to work normally is 1.1V), then when the voltage of the first power supply Vddc1 is detected to drop to the first threshold of 0.99V or less, it is considered that the first chip 10 is in a power-down sleep state. At this time, the communication signal from the first normally open device 102 to the second normally open device 202 is considered to be a floating signal. The first isolation device 204 can be enabled by the first power detection module 203 to isolate the first interaction channel 30A, thereby isolating the floating signal of the communication from the first normally open device 102 to the second normally open device 202, avoiding affecting the normal operation of the second chip 20, improving the operational stability of the second chip 20, and effectively protecting the second chip 20.
[0047] Optionally, the low-power control system 000 for interconnect chips provided in this embodiment includes a second power supply detection module 103 in the first chip 10 that detects the value of the second power supply Vddc2 in real time. When the voltage of the second power supply Vddc2 is detected to be less than or equal to a second threshold, and the second threshold is less than or equal to 90% of the voltage of the second power supply Vddc2, such as the second power supply Vddc2 that enables the second chip 20 to work normally being 1.1V, then when the voltage of the second power supply Vddc2 is detected to drop to the second threshold of 0.99V or less, it is considered that the second chip 20 is in a power-down sleep state. At this time, the communication signal from the second normally open device 202 to the first normally open device 102 is considered to be a floating signal. The second power supply detection module 103 can control the second isolation device 104 to be enabled, isolating the second interaction channel 30B, thereby isolating the floating signal of the communication between the second normally open device 202 and the first normally open device 102, avoiding affecting the normal operation of the first chip 10, improving the operational stability of the first chip 10, and effectively protecting the first chip 10.
[0048] In some alternative embodiments, please refer to Figure 3 , Figure 3 This is another structural schematic diagram of a low-power control system for interconnect chips provided in this embodiment. In this embodiment, the on / off region of the first chip 10, namely the first on / off region 10B, includes a first power supply region 10B1 and a second power supply region 10B2. The first power supply area 10B1 includes a third low-dropout linear regulator 105 and a low-voltage logic device 106. The third low-dropout linear regulator 105 is configured to receive the first control power supply power1 ctrl output by the first normally open device 102 and control the third low-dropout linear regulator 105 to output the third power supply Vddc3 to the low-voltage logic device 106. The second power supply area 10B2 includes a fourth low-dropout linear regulator 107 and a high-voltage logic device 108. The fourth low-dropout linear regulator 107 is configured to receive the second control power supply power2 ctrl output from the first normally open device 102, and control the fourth low-dropout linear regulator 107 to output the fourth power supply Vddc4 to the high-voltage logic device 108.
[0049] In the low-power control system 000 for interconnect chips provided in this embodiment, the first chip 10 can be divided into multiple power domains and controlled. That is, in addition to the normally open region 10A (i.e., the normally open power supply region), the first chip 10 can also include other power domains. For example, the switchable region 10B of the first chip 10 can include at least a first power supply region 10B1 and a second power supply region 10B2 to shut down the power supply to power domains that are not needed, thereby effectively reducing static power consumption. Specifically, the first chip 10 as a whole can include at least one normally open power supply region of the first normally open region 10A, one first power supply region 10B1 of the first switchable region 10B, and one second power supply region 10B2. The first power supply region 10B1 and the second power supply region 10B2 can be shut down and put into sleep mode when not needed. The first power supply area 10B1 of the first switchable region 10B includes a third low-dropout linear regulator 105 and a low-voltage logic device 106. The first power supply area 10B1 can be understood as a low-voltage logic area. The first external power supply VDD1 supplies power to the first chip 10. After receiving the first external power supply VDD1, the first low-dropout linear regulator 101 outputs a stable and lower first power supply Vddc1 to the first normally open device 102. The first power supply Vddc1 supplies power to the first normally open device 102, serving as the main power supply for the normally open area of the first chip 10. After passing through the first normally open device 102, the first power supply Vddc1 generates a control signal of the first control power supply power1 ctrl to control the third low-dropout linear regulator 105 to turn on and outputs the third power supply Vddc3 to the low-voltage logic device 106, supplying power to the low-voltage logic device 106 related to the first power supply area 10B1. The second power supply area 10B2 of the first switchable area 10B includes a fourth low-dropout linear regulator 107 and a high-voltage logic device 108. The second power supply area 10B2 can be understood as the high-voltage logic area. The first external power supply VDD1 supplies power to the first chip 10. After receiving the first external power supply VDD1, the first low-dropout linear regulator 101 outputs a stable and lower first power supply Vddc1 to the first normally open device 102. The first power supply Vddc1 supplies power to the first normally open device 102, serving as the main power supply for the normally open area of the first chip 10. After passing through the first normally open device 102, the first power supply Vddc1 generates a control signal for the second control power supply power2 ctrl, which controls the fourth low-dropout linear regulator 107 to turn on and outputs the fourth power supply Vddc4 to the high-voltage logic device 108, supplying power to the high-voltage logic device 108 related to the second power supply area 10B2.
[0050] In this embodiment, the first chip 10 is configured to include at least a normally open power supply region of a first normally open region 10A, a first power supply region 10B1 of a first switchable region 10B, and a second power supply region 10B2. The first normally open region 10A is defined as a normally open power supply region. When the first chip 10 is in normal working state and sleep / standby state, the logic devices in the first normally open region 10A can operate normally. The first power supply region 10B1 is defined as a switchable low power supply region. When the first chip 10 is in normal working state, it completes the chip function. When the first chip 10 is in sleep / standby state, the logic devices in the first power supply region 10B1, such as the third low-dropout linear regulator 105 and the low-voltage logic device 106, can be powered down. If it returns from sleep / standby state to normal working state, the first normally open device 102 turns on the third low-dropout linear regulator 105, and the logic devices in the first power supply region 10B1 are powered on again, and then operate normally. Similarly, the second power supply area 10B2 is defined as a high power supply area that can be switched on and off. When the first chip 10 is in normal working state, it completes the chip function. When the first chip 10 is in sleep standby state, the logic devices in the second power supply area 10B2, such as the fourth low dropout linear regulator 107 and the high voltage logic device 108, can be powered off. When switching from sleep standby state to normal working state, the first normally open device 102 turns on the fourth low dropout linear regulator 107, and the logic devices in the second power supply area 10B2 are powered on again and then run normal functions.
[0051] In this embodiment, the first chip 10 is designed as a low-power single-chip multi-power-domain design. The first normally open device 102 is retained in the first normally open region 10A. The third low-dropout linear regulator 105 and the low-voltage logic device 106 are grouped into the first power supply region 10B1, which allows power to be switched on and off. The fourth low-dropout linear regulator 107 and the high-voltage logic device 108 are grouped into the second power supply region 10B2, which also allows power to be switched on and off. Both the third low-dropout linear regulator 105 and the fourth low-dropout linear regulator 107 can be powered on and off by the first normally open device 102 in the first normally open region 10A according to actual needs. For example, when the first chip 10 is performing a task, it is in normal working state, and the devices in the first normally open region 10A, the first power supply region 10B1, and the second power supply region 10B2 are all controlled to be energized. When the first chip 10 is not performing a task for a certain period of time... After that, the first chip 10 is considered to have entered a sleep standby state. At this time, only the devices in the first normally open area 10A are controlled to be in a powered state. The first normally open device 102 can control the devices in the first power area 10B1 and the second power area 10B2 to be in a powered-down state according to actual needs, which can greatly reduce the static power consumption of the first chip 10. The operating power consumption of the logic devices in the first normally open area 10A accounts for a very small proportion of the operating power consumption of the entire system, which can ensure that the first chip 10 is in an ultra-low power consumption state when in sleep standby state, thereby achieving the low power consumption effect of the entire system.
[0052] When the first chip 10 has a task to process, the external system wakes it up from its sleep / standby state to its normal operating state via a communication interface. The wake-up logic can be implemented in the logic of the first normally open region 10A. Simultaneously, the first normally open device 102 in the first normally open region 10A will turn on the devices in the first power region 10B1 and the second power region 10B2 according to actual needs. Optionally, the first power region 10B1 is a low-voltage power region, and the second power region 10B2 is a high-voltage power region. Because their functions are different, they can be controlled in real-time in a layered manner. When the first power region 10B1 has a task and the second power region 10B2 does not, only the devices in the first power region 10B1 can be turned on, causing the devices in the second power region 10B2 to power down. Conversely, when the first power region 10B1 has no task and the second power region 10B2 has a task, only the devices in the second power region 10B2 can be turned on, causing the devices in the first power region 10B1 to power down, which helps to further reduce the power consumption of the entire system.
[0053] Optional, such as Figure 4 As shown, Figure 4This is another structural schematic diagram of a low-power control system for interconnect chips provided in this embodiment. In this embodiment, a third isolation device 109 is provided between the on / off region of the first chip 10, such as the first on / off region 10B, and the normally open region of the first chip 10, such as the first normally open region 10A. The control terminal of the third isolation device 109 is electrically connected to the output terminal of the first normally open device 102. The first on / off region 10B of the first chip 10 is configured such that, after the first power region 10B1 and / or the second power region 10B2 ceases operation for a first time, the first normally open device 102 controls the first power region 10B1 and / or the second power region 10B2 to power down, and controls the third isolation device 109 to isolate the first on / off region 10B of the first chip 10 from the first normally open region 10A of the first chip 10; wherein, optionally, the first time is greater than or equal to 1 second.
[0054] This embodiment explains that the first chip 10 is designed as a low-power single-chip multi-power-domain design. When the first chip 10 is performing a task, it is in normal working state, and the devices in the first normally open region 10A, the first power region 10B1, and the second power region 10B2 are all controlled to be in a powered state. After the first chip 10 stops working for a first time, the first time is greater than or equal to 1 second, that is, after the first chip 10 stops working for at least 1 second, the first chip 10 is considered to have entered a sleep standby state. At this time, only the devices in the first normally open region 10A are controlled to be in a powered state. The first normally open device 102 can control the devices in the first power region 10B1, the first power region 10B2 ... The devices in the second power supply area 10B2 are controlled to be in a power-down state, which can greatly reduce the static power consumption of the first chip 10. Furthermore, a third isolation device 109 is provided between the first on / off area 10B and the first normally open area 10A of the first chip 10. The control terminal of the third isolation device 109 is electrically connected to the output terminal of the first normally open device 102. The third isolation device 109 is used to isolate the first on / off area 10B and the first normally open area 10A of the first chip 10, thereby preventing the floating signal of the power-down area from entering the normally open power area and affecting the normal operation of the normally open power area.
[0055] Optional, such as Figure 5 As shown, Figure 5 This is another schematic diagram of a low-power control system for interconnect chips provided in this embodiment. In this embodiment, the first chip 10 further includes a level converter 110, which is disposed between the second power supply region 10B2 and the normally open region 10A of the first chip 10. The level converter 110 is powered by a first power supply Vddc1. The level converter 110 is used to realize level conversion between interactive signals from different power supply regions, which can ensure the integrity and stability of signal transmission within the chip.
[0056] In some alternative embodiments, please refer to Figure 6 , Figure 6 This is another structural schematic diagram of a low-power control system for interconnect chips provided in this embodiment of the present disclosure. In this embodiment, the on / off region of the second chip 20, namely the second on / off region 20B, includes a third power supply region 20B1. The third power supply area 20B1 includes a fifth low-dropout linear regulator 205 and a functional logic device 206. The fifth low-dropout linear regulator 205 is configured to receive the third control power supply power3 ctrl output by the second normally open device 202, and control the fifth low-dropout linear regulator 205 to output the fifth power supply Vddc5 to the functional logic device 206.
[0057] In the low-power control system 000 for interconnect chips provided in this embodiment, the second chip 20 can be divided into a single power domain and controlled accordingly. That is, in addition to the normally open region 20A (i.e., the normally open power supply region), the second chip 20 can also include other power domains. For example, the switchable region 20B of the second chip 20 can at least include a third power region 20B1 to shut down the power supply to power domains that are not needed, thereby effectively reducing static power consumption. Specifically, the second chip 20 as a whole can include at least one normally open power supply region of the second normally open region 20A and one third power region 20B1 of the second switchable region 20B. The third power region 20B1 can be shut down and put into sleep mode when not needed. The third power supply area 20B1 of the second on / off region 20B includes a fifth low-dropout linear regulator 205 and a functional logic device 206. The third power supply area 20B1 can be understood as the main functional logic area. The second external power supply VDD2 supplies power to the second chip 20. After receiving the second external power supply VDD2, the second low-dropout linear regulator 201 outputs a stable, lower second power supply Vddc2 to the second normally open device 202. The second power supply Vddc2 supplies power to the second normally open device 202, serving as the main power supply for the normally open region of the second chip 20. After passing through the second normally open device 202, the second power supply Vddc2 generates a control signal for the third control power supply power3 ctrl, which controls the fifth low-dropout linear regulator 205 to turn on and outputs the fifth power supply Vddc5 to the functional logic device 206, supplying power to the functional logic device 206 related to the third power supply area 20B1.
[0058] In this embodiment, the second chip 20 is configured to include at least a normally open power supply region of a second normally open region 20A and a third power supply region 20B1 of a second switchable region 20B. The second normally open region 20A is defined as a normally open power supply region. When the second chip 20 is in normal working state and sleep / standby state, the logic devices in the second normally open region 20A can operate normally. The third power supply region 20B1 is defined as a switchable power supply region. When the second chip 20 is in normal working state, it completes the chip function. When the second chip 20 is in sleep / standby state, the logic devices in the third power supply region 20B1, such as the fifth low-dropout linear regulator 205 and the functional logic device 206, can be powered down. If it switches from sleep / standby state to normal working state, the second normally open device 202 turns on the fifth low-dropout linear regulator 205, and the logic devices in the third power supply region 20B1 are powered on again, and then operate normally.
[0059] In this embodiment, the second chip 20 is designed as a low-power single-chip single-power-domain design, retaining the second normally open device 202 in the second normally open region 20A, and the fifth low-dropout linear regulator 205 and the functional logic device 206 are grouped into the third power region 20B1 where the power supply can be switched on and off. The fifth low-dropout linear regulator 205 and the functional logic device 206 can be powered on and off by the second normally open device 202 in the second normally open region 20A according to actual needs. When the second chip 20 has a task, it is in normal working state, and the devices in the second normally open region 20A and the third power region 20B1 are controlled to be powered on. After the second chip 20 has no task for a certain period of time, it is considered to have entered a sleep standby state. At this time, only the devices in the second normally open region 20A are controlled to be powered on, and the second normally open device 202 can control the devices in the third power region 20B1 to be powered off according to actual needs. This can greatly reduce the static power consumption of the second chip 20. The operating power consumption of the logic devices in the second normally open region 20A accounts for a very small proportion of the operating power consumption of the entire system, which can ensure that the second chip 20 is in an ultra-low power consumption state when in sleep standby state, thereby achieving the low power consumption effect of the entire system.
[0060] When the second chip 20 has a task to process, the external system can wake up the second chip 20 from the sleep standby state to the normal working state through the communication interface. The wake-up logic can be implemented in the logic of the second normally open area 20A. At the same time, the second normally open device 202 of the second normally open area 20A will turn on the device in the third power area 20B1 according to the actual needs, which helps to further reduce the power consumption of the entire system.
[0061] Optional, such as Figure 7 As shown, Figure 7This is another structural schematic diagram of a low-power control system for interconnect chips provided in this embodiment. In this embodiment, a fourth isolation device 207 is provided between the on / off region 20B of the second chip 20 and the normally open region 20A of the second chip 20. The control terminal of the fourth isolation device 207 is electrically connected to the output terminal of the second normally open device 202. The second on / off region 20B of the second chip 20 is configured such that after the third power region 20B1 is not working for a second time, the second normally open device 202 controls the third power region 20B1 to power off and controls the fourth isolation device 207 to isolate the second on / off region 20B of the second chip 20 from the second normally open region 20A of the second chip 20; wherein, optionally, the second time is greater than or equal to 1 second.
[0062] This embodiment explains that the second chip 20 is designed as a low-power single-chip, single-power-domain design. When the second chip 20 is performing a task, it is in normal working state, and the devices in the second normally open region 20A and the third power region 20B1 are controlled to be in a powered state. After the second chip 20 stops working for a second time (the second time is greater than or equal to 1 second, i.e., after the second chip 20 stops working for at least 1 second), the second chip 20 is considered to have entered a sleep standby state. At this time, only the devices in the second normally open region 20A are controlled to be in a powered state. The second normally open device 202 can control the devices in the third power region 20B1 to be powered according to actual needs. The device is controlled to be in a power-off state, which can greatly reduce the static power consumption of the second chip 20. Furthermore, a fourth isolation device 207 is provided between the second on / off region 20B and the second normally open region 20A of the second chip 20. The control terminal of the fourth isolation device 207 is electrically connected to the output terminal of the second normally open device 202. The fourth isolation device 207 is used to isolate the second on / off region 20B and the second normally open region 20A of the second chip 20, thereby preventing the floating signal of the power-off region from entering the normally open region and affecting the normal operation of the normally open region.
[0063] In some alternative embodiments, please refer to Figure 8 , Figure 8 This is another schematic diagram of a low-power control system for interconnect chips provided in this embodiment. In this embodiment, a power gating device G is also included between the second external power supply VDD2 and the second low-dropout linear regulator 201. The power gating device G is configured to be powered through the output terminal of the first normally open device 102 and actively shut down the second external power supply VDD2 to power the second chip 20.
[0064] This embodiment explains that when the second external power supply VDD2 supplies power to the second chip 20, a power gating device G can be set between the connection path of the second external power supply VDD2 and the second low-dropout linear regulator 201. The power gating device G can be powered through the output terminal of the first normally open device 102. Therefore, when the second chip 20 has no working task, the power supply to the second chip 20 can be actively turned off by cutting off the power gating device G. The power gating device G can be a power gate or a power switch cell. When it is necessary to cut off or restore the main power supply to the second chip 20, i.e., the input or disconnection of the second external power supply VDD2, the power gating device G can be turned on or off to reduce the standby power consumption of the second chip 20, while ensuring the correctness of the circuit function in the entire system.
[0065] It is understood that this embodiment does not limit the specific structure of the power gate device G. For example, the power gate device G can be a MOSFET, etc. When the MOSFET is in the off state, the second external power supply VDD2 can be stopped from supplying power to the second chip 20. In specific implementation, the structure of the power gate device G includes, but is not limited to, this.
[0066] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0067] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A low-power control system for interconnect chips, characterized in that, It includes at least a first chip and a second chip interconnected via an interactive bus; The first chip is powered by a first external power supply. The normally open region of the first chip includes a first low-dropout linear regulator and a first normally open device. The first low-dropout linear regulator is configured to output a first power supply to the first normally open device according to the first external power supply. The second chip is powered by a second external power supply. The normally open region of the second chip includes a second low-dropout linear regulator and a second normally open device. The second low-dropout linear regulator is configured to output a second power supply to the second normally open device according to the second external power supply. The interaction bus is at least configured to control the first normally open device to communicate with the second normally open device through the first interaction channel. The second chip also includes a first power detection module. The detection terminal of the first power detection module is electrically connected to the first power supply, and the output terminal of the first power detection module is electrically connected to the control terminal of the first isolation device. The first isolation device is disposed on the first interaction channel. The first power detection module is configured to control the first isolation device to isolate the first interaction channel when it detects that the voltage of the first power supply is less than or equal to a first threshold.
2. The low-power control system for interconnect chips according to claim 1, characterized in that, The interactive bus is also configured to control the second normally open device to communicate with the first normally open device via the second interactive channel. The first chip further includes a second power detection module. The detection terminal of the second power detection module is electrically connected to the second power supply, and the output terminal of the second power detection module is electrically connected to the control terminal of the second isolation device. The second isolation device is disposed on the second interaction channel. The second power detection module is configured to control the second isolation device to isolate the second interaction channel when the voltage of the second power supply is detected to be less than or equal to a second threshold.
3. The low-power control system for interconnect chips according to claim 2, characterized in that, The first power detection module is powered by the second power supply. The second power detection module is powered by the first power supply.
4. The low-power control system for interconnect chips according to claim 2, characterized in that, The first threshold is less than or equal to 90% of the first power supply voltage, and the second threshold is less than or equal to 90% of the second power supply voltage.
5. The low-power control system for interconnect chips according to claim 1, characterized in that, The on / off regions of the first chip include a first power supply region and a second power supply region. The first power supply area includes a third low-dropout linear regulator and a low-voltage logic device. The third low-dropout linear regulator is configured to receive a first control power supply output from the first normally open device and control the third low-dropout linear regulator to output a third power supply to the low-voltage logic device. The second power supply area includes a fourth low-dropout linear regulator and a high-voltage logic device. The fourth low-dropout linear regulator is configured to receive a second control power supply output from the first normally open device and control the fourth low-dropout linear regulator to output a fourth power supply to the high-voltage logic device.
6. The low-power control system for interconnect chips according to claim 5, characterized in that, A third isolation device is provided between the on / off region of the first chip and the normally open region of the first chip, and the control terminal of the third isolation device is electrically connected to the output terminal of the normally open device. The on / off region of the first chip is configured such that, after the first power area and / or the second power area cease to operate for a first time, the first normally open device controls the first power area and / or the second power area to power down, and controls the third isolation device to isolate the on / off region of the first chip from the normally open region of the first chip.
7. The low-power control system for interconnect chips according to claim 5, characterized in that, The first chip further includes a level shifting device, which is disposed between the second power supply area and the normally open area of the first chip, and is powered by the first power supply.
8. The low-power control system for interconnect chips according to claim 1, characterized in that, The on / off region of the second chip includes a third power supply area; The third power supply area includes a fifth low-dropout linear regulator and a functional logic device. The fifth low-dropout linear regulator is configured to receive the third control power output from the second normally open device and control the fifth low-dropout linear regulator to output a fifth power supply to the functional logic device.
9. The low-power control system for interconnect chips according to claim 8, characterized in that, A fourth isolation device is provided between the on / off region of the second chip and the normally open region of the second chip, and the control terminal of the fourth isolation device is electrically connected to the output terminal of the normally open device. The on / off region of the second chip is configured such that, after the third power region is not working for a second time, the second normally open device controls the third power region to power down, and controls the fourth isolation device to isolate the on / off region of the second chip from the normally open region of the second chip.
10. The low-power control system for interconnect chips according to claim 1, characterized in that, The second external power supply and the second low-dropout linear regulator also include a power gating device, which is configured to be powered through the output of the first normally open device and actively shut down the second external power supply to power the second chip.