Memory management device and method for intelligent processors

Abstract

This application provides a memory management apparatus and method for an intelligent processor. The memory management apparatus includes a prefetch circuit, a setting circuit, and a mapping circuit. The prefetch circuit obtains raw data via a direct memory access circuit. The raw data indicates a mapping relationship between a first virtual address and a plurality of physical addresses of a memory. The setting circuit parses the raw data to sequentially map each of the physical addresses to a plurality of second virtual addresses including the first virtual address and issues a write request. The mapping circuit stores the mapping relationship between each physical address and the corresponding second virtual address as a first mapping table according to the write request, and accesses the memory using the first mapping table according to at least one read request corresponding to at least one channel of the direct memory access circuit.

Description

Technical Field

[0001] This application relates to memory management apparatus and methods, and in particular to memory management apparatus and methods that can improve the memory management efficiency of intelligent processors. Background Technology

[0002] With the development of artificial intelligence technology, the application scenarios of intelligent processors are becoming increasingly diverse. Current technologies can increase the internal storage space of intelligent processors to meet their memory bandwidth access requirements in these scenarios. However, current memory management in intelligent processors may result in fragmented data access (typically involving multiple non-contiguous physical addresses) or require a complete buffer search to obtain memory physical addresses. This leads to inefficient memory management, thus affecting instruction processing efficiency. Summary of the Invention

[0003] In some embodiments of this application, one of the objectives of this application is to provide a memory management apparatus and method that can improve the shortcomings of the prior art.

[0004] In some embodiments of this application, a memory management device applied to an intelligent processor includes a prefetch circuit, a setting circuit, and a mapping circuit. The prefetch circuit obtains raw data via a direct memory access circuit. This raw data indicates a mapping relationship between a first virtual address and a plurality of physical addresses of memory. The setting circuit parses the raw data to sequentially map these physical addresses to a plurality of second virtual addresses containing the first virtual address and issues a write request. The mapping circuit stores the mapping relationship between the physical addresses and the second virtual addresses as a first mapping table according to the write request, and uses the first mapping table to access the memory according to at least one read request corresponding to at least one channel of the direct memory access circuit.

[0005] In some embodiments, the memory management method includes the following operations: obtaining raw data via a direct memory access circuit, the raw data indicating a mapping relationship between a first virtual address and a plurality of physical addresses of a memory; parsing the raw data to sequentially map the physical addresses to a plurality of second virtual addresses including the first virtual address and issuing a write request; storing the mapping relationship between the physical addresses and the second virtual addresses as a first mapping table according to the write request, and using the first mapping table to access the memory according to at least one read request corresponding to at least one channel of the direct memory access circuit.

[0006] The features, implementation, and effects of this application are described in detail below with reference to the accompanying drawings, using preferred embodiments. Attached Figure Description

[0007] [Figure 1 [A schematic diagram of a memory management device is provided based on some embodiments of this case;]

[0008] [ Figure 2 [Drawn according to some embodiments of this case] Figure 1 A schematic diagram of the original data in the diagram;

[0009] [ Figure 3 [Drawn according to some embodiments of this case] Figure 1 A flowchart of the operations performed by the setting circuit in the diagram;

[0010] [ Figure 4A [Drawn according to some embodiments of this case] Figure 1 A schematic diagram of the control circuit in the diagram;

[0011] [ Figure 4B [Drawn according to some embodiments of this case] Figure 1 A schematic diagram of the scheduling of memory access by the setting circuit and the direct memory access circuit; and

[0012] [ Figure 5 A flowchart of a memory management method is drawn based on some embodiments of this case. Detailed Implementation

[0013] All terms used herein have their common meanings. The definitions of the terms used in commonly used dictionaries, and any examples of the use of any term discussed herein, are merely illustrative and should not be construed as limiting the scope or meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0014] As used herein, "coupling" or "connection" can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or moving together. As used herein, the term "circuit" can refer to a device in which at least one transistor and / or at least one active or passive component are connected in a certain manner to process signals.

[0015] Figure 1 A schematic diagram of a memory management device 100 is provided according to some embodiments of this invention. In some embodiments, the memory management device 100 may be applied within an intelligence processing unit to manage the internal memory of the intelligent processing unit to improve the utilization of the internal memory.

[0016] The memory management device 100 includes a pre-fetch circuit 110, a setting circuit 120, a mapping circuit 130, and a control circuit 140. The pre-fetch circuit 110 is coupled to a Direct Memory Access (DMI) circuit 100A to access external memory (e.g., but not limited to, dynamic random access memory) and / or a cache in an intelligent processor. The pre-fetch circuit 110 can obtain raw data OD via the DMI circuit 100A. In some embodiments, the raw data OD may indicate a mapping between a first virtual address and multiple physical addresses in memory (e.g., the aforementioned external memory or cache). The method of setting the raw data OD will be described later. Figure 2 illustrate.

[0017] In some embodiments, during the initial phase or after the memory management device 100 is first started, the prefetch circuit 110 can configure internal circuit parameters (e.g., but not limited to, the value of the cache) by means of a trigger signal TR1 issued via the main processor (e.g., central processing unit) in the system. In subsequent operations, the main processor (and / or control circuit 140) can issue a subsequent trigger signal TR1 according to the command CMD to be executed, so as to control the prefetch circuit 110 to obtain the corresponding raw data OD via the direct memory access circuit 100A.

[0018] In some embodiments, the prefetch circuit 110 further determines whether the remaining data capacity in the prefetch circuit 110 is sufficient to store a portion of the original data OD, so as to selectively store that portion of data until the original data OD is completely stored. For example, the prefetch circuit 110 includes a prefetch control circuit 111 and a buffer circuit 112. The prefetch control circuit 111 is controlled by a trigger signal TR1 and sequentially reads multiple portions of data (which can form the original data OD) via the direct memory access circuit 100A. The prefetch control circuit 111 can determine whether the current remaining data capacity of the buffer circuit 112 is greater than or equal to the data size of a portion of data, so as to selectively control the buffer circuit 112 to store that portion of data. For example, if the current remaining data capacity of the buffer circuit 112 is greater than or equal to the data size of a portion of data, the prefetch control circuit 111 can control the buffer circuit 112 to receive and store that portion of data via the direct memory access circuit 100A. Similarly, the prefetch control circuit 111 can repeat the above operation until the complete original data OD is stored (i.e., prefetched) to the buffer circuit 112. In some embodiments, the direct memory access circuitry 100A in the intelligent processor supports multi-stride, multi-level length, and byte-aligned data transport. Therefore, during the aforementioned prefetching of raw data OD, the prefetch control circuitry 111 can progressively transport these partial data, each of which may have a fixed length, for example, but not limited to, 256 bits.

[0019] The configuration circuit 120 parses the raw data OD to sequentially map the aforementioned plurality of physical addresses to a plurality of second virtual addresses (which include the first virtual address) and issues a write request WR. In some embodiments, the configuration circuit 120 may be implemented by a decoder and a state machine to parse the raw data OD according to its data format to obtain the mapping relationship between the physical addresses and the second virtual addresses. For details on this operation, please refer to... Figure 3 Explanation: After obtaining the above mapping relationship, the setting circuit 120 can send a write request WR to the mapping circuit 130, thereby storing the above mapping relationship as a mapping table. In some embodiments, the setting circuit 120 is controlled by a trigger signal TR2. The control circuit 140 can decode a command CMD from the source autonomous processor to generate the trigger signal TR2, thereby controlling the setting circuit 120 to parse the original data OD to update the mapping relationship between virtual addresses and physical addresses.

[0020] The mapping circuit 130 stores the mapping relationship between the physical addresses and the second virtual addresses in its first storage space as a first mapping table according to the write request WR. It then uses this first mapping table to access the aforementioned external memory or cache according to one or more (at least one) read requests RR1-RRN from the direct memory access circuit 100A, where each read request RR1-RRN corresponds to a different channel of the direct memory access circuit 100A. For example, when a portion of the instructions or operations in the main processor's command CMD is executed by the intelligent processor, the intelligent processor can issue one or more read requests RR1-RRN to the mapping circuit 130 via the direct memory access circuit 100A. Based on these one or more read requests RR1-RRN, the mapping circuit 130 can use the first mapping table (or another mapping table that indicates the mapping relationship between other virtual addresses and other physical addresses) to obtain the actual storage address (i.e., physical address) of the instruction and / or data to be used in the aforementioned external memory or cache, and then retrieve the instruction and / or data to be used from the external memory or cache.

[0021] In some embodiments, the mapping circuit 130 further stores the read requests RR1 to RRN and the write requests WR, and arbitrates the read requests RR1 to RRN and the write requests WR to determine the order in which each of the read requests RR1 to RRN and the write requests WR accesses a plurality of storage spaces of the mapping circuit 130.

[0022] In detail, the mapping circuit 130 includes an arbitration circuit 131 and memory 132. The arbitration circuit 131 includes a buffer 131A, which can temporarily store the read requests RR1 to RRN and the write requests WR. This prevents the arbitration circuit 131 from malfunctioning and stopping receiving write and / or read requests during arbitration due to an excessive number of requests. The arbitration circuit 131 can execute an arbitration algorithm to determine the order in which the write requests WR and the read requests RR1 to RRN access multiple storage spaces in memory 132. In some embodiments, the arbitration algorithm can be, but is not limited to, a round-robin algorithm. Memory 132 includes multiple storage spaces, each of which can store multiple mapping tables. For example, in response to the write request WR, the arbitration circuit 131 can store the mapping relationship between these physical addresses and these second virtual addresses in a first storage space among the multiple storage spaces, as a first mapping table.

[0023] By setting up the arbitration circuit 131, the direct memory access circuit 100A and the setting circuit 120 can access multiple mapping tables in the mapping circuit 130 in parallel, thereby achieving high-efficiency memory management. For example, when the setting circuit 120 stores the first mapping table into the first storage space of memory 132 (corresponding to write request WR) and the direct memory access circuit 100A reads the mapping table of the second storage space in memory 132 (e.g., corresponding to read request RR1), since the storage spaces to be accessed by the two circuits are different, the arbitration circuit 131 allows the setting circuit 120 and the direct memory access circuit 100A to access the first and second storage spaces simultaneously. In other words, in this case, the period during which the setting circuit 120 writes the first mapping table into the first storage space and the period during which the direct memory access circuit 100A reads the second storage space overlap at least partially. In this way, the access efficiency of memory 132 can be improved, thereby improving the efficiency of memory management.

[0024] The control circuit 140 can decode the command CMD from the source autonomous processor and determine the dependencies in the command CMD to set multiple trigger signals TR2 and S1~SN. The control circuit 140 can set multiple virtual buffer values ​​(e.g., based on the multiple trigger signals TR2 and S1~SN) corresponding to multiple virtual buffer values. Figure 4B The multiple virtual cache values ​​EVR1~EVR4 and EVR1'~EVR4' are used to determine the operation status of multiple storage spaces in memory 132, so as to set the output order of multiple trigger signals TR2 and S1~SN. As mentioned above, trigger signal TR2 can trigger setting circuit 120 to issue write request WR, and the remaining multiple trigger signals S1~SN can trigger direct memory access circuit 100A to issue these read requests RR1~RRN. The multiple trigger signals S1~SN correspond to these read requests RR1~RRN respectively. For example, trigger signal S1 can trigger direct memory access circuit 100A to issue read request RR1, and trigger signal S2 can trigger direct memory access circuit 100A to issue read request RR2. And so on, the correspondence between multiple trigger signals S1~SN and these read requests RR1~RRN should be understood. Detailed operation of control circuit 140 will be referred to later. Figure 4A and Figure 4B .

[0025] Figure 2 Drawing based on some embodiments of this case Figure 1 A schematic diagram of the original data OD in the image. (See image for details.) Figure 2 As shown, the original data OD contains multiple columns of data, each column containing 16 pieces of information, and each piece of information can contain 16 bits. In other words, the length of one column of data is 256 bits.

[0026] Taking the data in columns 1 to 3 as an example, based on a right-to-left and top-to-bottom order, the original data OD sequentially includes quantity information (labeled TL=32), tag information (labeled Tag), quantity information (labeled LEN=4), information on the first virtual address (labeled VA), information on multiple entity addresses (labeled PA0~PA3 in sequence), quantity information (labeled LEN=26), information on the first virtual address (labeled VA), information on multiple entity addresses (labeled PA0~PA25 in sequence), quantity information (labeled LEN=1), information on the first virtual address (labeled VA), information on entity addresses (labeled PA0), quantity information (labeled LEN=1), information on the first virtual address (labeled VA), information on entity addresses (labeled PA0), and multiple invalid information (labeled TL=0). It should be noted that the virtual address VA and entity addresses PA0~PA25 in different information fields can represent different addresses. Multiple invalid information entries are fragmented and useless information that can be used to pad data to achieve bit alignment.

[0027] The quantity information TL=32 indicates that the total number of entity addresses to be set is 32. For example, in the data of columns 1 to 3, there are a total of 32 pieces of information related to entity addresses. The tag information is used to allow the setting circuit 120 to determine whether the correct raw data OD has been read. The quantity information LEN=4 indicates the increment of the virtual address VA (equivalent to the number of second virtual addresses). For example, virtual address VA (equivalent to the first virtual address or the first of the second virtual addresses) can correspond to entity address PA0 to its left, virtual address VA+1 (equivalent to the second of the second virtual addresses) can correspond to entity address PA1 to its left, and so on, virtual address VA+3 can correspond to entity address PA3. Furthermore, if we follow this logic further, the subsequent quantity information LEN=26 and virtual address VA can indicate that virtual address VA corresponds to entity address PA0, and virtual address VA+25 corresponds to entity address PA25. Based on this, it should be understood that the above information can indicate the mapping relationship between multiple entity addresses and multiple second virtual addresses.

[0028] Based on the above configuration, multiple physical addresses can be compressed into a single virtual address. For example, in the first column, the quantity information LEN = 4 can map one virtual address VA to four physical addresses PA0 to PA3. In some embodiments, the raw data OD can be generated in advance by an external system or the main processor. For example, the external system and the main processor can prepare the raw data OD in advance based on the relevant scenario applied by the neural network executed by the intelligent processor (i.e., the raw data OD is generated offline). In this way, the amount of data can be compressed and the direct memory access circuit 100A can use consecutive virtual addresses, thereby generating consecutive instructions to reduce the frequency of changing the mapping table.

[0029] Figure 3 Drawing based on some embodiments of this case Figure 1 The flowchart illustrates the operations performed by the setting circuit 120. In some embodiments, the following operations may be used to implement the operation of the state machine.

[0030] In operation S310, the next operation is executed from the idle state via a trigger signal (e.g., trigger signal TR2). In operation S320, the original data is read, and invalid information (e.g., ...) is discarded. Figure 2 If invalid information TL=0 is found in the data, the quantity information (e.g., quantity information TL=32) is checked and verified. If the quantity information is correctly read, operation S330 is executed. In operation S330, tag information (e.g., tag information) is compared to confirm whether the correct raw data has been read. For example, when the control circuit 140 decodes the command CMD, the control circuit 140 can identify the tag of the mapping table to be used for the operation or instruction related to the command CMD. The control circuit 140 can transmit this tag information and the trigger signal TR2 to the setting circuit 120. The setting circuit 120 can compare this tag with the tag information Tag in the raw data OD to determine whether the correct raw data OD has been obtained. If the raw data OD has been obtained correctly, operation S340 is executed. If the raw data has not been obtained correctly, operation S350 is executed to report the error.

[0031] In operation S340, the virtual address information and quantity information (e.g., quantity information TL=32) are parsed. If parsing is complete, operation S360 is executed to parse the information of multiple entity addresses to establish the mapping relationship between multiple second virtual addresses and multiple entity addresses. For example, as described above, in Figure 2In the first column of data, the mapping relationship related to the multiple entity addresses PA0 to PA3 associated with the quantity information LEN = 4 is as follows: virtual address VA corresponds to entity address PA0, virtual address VA+1 corresponds to entity address PA1, virtual address VA+2 corresponds to entity address PA2, and virtual address VA+3 can correspond to the entity address PA3 on the left. In other words, through operations S340 and S360, the setting circuit 120 can restore the compressed mapping relationship (i.e., one virtual address corresponds to multiple entity addresses) in the original data OD to a mapping relationship between multiple virtual addresses and multiple entity addresses. If the number of entity addresses processed in operation S360 is different from the value of the quantity information (e.g., TL = 32), it means that the number of entity addresses is incorrect. In this state, operation S350 is executed to report the error, and after reporting the error, the relevant data is cleared and the system returns to the idle state. In operation S370, a write request is issued and arbitration is waited for to complete. After the mapping relationship between multiple second virtual addresses and multiple entity addresses is stored in the first mapping table, the system returns to the idle state.

[0032] Figure 4A Drawing based on some embodiments of this case Figure 1 A schematic diagram of the control circuit 140 is shown. The control circuit 140 includes an instruction decoder 141, multiple task queue circuits 142[0] to 142[N], multiple trigger circuits 143[0] to 143[N], an external virtual register queue circuit 144, and a dependency confirmation circuit 145.

[0033] Each of the multiple task queue circuits 142[0] to 142[N] can be, but is not limited to, a first-in-first-out (FIFO) circuit. Task queue circuit 142[0] stores the tasks to be executed by setting circuit 120, and task queue circuits 142[1] to 142[N] respectively store the tasks to be executed by the first to Nth channels of direct memory access circuit 100A. Multiple trigger circuits 143[0] to 143[N] are respectively set to correspond to the multiple task queue circuits 142[0] to 142[N]. For example, trigger circuit 143[0] can generate a trigger signal TR2 according to the request issued by task queue circuit 142[0]. Trigger circuit 143[1] can generate a trigger signal S1 to direct memory access circuit 100A according to the request issued by task queue circuit 142[1], so that the first channel of direct memory access circuit 100A issues a read request RR1. Similarly, the trigger circuit 143[N] can generate a trigger signal SN to the direct memory access circuit 100A according to the request issued by the task queue circuit 142[N], so that the Nth channel of the direct memory access circuit 100A issues a read request RRN.

[0034] Instruction decoder 141 can decode command CMD to confirm the instructions or data required by command CMD, and accordingly transmit the relevant task to multiple task queue circuits 142[0] and 142[1] to 142[N]. For example, if the required instructions or data involve the entity address recorded in a new mapping table, instruction decoder 141 can send the task to task queue circuit 142[0]. Trigger circuit 143[0] can thereby generate a new write request WR to control setting circuit 120 to replace the existing mapping table.

[0035] To ensure that the setting circuit 120 and the control circuit 140 can correctly use the multiple mapping tables stored in the mapping circuit 130 in parallel, the operation status of the multiple storage spaces in the mapping circuit 130 can be determined by the external virtual register queue circuit 144 and the dependency confirmation circuit 145, so as to set the output order via multiple trigger signals TR2 and S1~SN. The instruction decoder 141 can decode the command CMD and set the multiple external virtual register values ​​in the external virtual register queue circuit 144 (such as...) according to the dependency between the instructions or data required by the command CMD. Figure 4B Multiple external virtual buffer values ​​(EVR1 to EVR4 and EVR1' to EVR4') are used to record the operational status of multiple storage spaces in the mapping circuit 130 (e.g., whether they are being written to by the setting circuit 120 or being accessed by a channel of the direct memory access circuit). The dependency confirmation circuit 145 can confirm the output order of multiple trigger signals TR2 and S1 to SN based on the dependency between instructions or data and the multiple external virtual buffer values. Based on the dependency between instructions or data, the dependency confirmation circuit 145 can set whether multiple task queue circuits 142[0] to 142[N] can transmit requests to multiple trigger circuits 143[0] to 143[N]. For example, the dependency confirmation circuit 145 can set the output order of multiple trigger signals TR2 and S1 to SN by interrupting the connection between multiple task queue circuits 142[0] to 142[N] and multiple trigger circuits 143[0] to 143[N]. The description here will be referred to later. Figure 4B illustrate.

[0036] Figure 4B Drawing based on some embodiments of this case Figure 1 A schematic diagram of the work schedule for the setting circuit 120 and the direct memory access circuit 100A accessing memory 132. Figure 4BIn the example, the dependency confirmation circuit 145 can determine the order in which the setting circuit 120 and the direct memory access circuit 100A access memory 132 based on the dependencies between multiple instructions. In some embodiments, the dependency confirmation circuit 145 can pre-record the dependencies between multiple instructions and / or data according to various relevant scenarios applied by the intelligent processor, so as to set the output order of multiple trigger signals TR2 and S1 to SN according to the instructions contained in the currently received command CMD.

[0037] For example, in some scenarios, the decoded command CMD contains multiple instructions corresponding to a series of mathematical operations (such as image processing operations or convolution operations). For instance, the first instruction might be a convolution operation, and the second instruction might use the result of the convolution operation for filtering to produce the next output. The dependency verification circuit 145 allows the direct memory access circuit 100A to first use the multiple entity addresses indicated in the first mapping table of memory 132 to access the multiple instructions and / or data used for the convolution operation to perform the first-level operation (e.g., the operation from time t1 to time t2). Then, the dependency verification circuit 145 allows the setting circuit 120 to replace the first mapping table of memory 132 with a second mapping table (e.g., the operation from time t2 to time t3), and controls the direct memory access circuit 100A to access the multiple instructions and / or data used for filtering based on the multiple entity addresses indicated in the second mapping table to perform the second-level operation (e.g., the operation starting at time t3).

[0038] Specifically, at time t1, channel 1 of the direct memory access circuit 100A is reading the first mapping table in memory 132 to obtain physical addresses and fetch instructions or data from the aforementioned external memory or cache for convolution operations. Therefore, the external virtual cache value EVR1 corresponding to channel 1 of the direct memory access circuit 100A (stored in the external virtual cache queue circuit 144) is switched to a default value (indicated by a slashed background) to indicate that the corresponding storage space in memory 132 storing the first mapping table is busy. At time t2, channel 1 of the direct memory access circuit 100A finishes reading the first mapping table. The setting circuit 120 can clear the corresponding storage space and write the second mapping table to that storage space. Therefore, the setting circuit 120 can switch the corresponding external virtual cache values ​​EVR1' and EVR2' (stored in the external virtual cache queue circuit 144) to their default values ​​to indicate that the corresponding storage space in memory 132 is busy. At time t3, the setting circuit 120 completes the replacement of the second mapping table, and channel 2 of the direct memory access circuit 100A is reading the second mapping table in memory 132 to obtain the physical address and fetch instructions or data from the aforementioned external memory or cache for filtering processing.

[0039] Channels 3 and 4 of the direct memory access circuit 100A access the second mapping table stored in the second storage space of memory 132 to obtain the required data and / or data. Since the first storage space is different from the second storage space, the operating time of channel 3 may partially overlap with the operating time of channel 1 and / or the time when the setting circuit 120 writes to the first storage space. Similarly, the operating time of channel 2 may partially overlap with the operating time of channel 3 or 4 and / or the time when the setting circuit 120 writes to the second storage space (i.e., the time when the external virtual buffer values ​​EVR3' and EVR4' are busy).

[0040] The operations between channels 3 and 4 of the direct memory access circuit 100A and the setting circuit 120 are similar to those described above, and therefore will not be repeated. It can be understood from the above operations that the replacement mapping table operation of the setting circuit 120 does not affect the processing efficiency of channel 3; similarly, the replacement mapping table operation of the setting circuit 120 does not affect the processing efficiency of channel 1. Accordingly, by setting multiple external virtual cache values ​​EVR1 to EVR4 and EVR1' to EVR4', the setting circuit 120 and the direct memory access circuit 100A can access multiple storage spaces of memory 132 in parallel with higher efficiency.

[0041] Figure 5A flowchart of a memory management method 500 is provided according to some embodiments of this invention. In operation S510, raw data is obtained via a direct memory access circuit. This raw data indicates a mapping relationship between a first virtual address and a plurality of physical addresses of memory. In operation S520, the raw data is parsed to sequentially map these physical addresses to a plurality of second virtual addresses containing the first virtual address, and a write request is issued. In operation S530, the mapping relationship between these physical addresses and these second virtual addresses is stored as a first mapping table according to the write request, and the memory is accessed using the first mapping table according to at least one read request corresponding to at least one channel of the direct memory access circuit.

[0042] The descriptions of the above operations can be found in the foregoing embodiments, and therefore will not be repeated. The operations of the memory management method 500 described above are merely examples and are not limited to being executed in the order shown in this example. Without departing from the operation mode and scope of the embodiments of this case, the various operations in the memory management method 500 may be appropriately added, replaced, omitted, or executed in a different order (for example, they may be executed simultaneously or partially simultaneously).

[0043] In summary, the memory management device and memory management method in some embodiments of this case can improve the efficiency of memory management by dynamically updating the mapping table, generating compressed mapping data offline, and parallelizing access within the intelligent processor, thereby improving the operating efficiency of the intelligent processor.

[0044] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art can make changes to the technical features of this case based on the express or implied content of this case. All such changes may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the scope of the patent application in this specification.

[0045] [Symbol Explanation]

[0046] 100: Memory Management Device

[0047] 100A: Direct Memory Access Circuit

[0048] 110: Prefetch circuit

[0049] 111: Prefetch control circuit

[0050] 112: Buffer circuit

[0051] 120: Setting Circuit

[0052] 130: Mapping circuit

[0053] 131: Arbitration Circuit

[0054] 131A: Buffer

[0055] 132: Memory

[0056] 140: Control Circuit

[0057] 141: Instruction Decoder

[0058] 142[0]-142[N]: Task queue circuit

[0059] 143[0]-143[N]: Trigger circuit

[0060] 144: External Virtual Buffer Queue Circuit

[0061] 145: Dependency Confirmation Circuit

[0062] 500: Memory Management Methods

[0063] CMD: command

[0064] EVR1-EVR4, EVR1'-EVR4': Virtual buffer values

[0065] LEN=4, LEN=26, LEN=1, LEN=5, LEN=1: Quantity information

[0066] OD: Raw Data

[0067] PA0-PA25: Physical address

[0068] RR1-RRN: Read Request

[0069] S1-SN: Trigger signal

[0070] S310, S320, S330, S340, S350, S360, S370: Operation

[0071] S510, S520, S530: Operation

[0072] TL=32, TL=4, TL=13: Quantity information

[0073] TR1, TR2: Trigger signals

[0074] Tag: Tag Information

[0075] VA: Virtual Address

[0076] WR: Write Request

[0077] t1~t3: Time

Claims

1. A memory management device, characterized by, Applied to an intelligent processor, the memory management device includes: A prefetch circuit obtains raw data via a direct memory access circuit, the raw data indicating a mapping between a first virtual address and a plurality of physical addresses of a memory. A circuit is configured to parse the original data to sequentially map each of the entity addresses to a plurality of second virtual addresses containing the first virtual address and issue a write request. as well as A mapping circuit stores a first mapping table based on the write request, representing the mapping relationship between each physical address and the corresponding second virtual address, and uses the first mapping table to access the memory based on at least one read request from at least one channel corresponding to the direct memory access circuit.

2. The memory management device as described in claim 1, characterized in that, The prefetch circuit includes: A buffer circuit; and A prefetch control circuit determines whether the remaining data capacity of the buffer circuit is greater than or equal to the amount of a portion of the original data, so as to selectively control the buffer circuit to store the portion of data.

3. The memory management device as described in claim 1, characterized in that, The original data includes a first quantity information, a second quantity information, a tag information, information of the first virtual address, and information of each of the entity addresses, wherein the first quantity information indicates the quantity of each of the entity addresses, and the second quantity information indicates the quantity of each of the second virtual addresses.

4. The memory management device as described in claim 3, characterized in that, The setting circuit determines whether the original data has been correctly prefetched based on the first quantity information and the tag information, and maps each entity address to the second virtual address in sequence based on the information of the first virtual address, the second quantity information and the information of each second virtual address.

5. The memory management device as described in claim 4, characterized in that, The setting circuit sequentially increments the first virtual address according to the information of the first virtual address and the second quantity information to generate each second virtual address.

6. The memory management device as claimed in claim 1, characterized in that, The mapping circuit updates and arbitrates the write request and the read request of each channel to determine the order in which each of the write request and the at least one read request accesses a storage space used to store the first mapping table.

7. The memory management device as claimed in claim 1, characterized in that, When the mapping circuit stores the first mapping table to a first storage space in the mapping circuit and the at least one read request reads a second storage space in the mapping circuit, the period during which the first mapping table is stored in the first storage space and the period during which the second storage space is read in response to the at least one read request at least partially overlap.

8. The memory management device as claimed in claim 1, characterized in that, The mapping circuit includes: One memory unit contains multiple storage spaces; as well as An arbitration circuit temporarily stores the at least one read request and the at least one write request, and determines the order in which the write request and the at least one read request access the respective storage spaces. In response to the write request, the arbitration circuit stores the first mapping table to a corresponding storage space in each of the storage spaces to replace a second mapping table previously stored in the corresponding storage space.

9. The memory management device according to any one of claims 1-8, characterized in that, The device further includes: A control circuit decodes an instruction from a main processor and determines the dependencies of the instruction to set a plurality of trigger signals. Based on the values ​​of a plurality of external virtual buffers corresponding to each trigger signal, it determines the operating state of a plurality of storage spaces in the mapping circuit to set the output order of each trigger signal. Among them, a first trigger signal is used to trigger the setting circuit to issue the write request, and the remaining trigger signals are used to trigger the direct memory access circuit to issue the at least one read request.

10. A memory management method, characterized in that, The method includes: Raw data is obtained via a direct memory access circuit, the raw data indicating the mapping relationship between a first virtual address and a plurality of physical addresses of a memory; The original data is parsed to sequentially map each of the entity addresses to a plurality of second virtual addresses containing the first virtual address and a write request is issued; as well as The mapping relationship between each entity address and each second virtual address is stored in a first mapping table according to the write request, and the memory is accessed by using the first mapping table according to at least one read request of at least one channel corresponding to the direct memory access circuit.

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