EMMC data guarantee method and system based on key bit backup and active recovery

Abstract

The invention discloses an eMMC data guarantee method and system based on key bit backup and active recovery, an NAND flash memory comprises a main data storage area and a high-reliability storage area, and after data are written into the main data storage area, fragile bits prone to bit flipping are identified; the backup information of the fragile bit is stored in a high-reliability storage area, the backup information is scanned regularly, and the health state of the fragile bit is evaluated based on the current voltage of the fragile bit; when the health state is abnormal, a recovery operation is performed on the fragile bit using the backup value. Therefore, in the process of writing data into the eMMC storage system, by identifying and extracting fragile bits and backing up relevant information of the fragile bits to a high-reliability storage area, the system continuously monitors the health conditions of the bits, and once the bits are found to have a sign of voltage drift or slight flipping, the data are written into the eMMC storage system. The backup value is immediately used to actively recover it, thereby completing charge refresh before an uncorrectable error occurs in the fragile bit.

Description

Technical Field

[0001] This invention relates to the field of data protection technology for storage devices, and in particular to an eMMC data protection method and system based on critical bit backup and active recovery. Background Technology

[0002] As the core storage medium of eMMC storage systems, NAND flash memory inherently suffers from data retention issues, and bit flips are prone to occur during long-term storage. Traditional data protection schemes mainly rely on ECC (Error Correction Code) technology, which can only correct a limited number of errors during data reading. For cold data that has not been accessed for a long time, errors will continue to accumulate. When the number of errors exceeds the error correction capability of ECC, it will lead to irreversible data loss.

[0003] To address this issue, existing technologies have proposed read wear leveling schemes. These schemes set a read count threshold, and when the number of reads of a data block reaches the threshold, the entire data block is moved. However, this scheme has significant drawbacks. Its write amplification factor is high, which increases the write pressure on the storage medium, reduces operating efficiency, and also shortens the lifespan of the storage medium. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method that can effectively reduce the risk of uncorrectable errors by actively intervening in the early stages or before errors occur, extend the storage life of cold data, and meet the long-term reliability requirements of backup devices, archive storage, and other scenarios.

[0005] The objective of this invention is achieved through the following technical solution: In a first aspect, this application discloses an eMMC data assurance method based on critical bit backup and active recovery, for NAND flash memory. The NAND flash memory includes a main data storage area and a high-reliability storage area. The method includes: after data is written to the main data storage area, identifying vulnerable bits that are prone to bit flipping; storing backup information of the vulnerable bits in the high-reliability storage area, the backup information including at least a physical address, bit offset, backup value, and health status; periodically scanning the backup information and assessing the health status of the vulnerable bits based on their current voltage; and when the health status is abnormal, performing a recovery operation on the vulnerable bits using the backup value.

[0006] Furthermore, the identification of vulnerable bits includes: calculating the voltage margin of the bit, wherein the voltage margin is the absolute value of the difference between the read voltage of the bit and a reference voltage threshold; calculating the vulnerability index of the bit based on the voltage margin; comparing the vulnerability index with a preset vulnerability threshold, and identifying the bit as a vulnerable bit when the vulnerability index is greater than the vulnerability threshold.

[0007] Furthermore, the calculation of the voltage margin M includes: Among them, V read V is the read voltage for a bit. f Reference voltage threshold; Vulnerability index of this bit: F = 1 / (M + ϵ) Where ϵ is a small constant used to avoid division by zero errors; θ is the fragility threshold. When F>θ, the bit is marked as a fragility bit.

[0008] Furthermore, the vulnerability threshold is dynamically adjusted based on the current P / E cycle number of the NAND flash memory.

[0009] Furthermore, the adjustment formula for the vulnerability threshold θ is as follows: Where, θ base It is the basic threshold, C PE It is the current P / E cycle number, C max It is the maximum rated P / E cycle number, and α is the adjustment factor.

[0010] Furthermore, the health status assessment based on the current voltage of the vulnerable bit includes: calculating the voltage deviation of the current voltage relative to the normal voltage range; comparing the voltage deviation with a preset safety margin threshold and a flip warning threshold to determine the health status.

[0011] Furthermore, the health status includes: a stable state, when the voltage deviation is greater than or equal to the safety margin threshold; a warning state, when the voltage deviation is less than the safety margin threshold and greater than or equal to the flip warning threshold; and a flipped state, when the voltage deviation is less than the flip warning threshold and the current read value of the bit does not match the backup value.

[0012] Furthermore, the periodic scanning and recovery operations are performed during the storage system's idle periods.

[0013] Secondly, this application discloses an eMMC data protection system based on critical bit backup and active recovery, including an application layer, an eMMC controller layer and a NAND flash physical layer, wherein the eMMC controller layer is used to execute the eMMC data protection method based on critical bit backup and active recovery.

[0014] Furthermore, the eMMC controller layer includes: an identification module configured to identify vulnerable bits prone to bit flipping; a backup storage unit located in the high-reliability storage area for storing backup information of the vulnerable bits; and a monitoring and recovery unit configured to periodically scan the backup storage unit, assess the health status of the vulnerable bits, and perform a recovery operation when the health status is abnormal. The beneficial effects of this invention are: during the process of writing data into the eMMC storage system, by identifying and extracting vulnerable bits (i.e. bits with low voltage margin and prone to flipping), the relevant information of these vulnerable bits is backed up to a high-reliability storage area. The system continuously monitors the health status of these bits, and once signs of voltage drift or slight flipping are detected, it immediately uses the backup value to actively restore them, thereby completing the charge refresh before the vulnerable bits cause uncorrectable errors. Attached Figure Description

[0015] Figure 1 This is a schematic flowchart of an eMMC data assurance method based on critical bit backup and active recovery according to some embodiments of this application; Figure 2 This is a schematic diagram illustrating the principle of an eMMC data protection method based on critical bit backup and active recovery according to some embodiments of this application; Figure 3 This is a schematic diagram illustrating the principle of an eMMC data protection system based on critical bit backup and active recovery according to some embodiments of this application. Detailed Implementation

[0016] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] refer to Figures 1-2 This application describes an eMMC data assurance method based on critical bit backup and active recovery, applicable to NAND flash memory. The NAND flash memory includes a main data storage area and a high-reliability storage area, where the high-reliability area can be an SLC cache, such as... Figure 1As shown, the method includes: reading the voltage margin after writing data to the main data storage area to obtain the bit read voltage as V. read The reference voltage threshold (used to distinguish between 0 and 1) is V. f The voltage margin M is defined as: Then, calculate the vulnerability index of that bit: F = 1 / (M + ϵ) Here, ϵ is a small constant (e.g., ϵ = 10−6) used to avoid division-by-zero errors, and a fragility threshold θ is set. When F > θ (considering the fragility threshold θ), the bit is marked as a fragility bit. The identified fragility bits are prone to bit flipping.

[0018] The high-reliability storage area stores backup information of the vulnerable bit, including physical address, bit offset, backup value, and health status (stable, warning, flipped). The backup storage unit is scanned periodically, and its health status is assessed based on the current voltage of the vulnerable bit. When the assessment indicates an abnormal health status, the backup value is used to perform a recovery operation on the vulnerable bit.

[0019] In other words, during the process of writing data into the eMMC storage system, vulnerable bits (i.e. bits with low voltage margin and prone to flipping) are identified and extracted, and the relevant information of these vulnerable bits is backed up to the high-reliability storage area. The system continuously monitors the health status of these bits, and once signs of voltage drift or slight flipping are detected, it immediately uses the backup value to actively restore them, thereby completing the charge refresh before the vulnerable bits cause uncorrectable errors.

[0020] In some embodiments, to adapt to the aging process of the storage medium, the fragility threshold θ can be dynamically adjusted, and the adjustment formula is: Where, θ base It is the basic threshold, C PE It is the current P / E cycle number, C max α is the maximum rated number of P / E cycles, and α is the adjustment factor, typically 0.1. As the flash memory ages, the threshold decreases, and more bits are identified as vulnerable. As the flash memory usage time increases and the number of P / E cycles increases, the vulnerability threshold will decrease accordingly, allowing more aged and unstable bits to be identified as vulnerable bits.

[0021] Assessing the health status of vulnerable elements includes: setting the normal voltage range of the bits to [V]. low V high ], V current Given the current voltage of a bit, the formula for calculating the voltage deviation D is: ; Based on the voltage deviation D, combined with the safety margin threshold β and the flip warning threshold γ, the health status of the bit is determined: when D≥β, the bit status is stable, where the typical value of β is, for example, 0.2V; when γ≤D<β, the bit status is in warning mode, where the typical value of γ is, for example, 0.1V; when D<γ and the current read value of the bit does not match the backup value (at which point ECC can still correct the error), the bit status is flipped. All of the above parameters can be embedded into the eMMC controller firmware after experimental calibration.

[0022] To better illustrate this, let's consider an execution flow, and refer to... Figure 1 First, the data is written to the main storage block (such as TLC or QLC storage block). After the write operation is completed, a read verification is performed. Then, the vulnerability index F of each bit is calculated. When F is greater than the vulnerability threshold θ, the physical address, bit offset, backup value and other information of the bit are recorded in the critical bit backup table and its initial health state is set to stable. If F does not reach the threshold, no record is made, thus completing the write and marking process.

[0023] refer to Figure 2 As shown, when the timer determines that an idle period has begun, it triggers the background health monitoring engine to start working. The detection method is detailed in the aforementioned embodiment. This engine first reads all records in the key bit backup table, and for each record's corresponding bit, it reads its current voltage V in the main data block. current The voltage deviation D is calculated using the above health status assessment formula, and the health status S is determined. When the bit status is "warning" or "flipped", the backup value stored in the backup table is used to perform a programming operation (i.e., charge refresh) on the bit. After the operation is completed, the health status of the bit in the backup table is updated to stable, and the monitoring and recovery of a single bit is completed. After processing all records in sequence, the monitoring and recovery phase ends.

[0024] For example, a data block contains 8 bits, with a reference voltage V. ref =2.0V (below 2.0V is judged as data 0, above 2.0V is judged as data 1), vulnerability threshold θ=2.0. Of course, this is just an example. In different examples, it can be calculated based on the dynamic threshold adjustment formula. Safety margin threshold β=0.2V, flip warning threshold γ=0.1V.

[0025] During the data writing and marking phase, after the data is written to the main memory block, the voltage value of each bit is read as follows: Bit 1: 1.8V, Bit 2: 2.1V, Bit 3: 1.95V, Bit 4: 2.3V, Bit 5: 1.99V, Bit 6: 2.0V, Bit 7: 1.7V, Bit 8: 2.4V.

[0026] To illustrate the principle, we will use a theoretical state as an example, thus ignoring ϵ. We will calculate the vulnerability index F using the formula to obtain the vulnerability index for each element: The values ​​for bit 1 are: F = 1 / ∣1.8−2.0∣ = 5.0, F = 1 / ∣2.1−2.0∣ = 10.0, F = 1 / ∣1.95−2.0∣ = 20.0, F = 1 / ∣2.3−2.0∣ = 3.33, F = 1 / ∣1.99−2.0∣ = 100.0, F = 1 / ∣2.0−2.0∣ = ∞ (this is a theoretical value; in practical applications, ϵ is used to avoid division by zero), F = 1 / ∣1.7−2.0∣ = 3.33, and F = 1 / ∣2.4−2.0∣ = 2.5. Since the F values ​​of bits 3, 5, and 6 are all greater than θ=2.0, these three bits are identified as vulnerable bits, and their backup values ​​are 1, 1, and 1 respectively (determined according to the reference voltage in different examples). The physical address, bit offset, backup value, and "stable" status of these bits are recorded in the critical bit backup table.

[0027] During the monitoring and recovery phase, assuming that after a period of use, the background health monitoring engine starts a scan during system idle periods and reads the current voltage V of bit 5 recorded in the critical bit backup table. current =1.92V, the normal voltage range of this bit is set to [1.8V, 2.2V] based on device characteristics. According to the voltage deviation calculation formula D=min(∣1.92−1.8∣,∣1.92−2.2∣)=0.12V, since γ=0.1V≤D=0.12V<β=0.2V, the health status of bit 5 is determined to be "warning". At this time, the background health monitoring and recovery engine triggers the recovery operation, uses the backup value 1 stored in the backup table to perform a programming operation on bit 5, and restores its voltage to a stable value (e.g., 2.0V). After the recovery is completed, the health status of bit 5 in the critical bit backup table is updated to "stable", completing the recovery process of a single warning state bit. Understandably, eMMC controllers typically have firmware programming capabilities, allowing direct integration of vulnerable bit identification modules and background health monitoring engines without additional hardware costs. Regarding the storage requirements of the backup table, assuming each backup record occupies 10 bytes, for a 1GB storage capacity, backing up 0.1% of vulnerable bits (approximately 8 million bits) would require a backup table size of approximately 80MB. The eMMC's SLC cache can fully meet this storage requirement, and the high reliability of the SLC cache ensures the security of backup data. Furthermore, the existing eMMC system's read verification mechanism can be directly extended for voltage margin analysis without redesigning the underlying verification logic.

[0028] Furthermore, both background health monitoring and recovery operations are performed during system idle periods, and actual testing shows that the impact on foreground I / O performance is less than 1%, having virtually no impact on normal user operation. The recovery operation targets only a single vulnerable bit, with extremely short programming time, and will not cause a system performance bottleneck. Simultaneously, this solution is fully compatible with existing ECC error correction mechanisms, requiring no modification to the upper-layer application; only adjustments to the eMMC controller firmware are needed. Parameters can also be continuously optimized based on actual field operating data to improve adaptability. Therefore, the method in this embodiment can be implemented through firmware upgrades, without the need for additional hardware purchases. The increase in cost per device is negligible, while the reduction in write amplification significantly extends the lifespan of storage devices, offering significant economic benefits for large-scale deployment scenarios.

[0029] In some embodiments, the typical parameter ranges and calibration data obtained through accelerated life testing are as follows: Among the vulnerability identification parameters, the basic vulnerability threshold θ base The typical value range is 1.5 to 3.0, dimensionless, and determined through experimental calibration; the aging adjustment factor α ranges from 0.05 to 0.2, dimensionless, and is determined according to the specific specifications of eMMC; the zero constant ε ranges from 10⁻⁻⁶. 6 Up to 10⁻ 8 The unit is volts (V), which is a fixed value; the reference decision voltage V ref The parameters for determining health status vary depending on the characteristics of the flash memory in the storage device. The typical range for the safety margin threshold β is 0.15 to 0.25V, serving as the lower limit for determining a "stable" state; the typical range for the flip-flop warning threshold γ is 0.08 to 0.12V, serving as the upper limit for determining a "flipped" state; and the normal voltage lower limit V... low and normal voltage upper limit V high The values ​​are determined based on the specific characteristics of the equipment, and different eMMC models have different values. The data structure of the critical bit backup table is as follows: The physical block address field is a 32-bit unsigned integer used to record the physical address of the main data block, with an example value of 0x1000; the bit offset field is a 16-bit unsigned integer used to record the specific position of the bit in the data block, with an example value of 0x00A1; the backup value field is a 1-bit binary field that stores the correct value of the bit (0 or 1), with an example value of 1; the health status field is a 2-bit enumeration value, where 00 indicates stable, 01 indicates warning, and 10 indicates flipped, with an example value of 01; the timestamp field is a 32-bit unsigned integer that records the time of the last check of this bit, with an example value of 0x5A3B; and the voltage history field is a 16-bit compressed data field that stores the encoding of the most recent voltage measurements, with an example value of 0x0F2A. To verify the technical effectiveness of this invention, multiple comparative experiments were conducted. In the data retention capability test, the test conditions were a 1TB TLCeMMC storage device. After 5000 P / E cycles, a long-term data retention test was performed at 55℃. The results showed that after 3 months of storage, the uncorrectable error rate (UBER) of the traditional ECC solution, the block migration solution, and the solution of this invention were all 1E-13, with no significant difference. After 6 months of storage, the UBER of the traditional ECC solution rose to 1E-12, while the block migration solution and the solution of this invention remained at 1E-13, with the solution of this invention showing a 10-fold improvement over the traditional ECC solution. After 12 months of storage, the UBER of the traditional ECC solution rose sharply to 1E-10, the block migration solution was 1E-12, and the solution of this invention remained at 1E-13, showing a 1000-fold improvement over the traditional ECC solution. After 24 months of storage, the UBER of the traditional ECC solution was 1E-8, the block migration solution was 1E-11, and the solution of this invention was 1E-12, showing a 10-fold improvement over the traditional ECC solution. In the write amplification factor test, the test load was a mixed read / write workload (70% read operations, 30% write operations), the data hot / cold ratio was 8:2, and the test time was 5000 hours. The results showed that the theoretical write amplification (WA) of the traditional ECC scheme was 1.0, the measured WA was 1.05, and the standard deviation was 0.02; the theoretical WA of the block migration scheme was 1.2 to 2.0, the measured WA was 1.8, and the standard deviation was 0.35; the theoretical WA of the scheme of this invention was 0.001, the measured WA was 0.005, and the standard deviation was 0.001. The write amplification factor is much lower than that of the existing schemes, showing significant advantages. The temperature compensation coefficient κ was determined through accelerated testing under different temperature environments. The test results show that: within the temperature range of -25℃ to 0℃, the κ value is -0.002, indicating enhanced stability of the storage medium within this temperature range, thus reducing the adjustment range of the vulnerability threshold; within the room temperature range of 0℃ to 45℃, the κ value is 0.000, requiring no additional adjustment based on room temperature; within the range of 45℃ to 85℃, the κ value is 0.003, indicating that high temperatures accelerate storage medium degradation, necessitating a larger adjustment range for the vulnerability threshold; within the extreme temperature range of 85℃ to 105℃, the κ value is 0.008, indicating extremely rapid degradation of the storage medium within this temperature range, requiring further increases in adjustment range to ensure no vulnerable bits are missed. The temperature compensation formula is θ = θbase × (1 + κ × (T - 25)), where T is the current ambient temperature and 25 is the room temperature baseline (unit: ℃). refer to Figure 3 According to an embodiment of this application, an eMMC data protection system based on critical bit backup and active recovery includes an application layer, i.e., a host system, an eMMC controller layer, and the aforementioned NAND flash physical layer, wherein the eMMC controller layer executes the eMMC data protection method based on critical bit backup and active recovery described in the foregoing embodiments.

[0030] Specifically, the eMMC controller layer includes: An identification module is configured to identify vulnerable bits prone to bit flipping after data is written to the main data storage area, and to calculate the vulnerability of the vulnerable bits; a backup storage unit is located in the high-reliability storage area and is used to store backup information of the vulnerable bits, including physical address, bit offset, backup value, and health status; a monitoring and recovery unit is configured to periodically scan the backup storage unit, assess its health status based on the current voltage of the vulnerable bits, and perform a recovery operation on the vulnerable bits using the backup value when the health status is abnormal.

[0031] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A method for ensuring data security in eMMC based on critical bit backup and active recovery, used in NAND flash memory, wherein the NAND flash memory includes a main data storage area and a high-reliability storage area, characterized in that, The method includes: After the data is written to the main data storage area, vulnerable bits that are prone to bit flipping are identified; The backup information of the vulnerable bits is stored in the high-reliability storage area, and the backup information includes at least the physical address, bit offset, backup value and health status. The backup information is periodically scanned, and its health status is assessed based on the current voltage of the vulnerable bits. When the health status is abnormal, the backup value is used to perform a recovery operation on the vulnerable bit.

2. The eMMC data assurance method based on critical bit backup and active recovery according to claim 1, characterized in that, The identification of vulnerable bits includes: Calculate the voltage margin of the bit, where the voltage margin is the absolute value of the difference between the read voltage of the bit and the reference voltage threshold. The vulnerability index of the bit is calculated based on the voltage margin. The vulnerability index is compared with a preset vulnerability threshold. When the vulnerability index is greater than the vulnerability threshold, the bit is identified as a vulnerable bit.

3. The eMMC data assurance method based on critical bit backup and active recovery according to claim 2, characterized in that, The calculation of the voltage margin M includes: Among them, V read V is the read voltage for a bit. f Reference voltage threshold; Vulnerability index of this bit: F = 1 / (M + ϵ) Where ϵ is a small constant used to avoid division by zero errors; θ is the fragility threshold. When F>θ, the bit is marked as a fragility bit.

4. The eMMC data assurance method based on critical bit backup and active recovery according to claim 2, characterized in that, The vulnerability threshold is dynamically adjusted based on the current P / E cycle number of the NAND flash memory.

5. The eMMC data assurance method based on critical bit backup and active recovery according to claim 4, characterized in that, The formula for adjusting the vulnerability threshold θ is: Where, θ base It is the basic threshold, C PE It is the current P / E cycle number, C max It is the maximum rated P / E cycle number, and α is the adjustment factor.

6. The eMMC data assurance method based on critical bit backup and active recovery according to claim 2, characterized in that, The assessment of the health status based on the current voltage of the vulnerable bit includes: Calculate the voltage deviation of the current voltage relative to the normal voltage range; The voltage deviation is compared with a preset safety margin threshold and a flip warning threshold to determine the health status.

7. The eMMC data assurance method based on critical bit backup and active recovery according to claim 6, characterized in that, The health status includes: In a stable state, when the voltage deviation is greater than or equal to the safety margin threshold; Warning status occurs when the voltage deviation is less than the safety margin threshold and greater than or equal to the flip warning threshold. The flipped state occurs when the voltage deviation is less than the flip warning threshold and the current read value of the bit does not match the backup value.

8. The eMMC data assurance method based on critical bit backup and active recovery according to claim 1, characterized in that, The periodic scan and recovery operations are performed during the storage system's idle periods.

9. An eMMC data assurance system based on critical bit backup and active recovery, comprising an application layer, an eMMC controller layer, and a NAND flash physical layer, characterized in that, The eMMC controller layer is used to execute the eMMC data protection method based on critical bit backup and active recovery as described in any one of claims 1 to 8.

10. The eMMC data assurance system based on critical bit backup and active recovery according to claim 9, characterized in that: The eMMC controller layer includes: The identification module is configured to identify vulnerable bits that are prone to bit flipping. A backup storage unit is provided in the high-reliability storage area for storing backup information of the vulnerable bits; The monitoring and recovery unit is configured to periodically scan the backup storage unit, assess the health status of the vulnerable bits, and perform recovery operations when the health status is abnormal.

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