Non-similar flight control computer with AI processing capability

Abstract

The invention provides a dissimilar flight control computer with AI processing capability, which comprises a heterogeneous power switching circuit, a heterogeneous bus, an isomorphic dual-redundancy processing channel, a heterogeneous AI processing channel and an external interface unit, and is characterized in that the isomorphic dual-redundancy processing channel comprises two isomorphic processors, and the heterogeneous AI processing channel comprises an AI processor; the isomorphic dual-redundancy processing channel and the heterogeneous AI processing channel are provided with a flight control algorithm, and the heterogeneous AI processing channel is also provided with a fault processing model; the isomorphic dual-redundancy processing channel, the heterogeneous AI processing channel and the external interface unit are all powered by the heterogeneous power conversion circuit; data interaction and information comparison are carried out between the two isomorphic processors and the AI processor through heterogeneous buses; and the heterogeneous AI processing channel supervises the isomorphic dual-redundancy processing channel. According to the invention, the common-mode fault probability and task reliability of the flight control computer can be effectively reduced, so that the system has better universality.

Description

Technical Field

[0001] This invention relates to the field of flight control electronics technology, and in particular to a dissimilar flight control computer with AI processing capabilities. Background Technology

[0002] As the core control component of an aircraft, the flight control computer is the "brain" that ensures flight safety and achieves precise control. Its reliability, fault tolerance, and computing performance directly determine the mission execution efficiency and survivability of the aircraft. Especially in low-altitude flight scenarios such as eVTOL and urban air traffic (UAM), the complex airspace environment, frequent attitude adjustments, and stringent safety and compliance requirements place higher demands on the performance of the flight control computer.

[0003] To meet high reliability requirements, traditional flight control computers generally employ redundancy technology. By setting up dual-redundancy, triple-redundancy, or even quadruple-redundancy architectures, redundant resources are used to shield the impact of single failures, ensuring that "single-point failures do not jeopardize flight safety." For example, some commercial airliners' flight control systems use a triple-redundancy architecture, employing three independent computing channels to perform parallel calculations and compare results to eliminate random faults. However, existing redundancy technologies mostly focus on "similar redundancy" designs, where each redundancy channel uses the same processor model, a consistent operating system, and homogenized bus interfaces, differing only in the number of interfaces and peripheral circuit details. While this design reduces the complexity of hardware selection and software development, it carries a significant risk of common-mode failures—when encountering common defects (such as processor chip design flaws, operating system underlying logic errors, or bus protocol compatibility issues), all similar redundancy channels may fail simultaneously, leading to the overall paralysis of the flight control system. This problem is particularly fatal in the field of low-altitude aircraft with high safety standards, and once it occurs, it can directly lead to catastrophic consequences such as crashes.

[0004] At the data interaction level, traditional flight control computers primarily rely on low-speed buses such as SPI (Serial Peripheral Interface), UART (Universal Asynchronous Receiver / Transmitter), and ARINC659 for redundant data transmission. The transmission rate of the SPI bus is typically no more than 100 Mbps, and the UART bus rate is even limited to the Mbps level. While the ARINC659 bus is a standard airborne bus, its single-channel bandwidth is only sufficient for basic control command transmission, making it difficult to meet the high bandwidth requirements of modern flight control systems involving multi-sensor data fusion and complex control law calculations. This bandwidth limitation directly leads to increased data transmission latency. For example, in traditional architectures, the latency from attitude calculation data acquisition to command output can reach 50-100 ms. This severely impacts the timeliness of control cycle tasks, causing lag in aircraft attitude response, especially at low altitudes and low speeds, increasing the risk of collisions with obstacles due to control delays. Furthermore, the shared bus design pattern leads to multiple channels competing for bus resources, further exacerbating data congestion and reducing flight quality.

[0005] With the increasing penetration of artificial intelligence (AI) technology into the aviation field, the demand for computing power in flight control systems is growing exponentially. Modern aircraft flight control is no longer limited to traditional PID control but integrates intelligent algorithms such as path planning, environmental perception, and adaptive fault tolerance. These algorithms often involve large-scale matrix operations and deep learning model inference, requiring powerful parallel computing capabilities. However, traditional flight control processors mostly use general-purpose MCUs or ordinary FPGAs, whose core processing is primarily serial, with computing power generally limited to the GFLOPS level, making it difficult to meet the real-time operation requirements of AI algorithms. For example, the inference latency of a deep learning-based obstacle recognition model on a traditional processor may exceed 200ms, failing to provide timely environmental decision support for flight control and hindering the practical application of intelligent algorithms.

[0006] Furthermore, existing flight control systems have significant shortcomings in their fault handling capabilities. Traditional fault handling relies heavily on preset logical judgment rules, which can only identify known simple faults (such as sensor disconnection or abnormal power supply voltage). For complex intermittent faults or multi-component interconnected faults (such as control command deviations caused by bus transmission errors or calculation errors due to processor core arithmetic unit degradation), effective identification and handling methods are lacking. Simultaneously, due to the lack of an independent fault handling unit, fault detection and control calculations share the same computing channel, not only consuming core control resources but also potentially causing secondary faults due to mutual interference between fault handling logic and control logic. For example, when a redundancy channel experiences a calculation anomaly, the main channel must be paused for fault diagnosis, a process that interrupts control commands and affects flight stability.

[0007] While some existing technologies attempt to optimize system reliability through heterogeneous redundancy design, such as using processors from different manufacturers to build redundancy channels, these solutions mostly focus on heterogeneity in the single dimension of processors, failing to cover critical aspects such as power supply, bus transmission, and control law design. For example, a patent proposes a heterogeneous redundancy flight control computer that only uses different architecture chips in processor selection, but the power system still uses a unified power supply, and the bus still uses a single ARINC429 bus. When the power module experiences common-mode failure or bus protocol compatibility issues, the system still faces the risk of failure. Furthermore, such solutions lack an integrated independent AI processing unit, making it impossible to achieve intelligent fault diagnosis and real-time reconfiguration, and also difficult to support the operation of intelligent flight algorithms, thus failing to meet the dual requirements of high safety and high intelligence for low-altitude aircraft.

[0008] In summary, existing flight control computers suffer from four major pain points: high risk of common-mode failures due to similar redundancy architectures, low data interaction efficiency caused by low-speed buses, inability of traditional processors to adapt to AI algorithms, and insufficient fault handling capabilities that easily interfere with core control tasks. These problems are further amplified in low-altitude flight scenarios, severely hindering the commercialization of new aircraft such as eVTOL and UAM. Therefore, there is an urgent need for a multi-dimensional heterogeneous, non-similar flight control computer with integrated AI processing capabilities. This requires innovative design across the entire chain, including hardware architecture, software systems, data transmission, and fault handling, to reduce the risk of common-mode failures while balancing computational performance and scenario adaptability, providing a highly reliable and intelligent control solution for new aircraft.

[0009] Therefore, it is necessary to research a dissimilar flight control computer with AI processing capabilities to address the shortcomings of existing technologies and to solve or mitigate one or more of the aforementioned problems. Summary of the Invention

[0010] In view of this, the present invention provides a dissimilar flight control computer with AI processing capabilities, which can effectively reduce the probability of common mode failure and mission reliability of flight control computers, making the system more versatile and expandable to application scenarios such as multi-electric / hybrid aircraft and urban air mobility (UAM) platforms.

[0011] On one hand, the present invention provides a dissimilar flight control computer based on an AI processor, the dissimilar flight control computer comprising: a heterogeneous power conversion circuit, a heterogeneous bus, a homogeneous dual-redundant processing channel, a heterogeneous AI processing channel, and an external interface unit. The homogeneous dual-redundant processing channel includes two homogeneous processors, and the heterogeneous AI processing channel includes one AI processor. The homogeneous dual-redundant processing channel and the heterogeneous AI processing channel are equipped with flight control algorithms, and the heterogeneous AI processing channel is also equipped with a fault handling model; The homogeneous dual-redundant processing channel, the heterogeneous AI processing channel, and the external interface unit are all powered by a heterogeneous power conversion circuit. The homogeneous dual-redundant processing channel and the heterogeneous AI processing channel output flight control commands through the external interface unit; The two homogeneous processors and the AI ​​processor interact and compare data through a heterogeneous bus; the heterogeneous AI processing channel supervises the homogeneous dual-redundant processing channel.

[0012] In addition to the aspects and any possible implementations described above, a further implementation of the heterogeneous power conversion circuit is provided, comprising: a channel power conversion circuit and a power path management module, wherein the channel power conversion circuit is connected to the power path management module; The power path management module supports dual power inputs; The channel power conversion circuit simultaneously supplies power to the homogeneous dual-redundant processing channel, the heterogeneous AI processing channel, and the external interface unit.

[0013] In addition to the aspects described above and any possible implementation, a further implementation is provided in which the channel power conversion circuit uses different devices to power the homogeneous dual-redundant processing channel; the channel power conversion circuit uses different power systems to power the heterogeneous AI processing channel; and the channel power conversion circuit uses different devices to power the external interface unit.

[0014] In addition to the aspects described above and any possible implementation, a further implementation is provided in which the two isomorphic processors are a processor with an ARM core and an FPGA processor, respectively; the two isomorphic processors are equipped with a real-time embedded operating system, and the isomorphic dual-redundant processing channel obtains task priority scheduling from the real-time embedded operating system; the flight control algorithm is run according to the task priority scheduling.

[0015] In addition to the aspects described above and any possible implementation, a further implementation is provided in which the AI ​​processor is a processor module with GPU parallel computing capabilities; the processor module with GPU parallel computing capabilities is equipped with a real-time operating system; the heterogeneous AI processing channel obtains task deadline schedules from the real-time operating system; runs the fault handling model according to the task deadline schedule; obtains fault monitoring results from the fault handling model; and generates a fault handling strategy based on the fault monitoring results.

[0016] In accordance with the aspects described above and any possible implementation, a further implementation is provided in which the heterogeneous bus includes a high-speed serial bus and a low-speed parallel bus. The high-speed serial bus simultaneously connects two homogeneous processors and an AI processor, enabling real-time data interaction between the homogeneous dual-redundant processing channel and the heterogeneous AI processing channel. The low-speed parallel bus simultaneously connects two homogeneous processors and an AI processor, enabling critical data transmission between the homogeneous dual-redundant processing channel and the heterogeneous AI processing channel. The high-speed serial bus is used to acquire real-time data, and based on the real-time data, critical information is transmitted through the low-speed parallel bus. Fault degradation data is acquired from the low-speed parallel bus.

[0017] In addition to the aspects described above and any possible implementation, a further implementation is provided in which the AI ​​processor has a complete flight control algorithm; one of the two isomorphic processors has a complete flight control algorithm; the other has a simplified flight control algorithm; control output is obtained from the complete flight control algorithm; the consistency of the three processor channels is compared according to the control output; if the comparison is inconsistent, a degraded output is obtained from the simplified flight control algorithm.

[0018] In addition to the aspects and any possible implementations described above, a further implementation is provided in which the two homogeneous processors and the AI ​​processor interact and compare data via a heterogeneous bus. Specifically, this involves: obtaining the output of the homogeneous dual-redundant processing channel from the heterogeneous bus; obtaining the output of the fault handling model from the heterogeneous AI processing channel; comparing the output of the homogeneous dual-redundant processing channel with the output of the fault handling model; confirming the flight control output if the comparison matches; and obtaining a fault degradation decision from the fault handling model if the comparison does not match.

[0019] In addition to the aspects described above and any possible implementation, a further implementation is provided in which the Ethernet of the two homogeneous processors is implemented as a high-speed serial bus by setting up FPGA IP cores and PHY chips, and the Ethernet of the heterogeneous AI processor is implemented as a high-speed serial bus by setting up PCIe switching chips; the three processors are implemented as a low-speed parallel bus through ARINC825 bus.

[0020] In addition to the aspects described above and any possible implementations, a further implementation is provided in which the flight control system obtains Ethernet packets from the FPGA IP core; transmits the Ethernet packets according to the PCIe switching chip; and obtains priority messages from the ARINC825 bus.

[0021] Compared with the prior art, the present invention can achieve the following technical effects: 1. This invention adopts a heterogeneous and independent design in multiple technical channels such as processor selection, power supply, communication bus, and control law setting, to avoid common mode failures in flight control computers and is suitable for the use requirements of high-safety flight controllers; 2. This invention can effectively reduce the probability of common-mode failure and mission reliability of flight control computers, making the system more versatile and expandable to application scenarios such as multi-electric / hybrid aircraft and urban air mobility (UAM) platforms.

[0022] Of course, any product implementing this invention does not necessarily need to achieve all of the technical effects described above at the same time. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a power distribution architecture for a dissimilar flight control computer provided in one embodiment of the present invention, showing dual busbar inputs, three independent power conversion channels, and the power supply object; Figure 2 This is a schematic diagram of information transmission between dissimilar flight control processor channels provided in an embodiment of the present invention, showing the topology of Ethernet (pair-to-pair connection) and ARINC825 bus (bus type); Figure 3 This is a schematic diagram of the control laws for the flight control processor channels provided in one embodiment of the present invention, showing the complete / simplified control laws and fault handling models for the three channels respectively; Figure 4 This is a schematic diagram of a heterogeneous three-channel system provided in one embodiment of the present invention, illustrating the hardware composition and interaction relationship of a homogeneous dual-redundant channel and an AI channel; Figure 5 This is a schematic diagram of the power path management module provided in one embodiment of the present invention, showing the circuit connection of the Pi2121 chip, current limiting resistor, and filter capacitor; Figure 6 This is a schematic diagram of a heterogeneous power conversion circuit architecture provided in one embodiment of the present invention, with the device models and output voltages of the three power conversion channels marked. Detailed Implementation

[0025] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0026] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0027] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0028] The following detailed description of the AI ​​processor-based dissimilar flight control computer of the present invention, with reference to specific embodiments, will make the objectives, technical solutions, and advantages of the present invention clearer. The embodiments of the present invention provide an AI processor-based dissimilar flight control computer, aiming to improve the reliability and fault tolerance of the flight control system through the combination of homogeneous dual-redundant processing channels and heterogeneous AI processing channels, as well as heterogeneous power supply and bus design. The following will describe the system architecture, functional implementation, and specific module implementation methods one by one.

[0029] In one embodiment, the flight control computer provided by this invention includes multiple core components, and the overall design adopts a dissimilar architecture to avoid system failure due to a single hardware or software failure. Specifically, the flight control computer includes a homogeneous dual-redundant processing channel, a heterogeneous AI processing channel, and an external interface unit. The homogeneous dual-redundant processing channel consists of two homogeneous processors, and the heterogeneous AI processing channel consists of one AI processor. This design achieves functional redundancy and fault isolation through different types of processor channels, ensuring that the system can still maintain basic flight control functions even if one channel fails. The implementation and specific functions of each component will be described in detail below.

[0030] Step S1 involves constructing the hardware architecture of the flight control computer, including a homogeneous dual-redundant processing channel, a heterogeneous AI processing channel, and an external interface unit. The homogeneous dual-redundant processing channel consists of two identical processors using the same hardware architecture and manufacturing process to ensure consistent operating logic and performance. This design achieves high reliability through redundancy mechanisms; for example, if one processor fails, the other can take over the task, ensuring uninterrupted system operation. In contrast, the heterogeneous AI processing channel employs a completely different hardware architecture, with its core being an AI processor designed specifically for high-performance computing. This processor excels at handling complex parallel computing tasks and is suitable for running fault diagnosis and decision-making models that require large amounts of data processing. The external interface unit is responsible for data interaction between the system and external devices, such as communicating with flight sensors, actuators, and the ground control station, ensuring that the flight control computer can acquire flight data in real time and output control commands.

[0031] Specifically, in the implementation of a homogeneous dual-redundant processing channel, the two homogeneous processors can be high-performance embedded processors based on ARM cores, while also integrating a field-programmable gate array (FPGA) module. This combination satisfies real-time computing requirements and enables hardware acceleration through programmable logic. For example, in flight control tasks, the ARM core is responsible for running control algorithms, while the FPGA module can accelerate signal processing tasks, such as filtering and preprocessing sensor data. The two processors synchronize data through an internal high-speed communication interface, ensuring consistency when running the same tasks. In practical applications, this design can effectively address the risks associated with hardware aging or transient failures. For instance, if one processor experiences performance degradation due to overheating, the other processor can immediately take over the task, preventing system interruption.

[0032] Furthermore, the hardware design of heterogeneous AI processing channels focuses on high-performance computing capabilities. AI processors can employ embedded modules based on graphics processing unit (GPU) architectures. These modules possess powerful parallel computing capabilities, enabling them to process large amounts of data in a short time. For example, during flight, the AI ​​processor can analyze data streams from multiple sensors in real time, quickly identify potential failure modes, and generate corresponding processing strategies. Unlike homogeneous processors, the hardware architecture and instruction set of the AI ​​processor are completely independent of the homogeneous channel. This heterogeneous design effectively avoids common-mode failures caused by design flaws or manufacturing problems. For instance, if a homogeneous processor fails due to a manufacturing defect in a specific batch of chips, the AI ​​processor, employing a different manufacturing process and design logic, is unaffected and can still maintain system functionality.

[0033] In one possible implementation, the external interface unit is designed to ensure efficient communication between the flight control computer and external devices. This unit can integrate multiple communication interfaces, such as serial, parallel, and network interfaces, to adapt to different external device requirements. For example, when communicating with flight sensors, a high-frequency data stream can be acquired via a serial interface, while large volumes of data can be transmitted via a network interface when communicating with the ground control station. The external interface unit also possesses a degree of fault tolerance; for instance, if one communication interface fails, it can automatically switch to a backup interface to ensure uninterrupted data transmission. This design is particularly important in complex flight environments, effectively addressing challenges posed by sensor failures or communication interference.

[0034] Step S2 involves embedding the flight control algorithm in both a homogeneous dual-redundant processing channel and a heterogeneous AI processing channel, while simultaneously incorporating a fault handling model within the heterogeneous AI processing channel. The flight control algorithm is the core functional module of the flight control computer, responsible for calculating control commands based on flight data to maintain the aircraft's stability and heading. Incorporating it across multiple processor channels enhances system reliability through redundancy. For example, in the homogeneous dual-redundant processing channel, two processors can each run the same control law algorithm, ensuring calculation accuracy through result comparison. The heterogeneous AI processing channel, on the other hand, can run more complex versions of the control law, leveraging its high-performance computing capabilities to optimize control effectiveness.

[0035] Specifically, in the isomorphic dual-redundant processing channel, the flight control algorithm can be implemented based on classical control algorithms, such as proportional-integral-derivative (PID) control. This method calculates the required control parameters by real-time monitoring of aircraft attitude, speed, and altitude, and outputs them to the actuators. In actual flight, for example, when the aircraft encounters crosswind interference, the control law adjusts the control surface deflection angle to maintain heading stability based on the yaw angle changes fed back by sensors. The two isomorphic processors run the same algorithm respectively and compare the calculation results. If the results are consistent, control commands are output; if they are inconsistent, a fault diagnosis mechanism is triggered to further identify the source of the problem.

[0036] Furthermore, in heterogeneous AI processing channels, the implementation of flight control algorithms can be combined with machine learning techniques, leveraging the high-performance computing capabilities of AI processors to optimize control performance. For example, a predictive model can be trained using historical flight data to predict the dynamic response of the aircraft in specific environments, and control parameters can be adjusted based on the prediction results. This method has significant advantages in complex flight scenarios; for instance, in high-altitude turbulent environments, the AI ​​processor can predict turbulence intensity based on real-time data and adjust control strategies in advance to avoid severe aircraft vibration. By setting different versions of control laws in different channels, the system can quickly switch to another channel's control law version when one channel fails, ensuring flight safety.

[0037] In one embodiment, the fault handling model embedded in the heterogeneous AI processing channels is a crucial component of the system's fault tolerance. This model leverages the powerful data processing capabilities of the AI ​​processor to analyze data from various channels and external devices in real time, identify potential fault modes, and generate corresponding processing strategies. For example, during flight, if abnormal fluctuations occur in sensor data, the fault handling model analyzes the fluctuation characteristics to determine whether it is caused by sensor hardware failure, communication interference, or environmental factors, and generates a processing plan based on the assessment results. If a sensor hardware failure is confirmed, the model will suggest switching to a backup sensor and adjusting the control law parameters to accommodate the missing data. This fault handling model significantly improves the system's adaptability to complex environments, preventing system failure due to a single point of failure.

[0038] Specifically, the fault handling model's operation can be divided into three stages: data acquisition, feature analysis, and decision generation. In the data acquisition stage, the model obtains real-time operational data from various processor channels and external interface units, including processor load, communication latency, and sensor readings. In the feature analysis stage, the model preprocesses and extracts features from the acquired data, such as identifying abnormal patterns through time series analysis. In the decision generation stage, the model generates fault handling strategies based on the analysis results, such as adjusting task allocation, switching to backup hardware, or reducing the system's operating level. This multi-stage approach enables intervention measures to be taken in the early stages of a fault, preventing further escalation.

[0039] In one possible implementation, the fault handling model can also dynamically adjust its analysis strategy according to different phases of the flight mission. For example, during takeoff and landing, due to the drastic changes in aircraft attitude, the model will increase its sensitivity to anomalies in sensor data and prioritize the analysis of data related to attitude control. During the cruise phase, the model will focus more on processor load and communication status to ensure long-term stable system operation. This dynamic adjustment strategy can optimize fault detection performance under different flight scenarios. For example, during a long-distance cruise mission, if the model detects a persistently high load on a certain homogeneous processor channel, it may trigger task reallocation, transferring some computational tasks to the AI ​​processor channel to avoid system failures caused by processor overload.

[0040] Step S3 involves configuring heterogeneous power conversion circuits to power the homogeneous dual-redundant processing channel, the heterogeneous AI processing channel, and the external interface unit. The power system is fundamental to the reliable operation of the flight control computer. Adopting a heterogeneous power conversion circuit design effectively prevents system-wide failure due to power supply malfunctions. The heterogeneous power conversion circuit provides independent power to each processor channel and interface unit through different power paths and conversion devices, ensuring that a failure in one power path or device will not affect the normal operation of other parts.

[0041] Specifically, the heterogeneous power conversion circuit design includes multiple independent modules, each responsible for powering a specific channel or unit. For example, the module powering the homogeneous dual-redundant processing channel can employ a switching power supply-based conversion circuit to provide a stable high-current output, meeting the processor's high-load operation requirements. The module powering the heterogeneous AI processing channel can use a linear power supply design to reduce electromagnetic interference and ensure signal integrity during high-performance computing. The power module for the external interface unit can adopt a hybrid design, ensuring power supply stability while also meeting low-power requirements.

[0042] Furthermore, the heterogeneous power conversion circuit also includes power path management functionality for monitoring and switching power inputs. For example, the system can connect to two independent power inputs, such as an onboard battery and an external power source, and the path management module monitors the voltage and current status of both power sources in real time. If the voltage of one power source drops below a safe threshold, the path management module automatically switches to the other power source to ensure uninterrupted power supply. In actual flight missions, such as when the battery gradually depletes during long-distance flights, the system can smoothly switch to the backup power source, avoiding control failures due to power interruptions.

[0043] In one embodiment, the heterogeneous power conversion circuit can also dynamically adjust power supply parameters according to the load characteristics of each channel. For example, when the AI ​​processor channel is running complex computing tasks, the power module will increase the output voltage and current to meet its high power consumption requirements. Conversely, during low-load operation, the power module will reduce the output power to decrease energy consumption and heat generation. This dynamic adjustment mechanism not only optimizes system energy efficiency but also extends hardware lifespan. For instance, during a high-intensity flight mission, the AI ​​processor needs to continuously run a fault handling model; the power module will adjust power supply parameters based on real-time load data to ensure stable processor operation while avoiding the risk of overheating.

[0044] Specifically, in the circuit design for powering homogeneous dual-redundant processing channels, the power conversion devices for the two processors can be different models or from different manufacturers to avoid common-mode failures caused by batch defects in components. For example, one processor can use a high-efficiency switching power supply chip from one brand, while the other processor uses a low-noise power supply chip from another brand. This heterogeneous device design ensures that the other processor can still operate normally even if one component fails. In practical applications, such as in high-altitude and low-temperature environments, one power supply chip may fail due to temperature adaptability issues, but because the other processor uses a different model of power supply chip, it is unaffected, and the system as a whole can still maintain its functionality.

[0045] In one possible implementation, the circuit design for powering heterogeneous AI processing channels prioritizes high power output and stability. Due to their high-performance computing characteristics, AI processors typically have high power consumption requirements. Therefore, their power conversion circuits can employ a multi-phase power supply design, using multiple parallel power phases to share the current load and ensure stable power supply. For example, when running complex fault handling models, AI processors may need to process large amounts of data streams in a short period. A multi-phase power supply design can effectively avoid voltage fluctuations, ensuring uninterrupted computing tasks. This design is particularly important in high-load flight scenarios, such as under complex weather conditions, where AI processors need to analyze data from multiple sensors in real time, and a stable power supply is crucial for their normal operation.

[0046] Furthermore, the power supply design for the external interface unit prioritizes low power consumption and interference immunity. Since the interface unit primarily handles data communication, its power consumption requirements are relatively low, but it is highly sensitive to electromagnetic interference. Therefore, its power conversion circuit can employ a low-noise linear power supply design to reduce the impact of electromagnetic interference on communication signals. For example, when communicating with high-frequency sensors, a linear power supply can provide stable, low-noise power, avoiding signal distortion and ensuring the accuracy of data transmission. In actual flight missions, such as in airport environments with strong electromagnetic interference, this power supply design can effectively improve the communication reliability of the interface unit.

[0047] It's worth noting that the implementation of heterogeneous power conversion circuits can be combined with fault isolation mechanisms to further enhance system reliability. For example, power modules can be connected via isolation devices to prevent the impact of a failure in one module on other modules. In practical applications, if a power module in a homogeneous processor channel experiences a short circuit leading to abnormal voltage, the isolation device will disconnect its electrical connection with other modules, ensuring that the power supply to the AI ​​processor channel and interface unit is unaffected. This fault isolation design can maintain system functionality to the greatest extent possible when a partial failure occurs in the power system.

[0048] In one embodiment, the heterogeneous power conversion circuit can also integrate self-diagnostic functions for real-time monitoring of the power module's operating status. For example, through built-in voltage and current sensors, the system can collect the output parameters of each module in real time and compare them with preset safety ranges. If the output parameters of a module exceed the safety range, the system will trigger an alarm and attempt to switch to the backup power path. This self-diagnostic function can take preventative measures before a power failure occurs, avoiding system failure due to power problems. For example, during a long-distance flight mission, if the system detects a continuous drop in the output voltage of a power module, it may switch to the backup path in advance to ensure stable power supply.

[0049] Specifically, the design of heterogeneous power conversion circuits can be customized according to the needs of flight missions. For example, in short-range, low-load missions, the output power of the power module can be reduced to decrease energy consumption; while in long-range, high-load missions, the output power can be increased to ensure high-performance operation of each channel. This flexible power supply strategy can optimize system performance under different flight scenarios. For example, in a short-range takeoff and landing mission, the system can reduce the power supply to the AI ​​processor channel to reduce unnecessary energy consumption, while in a long-range cruise mission, the power supply can be increased to ensure that the AI ​​processor can continuously run complex computing tasks.

[0050] In one possible implementation, the heterogeneous power conversion circuit can be combined with a redundancy backup mechanism to further enhance reliability. For example, by configuring each processor channel and interface unit with dual power inputs and dual conversion circuits, the backup circuit can immediately take over the power supply task when the main circuit fails. In actual flight, such as in high-altitude strong wind environments, the airborne power supply may experience momentary interruptions due to vibration or temperature changes. The dual-redundancy design can ensure uninterrupted power supply and maintain stable system operation. This redundancy backup mechanism can effectively cope with power challenges in extreme environments.

[0051] It should be noted that the implementation of heterogeneous power conversion circuits can be further optimized based on the specific needs of the hardware platform. For example, in small aircraft, a compact power module design can be used to reduce size and weight; while in large aircraft, a high-power module design can be used to meet higher computing demands. This application-scenario-optimized design approach can achieve optimal power supply performance in different types of flight missions. For instance, in small drone missions, a compact power module can effectively reduce system weight and improve flight endurance.

[0052] In step S4, the three processor channels interact and compare data via a heterogeneous bus. The heterogeneous bus design is a key component for achieving highly reliable data communication in the flight control computer. By combining a high-speed serial bus and a low-speed parallel bus, it separates real-time data interaction from critical information transmission, ensuring stability and fault tolerance under different communication requirements. The three processor channels—two homogeneous processors in the homogeneous dual-redundant processing channel and the heterogeneous AI processing channel—are interconnected through this heterogeneous bus to form a complete communication network. This network supports high-frequency real-time data exchange while ensuring reliable transmission of critical control information.

[0053] Specifically, heterogeneous buses include two types: high-speed serial buses and low-speed parallel buses. High-speed serial buses are primarily responsible for real-time data exchange between the three processor channels, such as the rapid transmission of raw sensor data, intermediate calculation results, and status monitoring information. This type of bus uses point-to-point or switched connections, enabling the transmission of large amounts of data in a short time to meet the real-time calculation requirements of flight control algorithms. Low-speed parallel buses, on the other hand, are used for the transmission of critical data, such as final control commands, fault status flags, and consistency comparison results. This type of bus emphasizes determinism and priority management in transmission, ensuring that critical information arrives at its destination preferentially under all circumstances.

[0054] In one embodiment, the high-speed serial bus can be implemented based on the Ethernet protocol, establishing connections between channels through different hardware implementations. The processors within the homogeneous dual-redundant processing channel utilize Ethernet intellectual property cores in a field-programmable gate array (FPGA) combined with a physical layer chip to achieve high-speed serial communication. This approach fully utilizes internal processor resources, reduces the number of external components, and provides flexible configuration capabilities. The heterogeneous AI processing channel achieves the same high-speed serial function through a high-speed switching chip interconnected with peripheral components. This switching chip is designed for high-bandwidth data transmission and can efficiently handle large parallel data streams from the graphics processing unit. The three processor channels are connected through these different implementations to form a unified real-time data interaction channel.

[0055] Furthermore, the implementation of the low-speed parallel bus can adopt bus standards widely used in the aviation field, such as extended protocols based on controller area networks or dedicated aviation buses. This bus connects three processor channels through a multi-master, multi-slave architecture, supporting a message priority arbitration mechanism to ensure that high-priority messages are transmitted first. For example, when a channel detects a potential fault and generates an emergency handling instruction, this instruction is assigned the highest priority and quickly broadcast to other channels via the low-speed parallel bus, avoiding delays in critical information caused by real-time data congestion.

[0056] In step S51, the high-speed serial bus connects the three processor channels for real-time data exchange between each other. In actual operation, the high-speed serial bus continuously transmits raw data collected by the flight sensors and intermediate results calculated within each channel. For example, one processor in the homogeneous dual-redundant processing channel sends the intermediate variables of the current attitude calculation to another homogeneous processor via the high-speed serial bus, and also to the heterogeneous AI processing channel. This pairwise connection ensures that each channel can obtain the real-time status of other channels in a timely manner, facilitating subsequent consistency comparison and fault monitoring.

[0057] Specifically, during communication on the high-speed serial bus, each channel periodically packages real-time data into standard-format data packets. These packets contain timestamps, data type identifiers, and verification information, and are transmitted to the target channel via a high-speed serial link. The receiving end parses the data packets and uses the data for local calculations or storage for subsequent comparisons. For example, when an aircraft performs rapid maneuvers, attitude sensors generate high-frequency data streams, which are distributed in real-time to the three channels via the high-speed serial bus, ensuring that the control law calculations for each channel are based on the same input foundation.

[0058] In one possible implementation, the high-speed serial bus also supports multicast functionality, allowing one channel to send the same data packet to two other channels simultaneously. This feature is particularly useful in sensor data distribution scenarios, reducing bandwidth consumption caused by redundant transmissions. For example, when the external interface unit receives new navigation data, the heterogeneous AI processing channel can multicast the data to both processors of the homogeneous dual-redundant processing channel at once, achieving efficient synchronization.

[0059] In step S52, a low-speed parallel bus connects the three processor channels for critical data transfer. This low-speed parallel bus is designed to transmit critical information with slightly lower real-time requirements but extremely high reliability requirements, such as final control output commands, channel status reports, and fault degradation flags. This bus uses broadcast communication, ensuring all channels receive the same information and guaranteeing complete consistency of critical decisions across the system.

[0060] Specifically, during critical data transmission, each channel manages messages according to a predefined priority queue. For example, the final control surface command generated by the flight control algorithm is marked as the highest priority and is immediately sent via a low-speed parallel bus once generated. Other channels, upon receiving this command, compare it with their local calculation results. If they match, the output is executed; otherwise, further fault handling procedures are triggered. This separation design avoids interference between real-time and critical data, improving overall communication reliability.

[0061] Step S53: Acquire real-time data from the high-speed serial bus. Each processor channel continuously monitors the high-speed serial bus through a dedicated receive buffer, parses and stores the incoming real-time data. This data includes sensor sample values, condition monitoring parameters, and intermediate calculation results from other channels, providing timely input for the local flight control algorithm and fault handling model.

[0062] In one embodiment, the real-time data acquisition process also includes an integrity check mechanism. When parsing data packets, the receiving end verifies the validity of the timestamp and the correctness of the checksum. If data anomalies are detected, such as a timestamp exceeding the expected range, the data packet is discarded and the anomaly event is recorded for subsequent fault analysis. This check mechanism can prevent erroneous data from entering the calculation process when transient interference occurs in the communication link.

[0063] Step S54: Key information is transmitted via a low-speed parallel bus based on real-time data. After completing local calculations and combining them with real-time data acquired from the high-speed serial bus, each channel generates key information, such as control output values ​​or consistency comparison results. This key information is then encapsulated into priority messages and sent to other channels via the low-speed parallel bus.

[0064] Specifically, when transmitting critical information, different priority markers are assigned based on the importance of the information. For example, control output commands under normal circumstances are assigned medium priority, while degraded commands detected when inconsistencies or faults are detected are assigned the highest priority. This priority management ensures that critical information can still reach its destination in a timely manner even when communication load is high.

[0065] Step S55: Obtain fault degradation data from the low-speed parallel bus. When a channel detects a severe inconsistency or internal fault, fault degradation data is generated, such as simplified control mode switching instructions or task reassignment instructions. This data is broadcast to all channels via the low-speed parallel bus to ensure the system quickly enters a safe state.

[0066] In one possible implementation, the acquisition of fault degradation data also includes an acknowledgment mechanism. Upon receiving a degradation command, the receiving channel sends an acknowledgment message back to the initiating channel. The degradation operation only officially takes effect after acknowledgment from a majority of channels. This mechanism avoids unnecessary degradation caused by misjudgment from a single channel, thus improving system stability.

[0067] Step S5: The heterogeneous AI processing channel supervises the homogeneous dual-redundant processing channel. Utilizing its unique hardware architecture and established fault handling model, the heterogeneous AI processing channel continuously monitors the operational status and computational results of the homogeneous dual-redundant processing channel. This supervision mechanism is the core of the system's fault tolerance capability, achieving fault detection and intervention through a heterogeneous path independent of the homogeneous channel.

[0068] Specifically, the monitoring process includes real-time result comparison, behavior pattern analysis, and anomaly intervention. The heterogeneous AI processing channel continuously acquires output data from the homogeneous dual-redundant processing channel from the heterogeneous bus and compares it with its own calculation results. If a deviation exceeds a preset threshold, in-depth analysis is triggered to determine whether the homogeneous channel is faulty.

[0069] In one embodiment, the monitoring mechanism also includes periodic health checks. The heterogeneous AI processing channel periodically sends test data packets to the homogeneous dual-redundant processing channel, requesting a specific response. If the response times out or contains errors, the corresponding channel is deemed to have a potential problem. This proactive checking method can detect potential issues before they manifest.

[0070] Furthermore, when the monitoring detects inconsistencies in the comparisons within the homogeneous dual-redundant processing channel, the heterogeneous AI processing channel can intervene in the decision-making process. For example, if two homogeneous processors output different results, the heterogeneous AI processing channel will determine which result is more credible based on its own calculation results and historical data, and guide the system to adopt that result or enter a degraded mode.

[0071] Step S61: The heterogeneous AI processing channel is equipped with a complete flight control algorithm. This complete flight control algorithm includes control algorithms and parameters for all normal flight modes, enabling independent implementation of complete flight control functions. This configuration ensures that the system can still maintain basic control capabilities even if the homogeneous dual-redundant processing channel completely fails.

[0072] Specifically, the implementation of a complete flight control algorithm leverages the high-performance computing resources of AI processors to support more complex control strategies. For example, an adaptive control module can be integrated to dynamically adjust gain parameters based on real-time flight conditions, improving control accuracy in complex environments.

[0073] Step S62: One of the homogeneous dual-redundant processing channels is equipped with a complete flight control algorithm. Of the two homogeneous processors, one runs the same complete version as the heterogeneous AI processing channel, ensuring that the system has multiple redundant computing capabilities under normal circumstances.

[0074] In one implementation, the complete flight control algorithm maintains the same algorithmic logic as the heterogeneous channel version, but the implementation details may be slightly adjusted due to differences in processor architecture. This design facilitates result comparison while fully utilizing the advantages of each hardware component.

[0075] Step S63: Another isomorphic dual-redundant processing channel is equipped with a simplified flight control algorithm. The simplified flight control algorithm only includes core stabilization functions, such as basic attitude maintenance and altitude control, significantly reducing the computational load and making it suitable as a backup solution in case of failure.

[0076] Specifically, the simplified flight control algorithm omits some advanced functional modules, such as optimized track tracking or complex maneuver control, thereby reducing resource consumption and improving operational determinism. In degraded mode, this version can ensure the aircraft's safe return or maintain basic stability.

[0077] Step S64: Obtain control output from the complete flight control algorithm. Under normal operating conditions, the system preferentially uses the calculation results of the complete flight control algorithm as the final control output. These results are sent to the actuators after being compared and confirmed through multiple channels.

[0078] In one possible implementation, the acquisition of control output also includes a weighted fusion mechanism. Based on the historical reliability records of each channel, the outputs of different channels are weighted and averaged to further improve output accuracy.

[0079] Step S65: Compare the consistency of the three processor channels based on the control output. Each channel exchanges its local complete or simplified control output via a heterogeneous bus and performs a multi-party comparison. The comparison process uses a majority voting principle; if at least two channels' results are consistent, the output is considered valid.

[0080] Specifically, consistency comparison includes numerical comparison and trend analysis. For example, it involves not only comparing current output values ​​but also analyzing whether the rate of change in the output is reasonable. If only the numerical values ​​are consistent but the trend is abnormal, further review will be triggered.

[0081] Step S66: If the comparison is inconsistent, a downgraded output is obtained from the simplified flight control algorithm. When the outputs of the three channels cannot reach an agreement, the system automatically switches to the output of the simplified flight control algorithm to ensure that the aircraft enters a safe and controllable state.

[0082] In one embodiment, the acquisition of the degraded output is accompanied by a notification mechanism. A degraded status report is sent to the pilot or ground station via an external interface unit, facilitating manual intervention. This approach is particularly suitable for manned aircraft.

[0083] Step S71: Obtain the output of the homogeneous dual-redundant processing channel from the heterogeneous bus. The heterogeneous AI processing channel continuously monitors the heterogeneous bus, collecting control outputs and status information from the two homogeneous processors to prepare the data foundation for subsequent comparison.

[0084] Specifically, the acquisition process adopts a subscription model, only receiving predefined key message types to avoid unnecessary data load.

[0085] Step S72: Obtain the fault handling model output from the heterogeneous AI processing channel. After analyzing various input data, the fault handling model generates supervisory opinions or fault determination results, which are also used in the overall comparison.

[0086] In one possible implementation, the fault handling model output includes a confidence score, indicating the reliability of its judgment of the current state. Higher confidence outputs have higher weighting in the comparison.

[0087] Step S73: Compare the output of the fault handling model with the output of the isomorphic dual-redundancy processing channel. Compare the supervision results of the fault handling model with the actual output of the isomorphic channel to determine whether there are any deviations or abnormal behaviors.

[0088] Specifically, the comparison process is divided into a numerical layer and a logical layer. The numerical layer compares specific control variables, while the logical layer checks whether the control decisions are reasonable. For example, even if the values ​​are close, an incorrect control direction will still be considered inconsistent.

[0089] Step S74: If the comparison matches, the flight control output is confirmed. When the fault handling model confirms that the isomorphic channel output is normal, the system officially adopts the output and sends it to the actuator.

[0090] In one implementation, the verification process also includes logging for post-event analysis and system optimization.

[0091] Step S75: If the comparison is inconsistent, obtain the fault degradation decision from the fault handling model. After detecting the inconsistency, the fault handling model generates a specific degradation strategy, such as isolating the fault channel or switching the control mode.

[0092] Specifically, downgrade decisions may include multiple levels, ranging from minor task reassignment to a complete simplification mode switch, dynamically selected based on the severity of inconsistencies.

[0093] In step S81, the homogeneous processor channel Ethernet implements a high-speed serial bus through a field-programmable gate array (FPGA) intellectual property core and a physical layer chip. This implementation fully utilizes the processor's integrated resources, providing flexible and configurable high-speed communication capabilities.

[0094] In one embodiment, the intellectual property core supports gigabit Ethernet speeds, which can meet the real-time data transmission requirements of flight control.

[0095] In step S82, the heterogeneous AI processing channel Ethernet realizes a high-speed serial bus through the interconnection of peripheral components and fast switching chips. This chip is designed for high-bandwidth applications and can efficiently process the data stream generated by the graphics processing unit.

[0096] Specifically, the switching chip supports multi-port configuration, enabling direct connection to two homogeneous processors.

[0097] In step S83, the three processor channels are implemented as a low-speed parallel bus via a dedicated avionics bus. This bus standard has mature applications in the aerospace field and supports deterministic transmission and priority management.

[0098] In one possible implementation, the bus is configured as a dual-redundant physical link to further improve reliability.

[0099] Step S84: Obtain Ethernet packets from the field-programmable gate array (FPGA) intellectual property core. The homogeneous processor directly accesses the intellectual property core buffer through internal logic to efficiently extract incoming packets.

[0100] Step S85: Ethernet data packets are transmitted via a high-speed switching chip based on the peripheral component interconnection. The heterogeneous AI processing channel utilizes the routing function of the switching chip to achieve fast forwarding of data packets.

[0101] Step S86: Obtain priority messages from the dedicated aviation bus. Each channel parses the priority field through the bus controller to ensure that high-priority messages are processed first.

[0102] In one implementation, the acquisition of priority messages also includes a filtering mechanism that processes only message types relevant to this channel, reducing the processing burden.

[0103] It should be noted that the aforementioned heterogeneous bus design achieves non-dissimilar redundancy at the communication layer by combining high-speed and low-speed, serial and parallel approaches, and employing different hardware implementation paths. This design can automatically rely on other paths to maintain necessary data interaction when one communication path fails, ensuring the flight control computer's continuous operation under extreme conditions.

[0104] Furthermore, in actual flight missions, such as under complex weather conditions, high-speed serial buses may experience temporary packet loss due to electromagnetic interference, but low-speed parallel buses, due to their anti-interference design, can still reliably transmit critical control commands, thereby maintaining the basic functions of the system. The supervision mechanism of the heterogeneous AI processing channel plays a crucial role at this time, quickly identifying communication anomalies and triggering corresponding processing strategies.

[0105] Specifically, the entire data interaction and information comparison process forms a closed-loop monitoring system. The homogeneous dual-redundant processing channel provides a traditional and reliable computing foundation, the heterogeneous AI processing channel provides advanced monitoring and backup capabilities, and the heterogeneous bus provides diversified communication guarantees. The three work together to significantly improve the fault tolerance and mission reliability of the flight control computer.

[0106] In one embodiment, when the aircraft is performing a long-distance cruise mission, the system continuously exchanges status information through a heterogeneous bus. The heterogeneous AI processing channel periodically analyzes trends. Once it detects that the performance of the homogeneous channel is slowly declining, it will suggest load balancing in advance, transferring some computing tasks to its own channel to avoid sudden failures.

[0107] In another implementation, during high-intensity maneuvering flight, the real-time data traffic increases significantly. The high-speed serial bus carries the main load, while the low-speed parallel bus focuses on the final command transmission, ensuring that critical decisions are not delayed even under high load conditions.

[0108] Through the above description of various implementation methods and operating scenarios, the flight control computer provided by this invention can maintain stable control and monitoring capabilities under different flight stages and fault conditions, thereby achieving a highly reliable flight control objective.

[0109] In step S21, the power path management module receives dual power inputs. These dual power inputs typically come from different onboard power systems, such as the main battery pack and a backup generator, ensuring that the failure of a single power source does not affect the overall power supply.

[0110] Specifically, the power path management module continuously monitors the voltage, current, and health status of the two inputs, and selects or combines the outputs according to a preset strategy.

[0111] In step S22, the channel power conversion circuit provides power to the homogeneous dual-redundant processing channel, the heterogeneous AI processing channel, and the external interface unit separately. Each dedicated conversion circuit operates independently to avoid cross-influence of faults.

[0112] In one possible implementation, each switching circuit has an independent protection mechanism, such as overvoltage, overcurrent, and short-circuit protection.

[0113] Step S23: Obtain power output from the power path management module based on the dual power inputs. When the path management module detects an abnormality in one input, it smoothly switches to the other input to ensure uninterrupted output.

[0114] Step S24: The channel power conversion circuit uses different power supply devices to power the homogeneous dual-redundant processing channel. The power supply devices for the two homogeneous processors are selected from different manufacturers or different series to avoid common-mode failure.

[0115] Step S25: The channel power conversion circuit uses different power supply systems to power the heterogeneous AI processing channel. For example, a combination of switching power supply and linear power supply is used to provide high efficiency and low noise characteristics.

[0116] Step S26: The channel power conversion circuit uses different devices to power the external interface unit. The power supply devices for the interface unit are designed for low power consumption to extend system battery life.

[0117] In step S31, the two homogeneous processors employ processors with ARM cores and field-programmable gate arrays. This integrated design balances software flexibility and hardware acceleration capabilities.

[0118] Step S32: The processor runs a real-time embedded operating system. This operating system provides deterministic task scheduling and interrupt management.

[0119] Step S33: Obtain task priority scheduling from the real-time embedded operating system. High-priority tasks, such as control law calculations, are executed first.

[0120] Step S34: Schedule and run the flight control algorithm according to mission priority. Ensure that critical missions are completed before the deadline.

[0121] Step S41: The AI ​​processor uses a processor module with parallel computing capabilities of a graphics processing unit. This is suitable for running complex fault handling models.

[0122] Step S42: The processor module is equipped with a real-time operating system. It supports a task deadline scheduling mechanism.

[0123] Step S43: Obtain the task deadline schedule from the real-time operating system. Ensure that hard real-time tasks are completed on schedule.

[0124] Step S44: Schedule and run the fault handling model according to the task deadline. The model task has the highest deadline priority.

[0125] Step S45: Obtain fault monitoring results from the fault handling model. The results include channel health status and anomaly indicators.

[0126] Step S46: Generate a fault handling strategy based on the fault monitoring results. The strategy may include channel isolation or mode degradation.

[0127] Example 1: This invention addresses the problem of complex fault handling models sharing common-mode faults with homogeneous processors when implementing complex fault management and reconfiguration functions in flight control computers by employing an independent AI processor channel. For example... Figure 1 The diagram shows the power distribution architecture of the dissimilar flight control computer of this invention, as detailed below: Different power redundancy conversion modules are used to power the homogeneous processor channel, the heterogeneous AI processing channel, and the external interface unit respectively, ensuring the independence of the AI ​​processor channel. The three processor channels of the dissimilar flight control computer use a heterogeneous bus approach combining a high-speed serial bus and a low-speed parallel bus for data exchange. A high-speed serial bus, connected in pairs, is used for real-time data exchange between the three processors, while the low-speed parallel bus is used for basic data monitoring and critical data transmission after fault degradation. This heterogeneous bus approach avoids system failure caused by a single bus failure. The data exchange relationship between the three processor channels is as follows: Figure 2 As shown.

[0128] The flight control computer's three processor channels each have different flight control algorithms. Homogeneous processor channel 1 and the heterogeneous AI processing channel have complete flight control algorithms; homogeneous processor channel 2 has a simplified flight control algorithm that ensures basic flight safety during fault degradation; the heterogeneous AI processing channel also has a fault management model for real-time fault monitoring and strategy recommendations. All three processor channels have control laws such as... Figure 3 As shown.

[0129] The core idea of ​​this invention is as follows: Figure 4 As shown, the core idea is to add an independent computing channel based on an AI processor to the traditional dual-redundant flight control computer. With the help of the powerful computing capabilities of the AI ​​processor, fault handling models and flight control algorithms can be run simultaneously, and the homogeneous dual-redundant computing channel can be supervised to improve the safety of the system.

[0130] 1. Power supply heterogeneity redundancy To achieve a dual-busbar power supply architecture, the power path management module supports dual power inputs to ensure that even if one power input fails, the power path management module can still provide a stable power input to the flight control computer.

[0131] like Figure 5 As shown, the power supply for the internal functional components of the flight control computer adopts a heterogeneous power conversion circuit. Channel 1 power conversion circuit supplies power to two homogeneous processor channels; Channel 2 power conversion circuit supplies power to the heterogeneous AI processing channel; and Channel 3 power conversion circuit supplies power to the external interface processing module. These three power conversion channels use different components or different power supply systems to avoid common-mode failures under the premise of unified power supply planning.

[0132] 2. Processor heterogeneity selection and operating system application like Figure 6 As shown, the flight control computer uses a heterogeneous processor, carries different operating systems, and handles different control tasks. This heterogeneity is designed to avoid occasional failures of the operating system, processor, and control algorithm.

[0133] 1) Selection of Homogeneous Dual-Redundant Processors The homogeneous dual-redundant processor uses the Xilinx ZYNQ7045 as its processor. The PS (Power Supply) side integrates a dedicated hard-core processor with two ARM-A7 cores and provides a rich set of external interfaces. Its PL (Power Supply) side integrates a K7 series FPGA, enabling flexible interface configuration as needed.

[0134] 2) Homogeneous dual-redundant processor operating system selection The processor uses the ReWorks real-time embedded operating system, which employs a microkernel, component-based architecture. It categorizes tasks within the system into 256 priority levels, features strong real-time scheduling, and can implement a priority-based preemptive scheduling strategy. It supports various processing mechanisms such as clock management, interrupt management, multi-task management, and memory management. The ReWorks operating system uses a priority-based preemptive scheduling algorithm to schedule tasks, ensuring that at any given time, the highest priority task runs on the processor. For tasks with the same priority, it uses a round-robin scheduling algorithm and a first-in-first-out (FIFO) principle to ensure the effective execution of core tasks.

[0135] 3) Selection of Heterogeneous AI Processors The AI ​​processor uses the NVIDIA Xavier module, which has powerful AI convolution processing capabilities and can quickly execute calculations for artificial intelligence-related algorithms. At the same time, this module needs to support mainstream AI algorithm frameworks, and the program has strong scalability and portability.

[0136] AI processors utilize GPU-based parallel computing to rapidly process AI algorithms. They support a rich set of artificial intelligence algorithm frameworks and offer the strongest scalability and portability.

[0137] 4) Selection of operating system for heterogeneous AI processors The heterogeneous processor runs on a Linux real-time operating system, achieving deterministic low-latency response through real-time scaling. The operating system employs fixed-priority preemptive scheduling, supporting both time-slice-less and time-slice-with round-robin scheduling. Dynamic priority scheduling based on the Earliest Deadline First (EDF) algorithm ensures task completion within deadlines. The operating system also supports isolating certain cores for dedicated real-time tasks, resolving priority inversion issues.

[0138] 3. Heterogeneous bus The flight control computer processor channels utilize Ethernet as a high-speed serial bus to achieve high-bandwidth data transmission. The Ethernet bus for the homogeneous redundant processor is implemented using the chip's built-in Ethernet IP core combined with peripheral circuitry, while the Ethernet bus for the heterogeneous AI processor is implemented using a PCIe bus extended with Ethernet. Furthermore, the flight control computer processor channels employ an ARINC825 parallel bus as a heterogeneous redundancy backup to ensure the transmission of critical information.

[0139] Homogeneous Dual-Redundant Processor Ethernet Interface Design The homogeneous dual-redundant processor uses Marvell's 88E1111-B2-BAB1I000 Ethernet chip to provide network communication services. The Ethernet PHY chip connects to BANK10 of the FPGA chip. The 88E1111-B2-BAB1I000 chip supports 10 / 100 / 1000Mbps network transmission rates and communicates with the FPGA's MAC layer (TSN IP core) via the RGMII interface. The 88E1111-B2-BAB1I000 chip supports MDIO / MDC auto-adaptation, 10 / 100 / 1000Mbps speed auto-adaptation, Master / Slave auto-adaptation, and supports MDIO bus for PHY chip register management.

[0140] Heterogeneous AI processor Ethernet interface design The heterogeneous AI processor adopts a PCIe interface conversion, and the switching chip selected is the PEX8619 PCIe switch chip manufactured by PLX Corporation. This chip can realize flexible and multi-functional interface conversion, provide submicron-level packet transmission latency and high-performance data transmission bandwidth, and provide end-to-end CRC high integrity check, making it suitable for high-speed and high-bandwidth data transmission applications.

[0141] Parallel bus design The triple-redundant processor uses the ARINC825 parallel bus for information exchange. This bus is an airborne bus standard based on the CAN 2.0B protocol extension and is specifically designed to meet the high reliability, real-time performance, and security requirements of avionics systems. Priority scheduling ensures real-time information transmission, while the design based on message sequence numbers and verification mechanisms enhances anti-interference capabilities, prevents message loss or errors, and adapts to the high reliability requirements of the airborne environment.

[0142] The core of this invention lies in employing an independent, dissimilar AI processor to run independent flight control algorithms and fault handling models based on a homogeneous dual-redundant processor. A heterogeneous bus is used for data communication and information comparison among the redundant processors, avoiding common-mode failures and improving the reliability of the flight control computer's mission operation. It can be used for automatic flight control and primary flight control of electric aircraft in low-altitude domains such as eVTOL. By adopting a dissimilar redundancy architecture based on an AI processor, and considering the heterogeneous redundancy design of the power supply and inter-processor communication bus, the system achieves high security. Simultaneously, the flight control computer considers the balance of the redundancy architecture, greatly improving the system's computing power without increasing system complexity, providing a high-performance computing platform for the intelligent algorithms. Therefore, this invention has better generalization ability and practical application value.

[0143] The foregoing has provided a detailed description of a dissimilar flight control computer with AI processing capabilities, as provided in the embodiments of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application; furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

[0144] Certain terms are used in the specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on differences in function. The terms "comprising" and "including" used throughout the specification and claims are open-ended and should be interpreted as "comprising / including but not limited to". "Approximately" means that within an acceptable margin of error, those skilled in the art can solve the technical problem and substantially achieve the technical effect within a certain margin of error. The following descriptions in the specification are preferred embodiments for carrying out this application; however, these descriptions are for the purpose of illustrating the general principles of this application and are not intended to limit the scope of this application. The scope of protection of this application shall be determined by the appended claims.

[0145] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a product or system comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a product or system. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the product or system that includes said element.

[0146] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0147] The foregoing description illustrates and describes several preferred embodiments of this application. However, as previously stated, it should be understood that this application is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the application concept described herein through the foregoing teachings or techniques or knowledge in related fields. Any modifications and variations made by those skilled in the art that do not depart from the spirit and scope of this application should be within the protection scope of the appended claims.

Claims

1. A dissimilar flight control computer based on an AI processor, characterized in that, The asymmetric flight control computer includes: a heterogeneous power conversion circuit, a heterogeneous bus, a homogeneous dual-redundant processing channel, a heterogeneous AI processing channel, and an external interface unit. The homogeneous dual-redundant processing channel includes two homogeneous processors, and the heterogeneous AI processing channel includes one AI processor. The homogeneous dual-redundant processing channel and the heterogeneous AI processing channel are equipped with flight control algorithms, and the heterogeneous AI processing channel is also equipped with a fault handling model; The homogeneous dual-redundant processing channel, the heterogeneous AI processing channel, and the external interface unit are all powered by a heterogeneous power conversion circuit. The homogeneous dual-redundant processing channel and the heterogeneous AI processing channel output flight control commands through the external interface unit; The two homogeneous processors and the AI ​​processor interact and compare data through a heterogeneous bus; the heterogeneous AI processing channel supervises the homogeneous dual-redundant processing channel.

2. The dissimilar flight control computer according to claim 1, characterized in that, The heterogeneous power conversion circuit includes: a channel power conversion circuit and a power path management module, wherein the channel power conversion circuit is connected to the power path management module; The power path management module supports dual power inputs; The channel power conversion circuit simultaneously supplies power to the homogeneous dual-redundant processing channel, the heterogeneous AI processing channel, and the external interface unit.

3. The dissimilar flight control computer according to claim 2, characterized in that, The channel power conversion circuit uses different devices or different power systems to connect the homogeneous dual-redundant processing channel and the heterogeneous AI processing channel to avoid common-mode faults.

4. The dissimilar flight control computer according to claim 1, characterized in that, The two isomorphic processors are an ARM core processor and an FPGA processor, respectively; the two isomorphic processors are equipped with a real-time embedded operating system, and the isomorphic dual-redundant processing channel obtains task priority scheduling from the real-time embedded operating system; the flight control algorithm is run according to the task priority scheduling.

5. The dissimilar flight control computer according to claim 1, characterized in that, The AI ​​processor is a processor module with GPU parallel computing capabilities; the processor module with GPU parallel computing capabilities is equipped with a real-time operating system; the heterogeneous AI processing channel obtains the task deadline schedule from the real-time operating system; and runs the fault handling model according to the task deadline schedule. Obtain fault monitoring results from the fault handling model; generate fault handling strategies based on the fault monitoring results.

6. The dissimilar flight control computer according to claim 1, characterized in that, The heterogeneous bus includes a high-speed serial bus and a low-speed parallel bus. The high-speed serial bus connects two homogeneous processors and an AI processor simultaneously, enabling real-time data interaction between the homogeneous dual-redundant processing channel and the heterogeneous AI processing channel. The low-speed parallel bus connects two homogeneous processors and an AI processor simultaneously, enabling critical data transmission between the homogeneous dual-redundant processing channel and the heterogeneous AI processing channel. The high-speed serial bus is used to acquire real-time data, and key information is transmitted through the low-speed parallel bus based on the real-time data. Fault degradation data is obtained from the low-speed parallel bus.

7. The dissimilar flight control computer according to claim 1, characterized in that, The AI ​​processor is equipped with a complete flight control algorithm; one of the two isomorphic processors is equipped with a complete flight control algorithm; the other is equipped with a simplified flight control algorithm; control output is obtained from the complete flight control algorithm; the consistency of the three processor channels is compared based on the control output; if the comparison is inconsistent, a downgraded output is obtained from the simplified flight control algorithm.

8. The dissimilar flight control computer according to claim 1, characterized in that, The two homogeneous processors and the AI ​​processor interact and compare data via a heterogeneous bus. Specifically, the output of the homogeneous dual-redundant processing channel is obtained from the heterogeneous bus; the output of the fault handling model is obtained from the heterogeneous AI processing channel; the output of the homogeneous dual-redundant processing channel is compared with the output of the fault handling model; if the comparison is consistent, the flight control output is confirmed; if the comparison is inconsistent, a fault degradation decision is obtained from the fault handling model.

9. The dissimilar flight control computer according to claim 6, characterized in that, The two homogeneous processors implement a high-speed serial bus via FPGA IP cores and PHY chips, while the heterogeneous AI processors implement a high-speed serial bus via PCIe switching chips; the three processors implement a low-speed parallel bus via ARINC825 bus.

10. The dissimilar flight control computer according to claim 9, characterized in that, The flight control system obtains Ethernet data packets from the FPGA IP core; transmits the Ethernet data packets according to the PCIe switching chip; and obtains priority messages from the ARINC825 bus.

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