Electronic equipment, interrupt processing method and storage medium

Abstract

The invention provides electronic equipment, an interrupt processing method and a storage medium, and relates to the technical field of computers. The electronic device runs based on a processor platform of a reduced instruction set, the electronic device comprises an embedded controller, a processor, a first target bus, a second target bus and at least one sub-device, the processor is based on the reduced instruction set, and the first target bus and the second target bus are both I2C buses. The I2C bus is a bidirectional two-wire system synchronous serial communication bus; the embedded controller is connected with the processor through a first target bus, so that the embedded controller communicates with the processor; the embedded controller is connected with each sub-device through a second target bus, so that the embedded controller communicates with each sub-device; the embedded controller and the sub-equipment are respectively configured as I2C equipment in the ACPI configuration table, so that the embedded controller, the embedded controller driver and the sub-equipment driver can run on the ARM platform, and the development workload of the ARM platform is reduced.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to an electronic device, an interrupt handling method, and a storage medium. Background Technology

[0002] An embedded controller (EC) is a small, processor-independent controller located on the motherboard. It manages and controls lower-level sub-devices such as power supplies, keyboards, and fans. Processor platforms include the x86 platform and the ARM platform. The x86 platform is based on the complex instruction set architecture (CIA), while the ARM platform is based on the reduced instruction set architecture (RISC).

[0003] The x86 platform processor provides a Low Pin Count (LPC) bus. The embedded controller connects and communicates with the processor through the LPC bus, and connects and communicates with sub-devices through the LPC bus, enabling the embedded controller, the embedded controller driver (EC driver) in the operating system, and their sub-device drivers to run on the x86 platform.

[0004] In the ARM platform, because the ARM platform does not have an LPC bus and does not support the LPC protocol, the embedded controller cannot communicate with the processor or connect and communicate with sub-devices through the LPC bus. As a result, the embedded controller cannot run on the ARM platform, and the embedded controller driver and its sub-device drivers in the operating system also cannot run on the ARM platform.

[0005] In related technologies, if embedded controllers, embedded controller drivers and their sub-device drivers are required to run on the ARM platform, the embedded controllers, embedded controller drivers and their sub-device drivers need to be redesigned, which will greatly increase the development workload and development cost of embedded controllers on the ARM platform. Summary of the Invention

[0006] To address the problems existing in the aforementioned related technologies, this disclosure provides an electronic device, an interrupt handling method, and a storage medium.

[0007] The first aspect of this disclosure provides an electronic device that operates on a Reduced Instruction Set Computing (RISC) processor platform. The electronic device includes an embedded controller, a processor, a first target bus, a second target bus, and at least one sub-device. The processor is a RISC-based processor, and both the first and second target buses are I / O pins. 2 C bus, I 2 The C bus is a bidirectional two-wire synchronous serial communication bus; The embedded controller is connected to the processor via a first target bus to enable communication between the embedded controller and the processor; The embedded controller connects to each sub-device via a second target bus to enable communication between the embedded controller and each sub-device. The embedded controller and sub-device are configured as I in the ACPI configuration table. 2 For device C, ACPI stands for Advanced Configuration and Power Interface.

[0008] Optionally, the above-mentioned electronic device may also include a first GPIO controller, a second GPIO controller, a third GPIO controller, and a fourth GPIO controller, where GPIO is a general purpose input / output interface; The processor is connected to the first target bus via the first GPIO controller; The embedded controller is connected to the first target bus through a second GPIO controller, and the embedded controller is connected to the second target bus through a third GPIO controller. For each sub-device, the sub-device is connected to the second target bus through the corresponding fourth GPIO controller.

[0009] Optionally, the first GPIO controller is connected to the first target bus via a first GPIO pin; The second GPIO controller is connected to the first target bus via the second GPIO pin; The third GPIO controller is connected to the second target bus through the third GPIO pin, and the number of the third GPIO pins is equal to the number of sub-devices; The fourth GPIO controller is connected to the second target bus via the fourth GPIO pin.

[0010] Optionally, the aforementioned electronic device may also include an interrupt processor; One end of the interrupt handler is connected to the processor, and the other end of the interrupt handler is connected to the first GPIO controller; An interrupt handler is used to process interrupt signals from an interrupt source and sends the interrupt signals to the processor so that the processor can process the interrupt signals. The interrupt source includes at least an embedded controller.

[0011] Optionally, the processor is the master device on the first target bus, and the embedded controller is the slave device on the first target bus; The embedded controller is the master device on the second target bus, and each sub-device is a slave device on the second target bus.

[0012] Optionally, the ACPI configuration table above shall include at least the device information of the embedded controller, the device information of each sub-device, the event queue query instruction corresponding to each interrupt signal of the embedded controller, and the event handling method corresponding to each event number; The device information for the embedded controller should at least include the device type of the embedded controller being I. 2 C device, device identifiers of each device connected to the embedded controller, communication address of the embedded controller, and data transmission rate; The device information of the sub-device should at least include the device type as I. 2 C. Device identifiers of each device connected to the sub-devices, communication addresses of the sub-devices, and data transmission rates.

[0013] The second aspect of this disclosure provides an interrupt handling method applied to a processor in the electronic device described in the first aspect, the method comprising: Receive a target interrupt signal sent by the embedded controller through the first target bus. The target interrupt signal is an interrupt signal generated by the embedded controller when it detects a target hardware event in at least one of the target sub-devices through the second target bus. Identify the target driver corresponding to the target interrupt signal; the target driver is the driver for the embedded controller. Based on target-driven approach, the target event handling method corresponding to the target interrupt signal is determined through the ACPI configuration table. Based on the target-driven approach, execute the target event handling method.

[0014] Optionally, the above-mentioned target-driven method for determining the target event handling corresponding to the target interrupt signal through the ACPI configuration table includes: Based on target-driven operation, the target event number corresponding to the target interrupt signal is queried through the ACPI configuration table; Based on target-driven operation, the target event handling method corresponding to the target event number is queried from the ACPI configuration table. Optionally, the above-mentioned querying of the target event number corresponding to the target interrupt signal through the ACPI configuration table based on target-driven operation includes: Based on target-driven operation, retrieve the event queue query instruction corresponding to the target interrupt signal from the ACPI configuration table; An event queue query command is sent to the embedded controller via the first target bus, so that the embedded controller responds to the event queue query command by returning the target event number corresponding to the target interrupt signal to the processor via the first target bus. Based on target-driven operation, the target event number corresponding to the target interrupt signal returned by the embedded controller is received.

[0015] Optionally, the above target-driven target event handling method includes: Based on target-driven approach, the target event information and target sub-device identifier corresponding to the target event number are obtained from the target event handling method; Based on target-driven, determine the target device driver corresponding to the target sub-device identifier, and notify the target device driver of the target event information; Based on the target device driver, execute the target operation corresponding to the target event information.

[0016] Optionally, the above-mentioned target operation, based on the target device driver and corresponding to the target event information, includes: Based on the target device driver, the target event information is sent to the user space of the operating system; Based on the target management program corresponding to the target event information in the user space, execute the target operation corresponding to the target event information.

[0017] A third aspect of this disclosure provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the interrupt handling method of the second aspect described above.

[0018] The technical solution provided in this disclosure has the following advantages compared with the prior art: In this embodiment of the disclosure, the electronic device operates on a Reduced Instruction Set Computing (RISC) processor platform. The electronic device includes an embedded controller, a processor, a first target bus, a second target bus, and at least one sub-device. The processor is a RISC-based processor, and both the first and second target buses are I / O pins. 2 C bus, I 2 The C-bus is a bidirectional two-wire synchronous serial communication bus; the embedded controller connects to the processor via the first target bus to enable communication between the embedded controller and the processor; the embedded controller connects to each sub-device via the second target bus to enable communication between the embedded controller and each sub-device; the embedded controller and sub-devices are configured as I in the ACPI configuration table. 2 For device C, ACPI stands for Advanced Configuration and Power Interface. Therefore, by configuring the embedded controller and its corresponding sub-device as I in the ACPI configuration table... 2 C device, and enables the embedded controller to communicate with the RISC-based processor via the existing I / O interface in the ARM platform. 2 Communication is achieved via the C bus, enabling the embedded controller and sub-devices to communicate through the existing I / O pins in the ARM platform. 2 Communication is achieved via the C bus, utilizing the ACPI mechanism and I supported on the ARM platform. 2The C-bus enables the ARM platform to support embedded controllers, embedded controller drivers, and their sub-device drivers in both hardware and software, allowing these drivers to run on the ARM platform. This eliminates the need to redesign embedded controllers, drivers, and sub-device drivers for the ARM platform, significantly reducing the development workload and costs associated with embedded controllers on the ARM platform.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0021] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of an electronic device provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of another electronic device provided in an embodiment of this disclosure; Figure 3 This is a flowchart of an interrupt handling method provided in an embodiment of this disclosure; Figure 4 This is a flowchart of another interrupt handling method provided in this embodiment of the disclosure; Figure 5 This is a flowchart of another interrupt handling method provided in the embodiments of this disclosure; Figure 6 This is a flowchart of another interrupt handling method provided in the embodiments of this disclosure. Detailed Implementation

[0023] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0024] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0025] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0026] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0027] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0028] To better understand the inventive concept of the embodiments of this disclosure, the technical solutions of the embodiments of this disclosure will be described below in conjunction with exemplary embodiments.

[0029] Figure 1 This is a schematic diagram of an electronic device provided in an embodiment of this disclosure, such as... Figure 1 As shown, the electronic device 100 provided in this embodiment operates on a Reduced Instruction Set Computing (ARM) processor platform. The electronic device 100 may include an embedded controller 110, a processor 120, a first target bus 130, a second target bus 140, and at least one sub-device 150; the processor is a RISC-based processor, and both the first and second target buses are I / O pins. 2 C bus, I 2 The C bus is a bidirectional two-wire synchronous serial communication bus; Among them, the embedded controller (EC) can be understood as a small controller on the motherboard that is independent of the processor. It is responsible for managing and controlling the underlying hardware devices such as power supply, keyboard, fan, temperature, and battery.

[0030] Processors based on a reduced instruction set are called ARM (Advanced RISC Machine) processors, which are processors in the ARM platform.

[0031] I 2 The C (Inter-Integrated Circuit) bus can be understood as a bidirectional two-wire synchronous serial communication bus, which only requires two wires (including a serial data line and a serial clock line) to transmit information between devices connected to the bus.

[0032] Sub-devices can be understood as underlying hardware devices such as power supplies, keyboards, fans, temperature controllers, and batteries.

[0033] The embedded controller can be connected to the processor via a first target bus to enable communication between the embedded controller and the processor; The embedded controller can be connected to each sub-device via a second target bus to enable communication between the embedded controller and each sub-device; The embedded controller and sub-device are configured as I in the ACPI configuration table. 2 For device C, ACPI stands for Advanced Configuration and Power Interface.

[0034] The Advanced Configuration and Power Interface (ACPI) can be understood as a power management standard or specification used to coordinate power management and device configuration between hardware and the operating system. It can also be understood as a communication standard or specification between hardware and the operating system.

[0035] The electronic device in this disclosure can be understood as any device with processing and computing capabilities, including but not limited to electronic devices such as smartphones, laptops, personal digital assistants (PDAs), tablet computers (PADs), portable multimedia players (PMPs), in-vehicle terminals, wearable devices, digital TVs, desktop computers, smart home devices, etc.

[0036] In this embodiment of the disclosure, the electronic device operates on a Reduced Instruction Set Computing (RISC) processor platform. The electronic device includes an embedded controller, a processor, a first target bus, a second target bus, and at least one sub-device. The processor is a RISC-based processor, and both the first and second target buses are I / O pins. 2 C bus, I 2The C-bus is a bidirectional two-wire synchronous serial communication bus; the embedded controller connects to the processor via the first target bus to enable communication between the embedded controller and the processor; the embedded controller connects to each sub-device via the second target bus to enable communication between the embedded controller and each sub-device; the embedded controller and sub-devices are configured as I in the ACPI configuration table. 2 For device C, ACPI stands for Advanced Configuration and Power Interface. Therefore, by configuring the embedded controller and its corresponding sub-device as I in the ACPI configuration table... 2 C device, and enables the embedded controller to communicate with the RISC-based processor via the existing I / O interface in the ARM platform. 2 Communication is achieved via the C bus, enabling the embedded controller and sub-devices to communicate through the existing I / O pins in the ARM platform. 2 Communication is achieved via the C bus, utilizing the ACPI mechanism and I supported on the ARM platform. 2 The C-bus enables the ARM platform to support embedded controllers, embedded controller drivers, and their sub-device drivers in both hardware and software, allowing these drivers to run on the ARM platform. This eliminates the need to redesign embedded controllers, drivers, and sub-device drivers for the ARM platform, significantly reducing the development workload and costs associated with embedded controllers on the ARM platform.

[0037] In some embodiments of this disclosure, the above-mentioned electronic device may further include a first GPIO controller, a second GPIO controller, a third GPIO controller, and a fourth GPIO controller, where GPIO (General Purpose Input / Output) is a general-purpose input / output interface; The processor can be connected to the first target bus via the first GPIO controller; The embedded controller can be connected to the first target bus through a second GPIO controller, and the embedded controller can be connected to the second target bus through a third GPIO controller; For each sub-device, the sub-device can be connected to the second target bus through the fourth GPIO controller corresponding to the sub-device.

[0038] GPIO can be understood as a pin interface that can be flexibly configured by user software. Its behavior (input or output) and electrical characteristics (such as level, drive capability, etc.) can be dynamically set by the program in the GPIO controller.

[0039] For example, Figure 2 This is a schematic diagram of an electronic device provided in an embodiment of this disclosure, such as... Figure 2As shown, the electronic device 200 provided in this embodiment runs on a Reduced Instruction Set Computing (ARM) processor platform. In the electronic device 200, the processor 210 can be connected to the first target bus 230 through the first GPIO controller 220; the embedded controller 250 can be connected to the first target bus 230 through the second GPIO controller 240; the embedded controller 250 can be connected to the second target bus 270 through the third GPIO controller 260; for each sub-device 290, the sub-device 290 can be connected to the second target bus 270 through the corresponding fourth GPIO controller 280.

[0040] Therefore, embedded controllers, processors, and I / O can be implemented using GPIO controllers supported by the ARM platform. 2 The C-bus connection enables the embedded controller's sub-devices to connect to I / O via the GPIO controller supported by the ARM platform. 2 The connection to the C bus enables the embedded controller and sub-devices to communicate via the existing I / O pins in the ARM platform. 2 Communication is achieved via the C bus, utilizing existing ACPI mechanisms and I2C supported on the ARM platform. 2 The C-bus enables the ARM platform to support embedded controllers, embedded controller drivers, and their sub-device drivers in both hardware and software, allowing these drivers to run on the ARM platform. This eliminates the need to redesign embedded controllers, drivers, and sub-device drivers for the ARM platform, significantly reducing the development workload and costs associated with embedded controllers on the ARM platform.

[0041] In some embodiments, the first GPIO controller described above can be connected to the first target bus via a first GPIO pin; The second GPIO controller can be connected to the first target bus via the second GPIO pin; The third GPIO controller can be connected to the second target bus through the third GPIO pins, and the number of the third GPIO pins is equal to the number of sub-devices; The fourth GPIO controller can be connected to the second target bus via the fourth GPIO pin.

[0042] Therefore, embedded controllers, processors, and I / O pins can be implemented using the GPIO controllers and pins supported by the ARM platform. 2 The C-bus connection enables the embedded controller's sub-devices to connect to I / O pins via the GPIO controller and pins supported by the ARM platform. 2 The C-bus connection enables the embedded controller and sub-devices to communicate via the existing I / O pins in the ARM platform. 2 Communication is achieved via the C bus, utilizing existing ACPI mechanisms and I2C supported on the ARM platform.2 The C-bus enables the ARM platform to support embedded controllers, embedded controller drivers, and their sub-device drivers in both hardware and software, allowing these drivers to run on the ARM platform. This eliminates the need to redesign embedded controllers, drivers, and sub-device drivers for the ARM platform, significantly reducing the development workload and costs associated with embedded controllers on the ARM platform.

[0043] In some embodiments, the above-mentioned electronic device may also include a Generic Interrupt Controller (GIC). One end of the interrupt handler can be connected to the processor, and the other end of the interrupt handler can be connected to the first GPIO controller; An interrupt handler can be used to receive interrupt signals from an interrupt source and send the interrupt signals to the processor so that the processor can process the interrupt signals. The interrupt source may include at least an embedded controller.

[0044] An interrupt handler can be understood as a hardware component used to receive and manage interrupt signals. It achieves orderly and efficient management of interrupt signals through priority determination, interrupt masking, and vector allocation.

[0045] Therefore, interrupt handlers can be used to achieve orderly and efficient management of interrupt signals in the ARM platform, thereby improving the processor's efficiency in handling interrupt signals.

[0046] In some embodiments, the processor may be a host device on the first target bus, and the embedded controller may be a slave device on the first target bus. The embedded controller can be the master device on the second target bus, and each sub-device can be a slave device on the second target bus.

[0047] The master device can be understood as the device that actively initiates communication in bus communication.

[0048] A slave device can be understood as a device in bus communication that is accessed by the master device and passively responds to the master device's requests. A slave device can only operate according to the commands sent by the master device, such as receiving or sending data.

[0049] In embedded controllers and processors, the processor is the master device and the embedded controller is the slave device.

[0050] In the embedded controller and its sub-devices, the embedded controller is the master device, and the sub-devices are the slave devices.

[0051] Therefore, it is possible to configure I 2Master and slave devices on the C-bus enable embedded controllers to communicate with sub-devices via existing I / O interfaces in the ARM platform. 2 Communication is achieved via the C bus, utilizing existing ACPI mechanisms and I2C supported on the ARM platform. 2 The C-bus enables the ARM platform to support embedded controllers, embedded controller drivers, and their sub-device drivers in both hardware and software, allowing these drivers to run on the ARM platform. This eliminates the need to redesign embedded controllers, drivers, and sub-device drivers for the ARM platform, significantly reducing the development workload and costs associated with embedded controllers on the ARM platform.

[0052] In some embodiments of this disclosure, the data in the ACPI configuration table described above can be predefined. Figure 3 This is a schematic diagram of an ACPI configuration table provided in an embodiment of this disclosure, as shown below. Figure 3 As shown, the ACPI configuration table 300 above may include at least the device information 310 of the embedded controller, the device information 320 of each sub-device, the event queue query instruction 330 corresponding to each interrupt signal of the embedded controller, and the event handling method 340 corresponding to each event number. The device information 310 of the embedded controller may include at least the device type of the embedded controller as I. 2 C device, device identifiers of each device connected to the embedded controller, communication address of the embedded controller, and data transmission rate; The device information of a sub-device can at least include the device type as I. 2 C. Device identifiers of each device connected to the sub-devices, communication addresses of the sub-devices, and data transmission rates.

[0053] For example, the device connected to the embedded controller may include the first I corresponding to the first target bus. 2 C-bus controller, processor-connected first GPIO controller, first GPIO pin in the first GPIO controller, second GPIO controller, second GPIO pin in the second GPIO controller, second I-band corresponding to the second target bus. 2 The C-bus controller, the third GPIO controller, the third GPIO pin in the third GPIO controller, the fourth GPIO controller, the fourth GPIO pin in the fourth GPIO controller, and various sub-devices.

[0054] For example, the device connected to the sub-device may include the second I corresponding to the second target bus. 2C-bus controller, embedded controller, third GPIO controller connected to embedded controller, third GPIO pin in third GPIO controller, fourth GPIO controller, fourth GPIO pin in fourth GPIO controller, etc.

[0055] Therefore, by defining the device information of the embedded controller, the device information of each sub-device, the event queue query instructions corresponding to each interrupt signal of the embedded controller, and the event handling methods corresponding to each event number in the ACPI configuration table, the embedded controller and its corresponding sub-devices can be configured as I... 2 C device, and enables the embedded controller to communicate with the RISC-based processor via the existing I / O interface in the ARM platform. 2 Communication is achieved via the C bus, enabling the embedded controller and sub-devices to communicate through the existing I / O pins in the ARM platform. 2 Communication is achieved via the C bus, utilizing the ACPI mechanism and I supported on the ARM platform. 2 The C-bus enables the ARM platform to support embedded controllers, embedded controller drivers, and their sub-device drivers in both hardware and software, allowing these drivers to run on the ARM platform. This eliminates the need to redesign embedded controllers, drivers, and sub-device drivers for the ARM platform, significantly reducing the development workload and costs associated with embedded controllers on the ARM platform.

[0056] This disclosure provides an interrupt handling method, applied to a processor in the electronic device described in any of the above embodiments. Figure 4 This is a flowchart of an interrupt handling method provided in an embodiment of this disclosure. This method can be executed by a processor in the electronic device described in any of the above embodiments, such as... Figure 4 As shown, the interrupt handling method provided in this embodiment includes the following steps: Step 410: Receive the target interrupt signal sent by the embedded controller through the first target bus. The target interrupt signal is an interrupt signal generated by the embedded controller when it detects a target hardware event in at least one of the target sub-devices through the second target bus.

[0057] In this embodiment of the present disclosure, the processor in the electronic device can access the first target bus (I) 2 The embedded controller communicates with the C bus, and the embedded controller can communicate via a second target bus (I). 2The embedded controller communicates with the sub-device via the C bus. The embedded controller can detect whether a hardware event has occurred in the sub-device via the second target bus. When the embedded controller detects that a target hardware event has occurred in at least one of the target sub-devices, it can generate a target interrupt signal and then send the target interrupt signal to the processor via the first target bus. The processor can receive the target interrupt signal.

[0058] The target hardware events can include events such as the battery being fully charged, the battery entering a low power state, the power button being pressed, the laptop lid being closed, and the laptop lid being opened.

[0059] Step 420: Determine the target driver corresponding to the target interrupt signal. The target driver is the embedded controller driver.

[0060] In this embodiment of the disclosure, the processor in the electronic device can determine the target driver corresponding to the target interrupt signal. The target driver can be understood as an embedded controller driver.

[0061] A driver can be understood as a software program that drives the hardware devices in a computer to perform actions. A driver is a special program added to the operating system that contains information about the hardware devices, which enables the computer to communicate with the corresponding hardware devices.

[0062] Step 430: Based on target-driven approach, determine the target event handling method corresponding to the target interrupt signal through the ACPI configuration table.

[0063] In this embodiment of the disclosure, the processor in the electronic device can determine the target event handling method corresponding to the target interrupt signal through the ACPI configuration table based on the target driver.

[0064] The ACPI configuration table can be pre-stored in the Basic Input Output System (BIOS). The BIOS is a set of programs embedded in a ROM chip on the motherboard. It stores the most important basic input and output programs of the computer device, the power-on self-test program, and the system startup program. Its main function is to provide the lowest level and most direct hardware settings and control for the computer device.

[0065] When a computer device starts up, the BIOS can send the ACPI configuration table to the operating system running on the processor.

[0066] Step 440: Based on the target-driven approach, execute the target event handling method.

[0067] In this embodiment of the disclosure, the processor can execute a target event processing method based on the target driver.

[0068] In this embodiment, the processor in the aforementioned electronic device receives a target interrupt signal sent by the embedded controller via a first target bus. The target interrupt signal is an interrupt signal generated by the embedded controller when it detects a target hardware event occurring in at least one of its sub-devices via a second target bus. The processor then determines the target driver corresponding to the target interrupt signal, which is the driver of the embedded controller. Based on the target driver, the processor determines the target event handling method corresponding to the target interrupt signal using an ACPI configuration table. Finally, the processor executes the target event handling method based on the target driver. Thus, the aforementioned electronic device enables the embedded controller, its driver, and its sub-device drivers to run on an ARM platform. The processor, based on a reduced instruction set architecture, and the embedded controller can communicate via the first target bus (I... 2 Communication is via a C-bus, and the embedded controller communicates with the sub-devices via a second target bus (I-bus). 2 Interrupt handling for embedded controllers on the ARM platform is achieved through a second target bus (C-bus). The embedded controller detects sub-devices via the second target bus and generates a target interrupt signal when a hardware event occurs on the sub-device. The target interrupt signal is then sent to the processor via the first target bus for processing. The processor, based on the reduced instruction set architecture (RISC), determines the target event handling method corresponding to the target interrupt signal of the embedded controller through the embedded controller driver and the ACPI configuration table, and executes the target event handling method based on the embedded controller driver. This significantly reduces the development workload and cost of interrupt handling for embedded controllers on the ARM platform.

[0069] In some embodiments, the above-described target event handling method, which determines the target interrupt signal based on the ACPI configuration table, can be executed by the processor in the electronic device. Figure 5 A flowchart of an interrupt handling method is provided, such as Figure 5 As shown, the interrupt handling method provided in this embodiment includes the following steps: Step 510: Based on target-driven operation, query the target event number corresponding to the target interrupt signal through the ACPI configuration table.

[0070] In this embodiment of the disclosure, the processor in the electronic device can query the target event number corresponding to the target interrupt signal through the target driver in the processor and the ACPI configuration table in the operating system.

[0071] A target event number can be understood as an identifier that uniquely identifies a target hardware event. For example, a target event number can be 01, 02, etc.

[0072] For example, if the target sub-device is a battery, and the target hardware event that occurs on the target sub-device is that the battery is fully charged, then the target event number can be 01; If the target sub-device is a battery, and the target hardware event that occurs in the target sub-device is that the battery enters a low power state, then the target event number can be 02; If the target sub-device is a laptop lid, and the target hardware event occurring on the target sub-device is the laptop lid closing, then the target event number can be 03; If the target sub-device is a laptop lid, and the target hardware event occurring on the target sub-device is "laptop lid open", then the target event number can be 04; If the target sub-device is a power button, and the target hardware event occurring on the target sub-device is the power button being pressed, then the target event number can be 05.

[0073] In some embodiments, based on the target driver, the processor in the electronic device can execute steps 5101-5103 by querying the target event number corresponding to the target interrupt signal through the ACPI configuration table: Step 5101: Based on the target driver, obtain the event queue query instruction corresponding to the target interrupt signal from the ACPI configuration table.

[0074] The embedded controller namespace in the ACPI configuration table predefines event queue query (GET Queue, GETQ) instructions corresponding to each interrupt signal. The event queue query instructions can be understood as event queue query functions.

[0075] Step 5102: Send an event queue query command to the embedded controller via the first target bus, so that the embedded controller responds to the event queue query command and returns the target event number corresponding to the target interrupt signal to the processor via the first target bus.

[0076] The embedded controller includes an event queue that records the event number corresponding to each interrupt signal. Based on the target driver, the processor can send an event queue query command corresponding to the target interrupt signal to the embedded controller via a first target bus. The embedded controller can respond to this command, retrieve the target event number corresponding to the target interrupt signal from the event queue, and then return the target event number to the processor via the first target bus.

[0077] Step 5103: Based on the target driver, receive the target event number corresponding to the target interrupt signal returned by the embedded controller.

[0078] The processor in the electronic device can receive the target event number corresponding to the target interrupt signal returned by the embedded controller, based on the target driver.

[0079] Therefore, the target event number corresponding to the target interrupt signal can be accurately obtained by querying the event queue corresponding to the target interrupt signal in the ACPI configuration table.

[0080] Step 520: Based on target-driven approach, query the target event handling method corresponding to the target event number from the ACPI configuration table.

[0081] In this embodiment of the disclosure, the embedded controller namespace of the ACPI configuration table predefines event handling methods corresponding to each event number. An event handling method can be represented as a _QXX method, where Q represents a query and XX represents the event number.

[0082] The processor can query the target event handling method corresponding to the target event number from the ACPI configuration table based on the target driver.

[0083] For example, if the target event number is 01, then the target event handling method corresponding to the target event number can be the _Q01 method; If the target event number is 02, then the target event handling method corresponding to the target event number can be the _Q02 method.

[0084] Therefore, the target event handling method corresponding to the target event number can be accurately and quickly obtained through the embedded controller driver and ACPI configuration table.

[0085] In some embodiments, the above-described target-driven, target event handling method can be executed by the processor in the electronic device. Figure 6 A flowchart of an interrupt handling method is provided, such as Figure 6 As shown, the interrupt handling method provided in this embodiment includes the following steps: Step 610: Based on target-driven approach, obtain the target event information and target sub-device identifier corresponding to the target event number from the target event processing method.

[0086] Target event information can be understood as descriptive information about target hardware events.

[0087] For example, the target event information could be the battery being fully charged, the battery entering a low power state, the laptop lid being closed, or the laptop lid being opened.

[0088] The target sub-device identifier can be understood as an identifier that can uniquely identify the target sub-device.

[0089] Step 620: Based on the target driver, determine the target device driver corresponding to the target sub-device identifier, and notify the target device driver of the target event information.

[0090] In this embodiment of the disclosure, the processor can determine the target device driver corresponding to the target sub-device identifier based on the target driver, and notify the target device driver of the target event information.

[0091] For example, the target device driver may include a battery driver, a lid driver, a button driver, etc.

[0092] For example, if the target event information is that the battery has entered a low power state, then the target device driver is the battery driver, and the processor can notify the battery driver of the target event information "the battery has entered a low power state" based on the target driver; If the target event information is that the power button is pressed, then the target device driver is the button driver. The processor can notify the button driver of the target event information "the power button is pressed" based on the target driver.

[0093] Step 630: Based on the target device driver, execute the target operation corresponding to the target event information.

[0094] The processor can execute the target operation corresponding to the target event information based on the target device driver.

[0095] For example, if the target event information is that the battery has entered a low power state, the target operation corresponding to the target event information may include updating the battery power display status, popping up a charging prompt window, etc.

[0096] Therefore, based on the embedded controller driver and ACPI configuration table, the target event handling method can be executed accurately and efficiently, improving the accuracy and efficiency of the embedded controller's interrupt handling.

[0097] In some embodiments, based on the target device driver, the target operation corresponding to the target event information is executed. The processor in the electronic device can send the target event information to the user space of the operating system based on the target device driver; and execute the target operation corresponding to the target event information based on the target management program corresponding to the target event information in the user space.

[0098] The processor can send target event information to the operating system's user space based on the target device driver through the input subsystem and netlink event subsystem in the operating system's kernel space.

[0099] User space can be understood as the running area of ​​ordinary applications in the operating system.

[0100] The kernel space can be understood as the running area of ​​the operating system's core programs. These core programs run at a higher privilege level, reside in a protected memory space, and have full access to hardware devices.

[0101] The target management program corresponding to the target event information in the user space can include desktop management program, icon management program, etc.

[0102] For example, if the target event information is that the battery has entered a low power state, the target management program corresponding to the target event information can be the icon management program and the desktop management program. The target operation of updating the battery power display status is performed based on the icon management program, and the target operation of popping up a charging prompt window is performed based on the desktop management program.

[0103] Therefore, the embedded controller driver sends target event information to the operating system's user space, and the target management program corresponding to the target event information in the user space executes the target operation corresponding to the target event information, thereby improving the accuracy and efficiency of the embedded controller's interrupt handling.

[0104] This disclosure provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it can implement the methods of any of the above embodiments. The execution method and beneficial effects are similar, and will not be described again here.

[0105] The aforementioned computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0106] The computer program described above can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this disclosure. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer device, partially on the user's device, as a standalone software package, partially on the user's computer device and partially on a remote computer device, or entirely on a remote computer device or server.

[0107] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0108] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0109] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An electronic device, characterized in that, The electronic device operates on a reduced instruction set computing (RISC) processor platform. The electronic device includes an embedded controller, a processor, a first target bus, a second target bus, and at least one sub-device. The processor is a RISC-based processor, and both the first and second target buses are I / O buses. 2 C bus, the I 2 The C bus is a bidirectional two-wire synchronous serial communication bus; The embedded controller is connected to the processor via the first target bus, so that the embedded controller can communicate with the processor; The embedded controller is connected to each of the sub-devices via the second target bus, so that the embedded controller can communicate with each of the sub-devices; The embedded controller and the sub-device are respectively configured as I in the ACPI configuration table. 2 Device C, where ACPI stands for Advanced Configuration and Power Interface.

2. The electronic device according to claim 1, characterized in that, The electronic device further includes a first GPIO controller, a second GPIO controller, a third GPIO controller, and a fourth GPIO controller, wherein the GPIO is a general purpose input / output interface; The processor is connected to the first target bus via a first GPIO controller; The embedded controller is connected to the first target bus via a second GPIO controller, and the embedded controller is connected to the second target bus via a third GPIO controller; For each of the sub-devices, the sub-device is connected to the second target bus through the fourth GPIO controller corresponding to the sub-device.

3. The electronic device according to claim 2, characterized in that, The first GPIO controller is connected to the first target bus via a first GPIO pin; The second GPIO controller is connected to the first target bus via a second GPIO pin; The third GPIO controller is connected to the second target bus via a third GPIO pin, and the number of the third GPIO pins is equal to the number of the sub-devices; The fourth GPIO controller is connected to the second target bus via the fourth GPIO pin.

4. The electronic device according to claim 2, characterized in that, The electronic device also includes an interrupt processor; One end of the interrupt handler is connected to the processor, and the other end of the interrupt handler is connected to the first GPIO controller; The interrupt processor is used to receive an interrupt signal from an interrupt source and send the interrupt signal to the processor so that the processor processes the interrupt signal. The interrupt source includes at least the embedded controller.

5. The electronic device according to claim 1, characterized in that, The processor is the master device on the first target bus, and the embedded controller is the slave device on the first target bus; The embedded controller is the master device on the second target bus, and each of the sub-devices is a slave device on the second target bus.

6. The electronic device according to claim 1, characterized in that, The ACPI configuration table includes at least the device information of the embedded controller, the device information of each of the sub-devices, the event queue query instruction corresponding to each interrupt signal of the embedded controller, and the event handling method corresponding to each event number; The device information of the embedded controller includes at least the device type of the embedded controller being I. 2 C. Device identifiers of each device connected to the embedded controller, communication address of the embedded controller, and data transmission rate; The device information of the sub-device includes at least the device type of the sub-device being I. 2 C device, the device identifier of each device connected to the sub-device, the communication address of the sub-device, and the data transmission rate.

7. An interrupt handling method, characterized in that, The method, applied to a processor in any one of claims 1-6, comprises: The embedded controller receives a target interrupt signal sent by the embedded controller via the first target bus, wherein the target interrupt signal is an interrupt signal generated by the embedded controller when it detects a target hardware event in the target sub-device of the at least one sub-device via the second target bus; Determine the target driver corresponding to the target interrupt signal, wherein the target driver is the driver of the embedded controller; Based on the target driver, the target event handling method corresponding to the target interrupt signal is determined through the ACPI configuration table; Based on the target driver, the target event handling method is executed.

8. The method according to claim 7, characterized in that, The method for handling the target event corresponding to the target interrupt signal based on the target driver and the ACPI configuration table includes: Based on the target driver, the target event number corresponding to the target interrupt signal is queried through the ACPI configuration table; Based on the target driver, the target event handling method corresponding to the target event number is queried from the ACPI configuration table.

9. The method according to claim 8, characterized in that, The step of querying the target event number corresponding to the target interrupt signal through the ACPI configuration table based on the target driver includes: Based on the target driver, obtain the event queue query instruction corresponding to the target interrupt signal from the ACPI configuration table; The event queue query instruction is sent to the embedded controller via the first target bus, so that the embedded controller, in response to the event queue query instruction, returns the target event number corresponding to the target interrupt signal to the processor via the first target bus. Based on the target driver, the target event number corresponding to the target interrupt signal returned by the embedded controller is received.

10. The method according to claim 7, characterized in that, The method for executing the target event handling based on the target driver includes: Based on the target driver, the target event information and target sub-device identifier corresponding to the target event number are obtained from the target event processing method; Based on the target driver, determine the target device driver corresponding to the target sub-device identifier, and notify the target device driver of the target event information; Based on the target device driver, the target operation corresponding to the target event information is executed.

11. The method according to claim 10, characterized in that, The step of executing the target operation corresponding to the target event information based on the target device driver includes: Based on the target device driver, the target event information is sent to the user space of the operating system; Based on the target management program corresponding to the target event information in the user space, the target operation corresponding to the target event information is executed.

12. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the interrupt handling method as described in any one of claims 7-11.

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