Cache system and method based on silicon interposer structure

Abstract

The invention relates to the field of chips, and discloses a cache system and method based on a silicon interposer structure, and the system comprises a silicon interposer, a computing bare chip, a plurality of HBM stacks, and a cache mapping scheduler embedded in the silicon interposer. The plurality of HBM stacks are distributed on the first surface and / or the second surface of the silicon interposer, and the computing bare chip is located on the first surface; all the HBM stacks in the plurality of HBM stacks are interconnected with the computing bare chip through a photon interconnection structure; or, a part of the HBM stacks in the plurality of HBM stacks are interconnected with the computing bare chip through the photon interconnection structure, and the other part of the HBM stacks are interconnected with the computing bare chip through the electric interconnection structure; the cache mapping scheduler determines the priority of the current cache data so as to map the cache data to a target HBM stack, and the access delay of the target HBM stack is matched with the priority of the current cache data; an interconnect path between the compute die and the target HBM stack is allocated. Signal congestion is reduced and access latency is reduced.

Description

Technical Field

[0001] This application relates to the field of chips, and in particular to a cache system and method based on a silicon interposer structure. Background Technology

[0002] In the field of integrated circuit chips, the deep integration of high-bandwidth memory (HBM) and high-performance processors in heterogeneous systems has become the mainstream trend in the industry. The packaging system of HBM, compute die and silicon interposer is the mainstream packaging system. This architecture has greatly improved the system data throughput and computing efficiency, but it has also made the signal congestion and latency problems caused by traditional redistribution layer (RDL) and through-silicon via (TSV) channels increasingly serious. Summary of the Invention

[0003] The purpose of this application is to provide at least one caching system and method based on silicon interposer structure, which can at least solve the signal congestion and delay problems caused by RDL and TSV channels, and at least achieve the effects of cached data path optimization and latency reduction.

[0004] In a first aspect, this application provides a cache system based on a silicon interposer structure, comprising: a silicon interposer, a computing die, multiple HBM stacks, and a cache mapping scheduler embedded in the silicon interposer; The silicon interposer has a first surface and a second surface opposite to each other, the plurality of HBM stacks are distributed on the first surface and / or the second surface, and the computing die is located on the first surface; All of the plurality of HBM stacks are interconnected with the computing die through a photonic interconnect structure; or, some of the plurality of HBM stacks are interconnected with the computing die through a photonic interconnect structure, and another part of the HBM stacks are interconnected with the computing die through an electrical interconnect structure. The cache mapping scheduler is used to determine the priority of the current cached data, and based on the priority of the current cached data, map the current cached data to a target HBM stack among the plurality of HBM stacks, wherein the access latency of the target HBM stack matches the priority of the current cached data; and allocate an interconnect path between the computing die and the target HBM stack.

[0005] Optionally, among the plurality of HBM stacks, the HBM stack interconnected with the computing die via the photonic interconnect structure has a higher priority for the cached data mapped to it than the HBM stack interconnected via the electrical interconnect structure.

[0006] Optionally, it also includes a photonic wavelength mapping scheduler embedded in the silicon interposer, the photonic wavelength mapping scheduler being used to map the priority of the current cached data to the corresponding target wavelength according to a preset correspondence between the priority of the cached data and the wavelength; The photonic interconnect structure is constructed based on wavelength division multiplexing technology, and includes at least a laser, multiple electro-optic modulators, an optical waveguide structure, at least one photonic switching router, and a multi-channel photodetector. Each of the electro-optic modulators corresponds to one of the HBM stacks; Each channel of the multi-channel photodetector corresponds to one of the HBM stacks; The electro-optic modulator is used to modulate the electrical signal corresponding to the current cached data into an optical signal based on the target wavelength using the laser, and input it into the optical waveguide structure. The at least one photonic switching router is used to select an optical channel matching the target wavelength from the optical waveguide structure according to the target wavelength, so as to route the optical signal of the target wavelength to the channel in the multi-channel photodetector corresponding to the target HBM stack; The multi-channel detector is used to separate the optical signal of the target wavelength from the received optical signal and demodulate it into an electrical signal based on the wavelength demultiplexer for transmission to the target HBM stack.

[0007] Optionally, the optical waveguide structure includes multiple optical waveguides, and the photonic switching router is disposed at the nodes between the optical waveguides; The photonic switching router routes the optical signal of the target wavelength to the channel in the multi-channel photodetector corresponding to the target HBM stack via a tunable ring resonator network.

[0008] Optionally, the optical waveguide structure is specifically used to simultaneously carry optical signals of the target wavelength corresponding to multiple buffered data in one optical channel using wavelength division multiplexing technology, or to transmit optical signals of multiple target wavelengths corresponding to one buffered data in parallel in multiple optical channels.

[0009] Optionally, the optical waveguide structure includes a symmetrical optical waveguide or a multilayered waveguide.

[0010] Optionally, the cache mapping scheduler is further configured to determine, when the priority of cached data stored in the HBM stack is increased, to migrate the stored cached data to an HBM stack whose priority matches that of the stored cached data.

[0011] Optionally, the cache mapping scheduler is specifically used to avoid channels of HBM stacks that are currently saturated when allocating the interconnect path.

[0012] Optionally, the cache mapping scheduler is further configured to determine, when the temperature of the computing die exceeds a first preset temperature, to migrate a portion of the cached data in the HBM stack closest to the computing die to the HBM stack at a distance. When the temperature of the HBM stack exceeds a second preset temperature, it is determined that some cached data in the HBM stack will be migrated to other HBM stacks.

[0013] Secondly, this application provides a caching method based on a silicon interposer structure, applied to any of the above-described caching systems based on a silicon interposer structure, the method comprising: The cache mapping scheduler determines the priority of the current cached data; The cache mapping scheduler maps the current cache data to a target HBM stack from multiple HBM stacks based on the priority of the current cache data; and allocates interconnect paths between the compute die and the target HBM stack.

[0014] The beneficial effects of the embodiments in this application compared with the prior art are: In this application, a caching system based on a silicon interposer structure is provided. The silicon interposer has opposing first and second surfaces. Multiple HBM stacks are distributed on the first and / or second surfaces. The computing die is located on the first surface. All HBM stacks and the computing die are interconnected via photonic interconnect structures. Alternatively, some HBM stacks and the computing die are interconnected via photonic interconnect structures, while others are interconnected via electrical interconnect structures. A cache mapping scheduler in the silicon interposer determines the priority of the current cached data and maps it to a target HBM stack among the multiple HBM stacks based on this priority. The access latency of the target HBM stack is matched with the priority of the current cached data. Then, an interconnect path is allocated between the computing die and the target HBM stack. This allows for optimization of the interconnect path based on the cached data priority, and combined with photonic interconnect paths, reduces signal congestion and lowers access latency.

[0015] It is understandable that the beneficial effects of the second aspect mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0016] One or more embodiments are illustrated by way of example with reference to the accompanying drawings, and these illustrative descriptions do not constitute a limitation on the embodiments.

[0017] Figure 1 This application provides a schematic diagram of a cache system based on a silicon interposer structure as one embodiment; Figure 2 This is a flowchart illustrating a caching method based on a silicon interposer structure, provided in another embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the various embodiments of this application to help readers better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments. The division of the various embodiments below is for the convenience of description and should not constitute any limitation on the specific implementation of this application. The various embodiments can be combined with and referenced by each other without contradiction.

[0019] To facilitate understanding of the embodiments of this application, relevant content regarding the packaging system will be introduced first.

[0020] In the field of integrated circuit chips, the deep integration of HBM and high-performance processors in heterogeneous systems has become the mainstream trend in the industry. The packaging system of HBM, computing die and silicon interposer is the mainstream packaging system. This packaging system generally adopts electrical interconnect structure for PHY-to-PHY communication, and relies entirely on high-speed serial channels such as SerDes. It has limited ability to optimize data priority, dynamic scheduling and power sensitivity, and lacks support for cache-aware routing.

[0021] This application proposes a caching system based on a silicon interposer structure. It is a novel storage interconnect architecture combining silicon photonic interconnects, a double-sided silicon interposer structure, and a cache priority-aware scheduling mechanism to achieve path optimization, latency compression, and improved interconnect energy efficiency for high-priority cached data. A set of photonic communication modules and a cache mapping scheduler are embedded in the silicon interposer to realize cross-layer high-priority cached data mapping, dynamic data redirection, and efficient access path selection.

[0022] The following is a detailed description of the implementation details of the caching system based on the silicon interposer structure in this embodiment. The following content is only for the convenience of understanding and is not necessary for implementing this solution.

[0023] This embodiment provides a caching system based on a silicon interposer structure, such as... Figure 1 As shown, it includes: a silicon interposer 101, a computing die 102, multiple HBM stacks 103, and a cache mapping scheduler 104 embedded in the silicon interposer 101; The silicon interposer 101 has a first surface and a second surface opposite to each other, the plurality of HBM stacks 103 are distributed on the first surface and / or the second surface, and the computing die 102 is located on the first surface; All of the plurality of HBM stacks 103 are interconnected with the computing die 102 through a photonic interconnect structure; or, some of the plurality of HBM stacks 103 are interconnected with the computing die 102 through a photonic interconnect structure, and another part of the HBM stacks 103 are interconnected with the computing die 102 through an electrical interconnect structure. The cache mapping scheduler 104 is used to determine the priority of the current cached data, and according to the priority of the current cached data, map the current cached data to a target HBM stack 103 among the plurality of HBM stacks 103, wherein the access latency of the target HBM stack 103 matches the priority of the current cached data; and allocate an interconnection path between the computing die 102 and the target HBM stack 103.

[0024] The cached data can be key-value cache (KVcache) data, activation graphs, or intermediate feature graphs from a large language model based on a transformer architecture. The compute die 102 contains the main processor and the key-value cache controller.

[0025] The silicon interposer 101 has a first surface and a second surface opposite to each other. HBM stacks 103 can be disposed on the first surface, the second surface, or both surfaces. The computing die 102 is located on the first surface, forming a double-sided silicon interposer structure. For example, five HBM stacks 103 are deployed on the silicon interposer 101, denoted as HBM-A, HBM-B, HBM-C, HBM-D, and HBM-E, forming a 2.5D package structure. Furthermore, a photonic interconnect structure is introduced for die-to-HBM communication, realizing a photonic communication module. Based on this, at least some of the multiple HBM stacks 103 are interconnected with the computing die 102 through the photonic interconnect structure. In one case, all of the multiple HBM stacks 103 are interconnected with the computing die 102 through the photonic interconnect structure. In another scenario, a portion of the multiple HBM stacks 103 are interconnected with the computing die 102 via a photonic interconnect structure, while another portion are interconnected with the computing die 102 via an electrical interconnect structure, thus achieving a hybrid optical-electrical interconnect structure. The electrical interconnect structure includes TSVs and RDLs (including RDLs on the upper and lower surfaces). The access latency between each HBM stack 103 and the computing die 102 is not entirely the same.

[0026] A cache mapping scheduler 104 is embedded in the silicon interposer 101. The cache mapping scheduler 104 determines the priority of the current cached data and maps the current cached data to a target HBM stack among the plurality of HBM stacks 103 according to the priority. Specifically, the current cached data is mapped to the HBM stack 103 whose access latency matches the priority of the cached data. For example, the higher the priority of the cached data, the lower the access latency of the HBM stack 103. The highest priority cached data is mapped to the HBM stack 103 with the lowest access latency.

[0027] For example, cached data is marked as high, medium, and low priority based on key type, model popularity, and access frequency. HBM-A, with the lowest access latency, is located directly below the silicon interposer, having the shortest physical distance to the computation die. The remaining HBM-B, HBM-C, HBM-D, and HBM-E are distributed in different locations. HBM-B and HBM-C have medium access latency, while HBM-D and HBM-E have the longest. High-priority key-value cached data (such as the most recent time step token of a large language model) is preferentially mapped to HBM-A, medium-priority key-value cached data is mapped to HBM-B and HBM-C, and cold data or long-term cached data is mapped to HBM-D and HBM-E.

[0028] In this embodiment, a caching system based on a silicon interposer structure is used. The silicon interposer has a first surface and a second surface. Multiple HBM stacks are distributed on the first surface and / or the second surface. The computing die is located on the first surface. All HBM stacks and the computing die are interconnected via photonic interconnect structures. Alternatively, some HBM stacks and the computing die are interconnected via photonic interconnect structures, while others are interconnected via electrical interconnect structures. A cache mapping scheduler in the silicon interposer determines the priority of the current cached data and maps it to a target HBM stack. The access latency of the target HBM stack is matched with the priority of the current cached data. Then, an interconnection path is allocated between the computing die and the target HBM stack. In this way, the interconnection path can be optimized according to the priority of the cached data. Combined with the photonic interconnection path, signal congestion is reduced and access latency is lowered.

[0029] In some embodiments, among the plurality of HBM stacks, the HBM stack interconnected with the computing die via the photonic interconnect structure has a higher priority for cached data mapped to it than the HBM stack interconnected via the electrical interconnect structure.

[0030] In the electro-optical hybrid interconnect structure, the interconnect path used for transmitting low-priority cached data adopts an electrical interconnect structure. For example, the path for control and low-speed data is implemented using TSV and RDL. The interconnect structure used for transmitting high-priority cached data adopts a photonic interconnect structure. For example, the path for high-frequency, high-priority data is implemented using an embedded photonic interconnect structure. Cached data below or equal to a preset priority threshold is low-priority cached data, and cached data above the preset priority threshold is high-priority cached data. In specific implementations, the paths for high-speed data (e.g., L2 / L3 cache data of the CPU core) and low-speed data can be separated according to the actual situation.

[0031] In this embodiment, the electro-optical hybrid interconnect structure can meet the access latency requirements of cached data with different priorities, while also reducing costs.

[0032] In some embodiments, the caching system based on a silicon interposer structure further includes a photonic wavelength mapping scheduler embedded in the silicon interposer. The photonic wavelength mapping scheduler maps the priority of the current cached data to a corresponding target wavelength according to a preset correspondence between the priority of the cached data and its wavelength. The target wavelength is the wavelength of the optical signal used to transmit the current cached data. For example, the priority of the cached data can be mapped to n different wavelengths λ1 to λ2. n For example, λ1 maps key-value cache data, and λ2 maps intermediate feature maps.

[0033] Accordingly, the photonic interconnect structure is constructed based on wavelength division multiplexing (WDM) technology, and the photonic interconnect structure includes at least a laser, multiple electro-optic modulators, an optical waveguide structure, at least one photonic switching router, and a multi-channel photodetector. Each of the electro-optic modulators corresponds to one of the HBM stacks; Each channel of the multi-channel photodetector corresponds to one of the HBM stacks; The electro-optic modulator is used to modulate the electrical signal corresponding to the current cached data into an optical signal based on the target wavelength using the laser, and input it into the optical waveguide structure. The at least one photonic switching router is used to select an optical channel matching the target wavelength from the optical waveguide structure according to the target wavelength, so as to route the optical signal of the target wavelength to the channel in the multi-channel photodetector corresponding to the target HBM stack; The multi-channel detector is used to separate the optical signal of the target wavelength from the received optical signal and demodulate it into an electrical signal based on the wavelength demultiplexer for transmission to the target HBM stack.

[0034] In practice, the thickness of the silicon interposer is compatible with the optical waveguide structure. For example, the thickness of the silicon interposer is >10um, and it needs to have a special TSV or optical via design.

[0035] Photonic interconnect elements, such as laser sources, electro-optic modulators, optical waveguide structures, demodulators (i.e., multi-channel photodetectors), are embedded in the central region of the silicon interposer. Photonic wavelength mapping schedulers and photonic switching routers are also embedded therein.

[0036] For example, the optical waveguide structure includes a symmetrical optical waveguide or a multi-layered waveguide (3D Optical Routing). The symmetrical optical waveguide connects the HBM stack on the upper and lower surfaces to the computing die along the horizontal direction of the silicon interposer or through the multi-layered waveguide.

[0037] The photonic interconnect structure includes a wavelength division multiplexing interconnect backbone built using an integrated photonic network, coupled with a priority-aware cache scheduling mechanism, to achieve multi-channel, high-speed, hierarchical cache data access. Data routing is implemented between the computing die and multiple HBM stacks based on the priority of the cached data, forming a physical isolation mechanism that serves priority awareness and scheduling control.

[0038] For high-speed data paths, cache access requests from the Central Processing Unit (CPU) or intermediate state results of large language models (such as key-value data in attention mechanisms) are fed into the electro-optic modulator SiPh Tx via circuitry. SiPh Tx modulates the electrical signal into an optical signal, which is then transmitted through an optical waveguide structure within the silicon interposer. A photonic switching router can allocate optical channels within the waveguide structure. The demodulator SiPh Rx (e.g., a multi-channel detector) on the silicon interposer side of the HBM stack, combined with a wavelength demultiplexer, receives and splits the optical signal, demodulating it into an electrical signal near the target HBM stack.

[0039] For example, the optical waveguide structure is specifically used to simultaneously carry optical signals of the target wavelength corresponding to multiple buffered data in one optical channel using wavelength division multiplexing (WDM) technology, or to transmit optical signals of multiple target wavelengths corresponding to one buffered data in parallel across multiple optical channels. In this way, buffered data corresponding to multiple HBM stacks can be aggregated into one optical channel, and multiple heterogeneous buffered streams can be simultaneously carried in one optical channel using WDM technology. Alternatively, high-priority buffered data can be mapped to multiple wavelengths for parallel transmission, with multiple channels splitting one buffered stream, better utilizing the parallel characteristics of the HBM bank layer and improving the transmission speed of large data volumes.

[0040] The Cache Mapper and Multiplexer (MUX) are located in the core area of ​​the silicon interposer layer, coordinating data flow scheduling, high-priority mapping, and dynamic path selection.

[0041] Photonic switching routers can be implemented using either all-optical switching (Photonic Crossbar) or programmable waveguides (Reconfigurable Ring Bus).

[0042] The photonic interconnect structure performs interface protocol conversion with the HBM controller logic, which is implemented at the HBM physical layer level.

[0043] The physical layer of the electrical interconnect between the traditional computing die and the HBM die (PHY-to-PHY communication path) is replaced with a wavelength division multiplexing interconnect backbone built on silicon photonics. Some electrical interconnects (including RDL, TSV, and bumps) are retained for short-distance transmission, power distribution, low-speed control / initialization signals, clock synchronization, or redundant interconnects. In this architecture, multiple high-priority data streams that were originally distributed across multiple bumps can be aggregated into an optical signal through a cache mapping scheduler, passing through a single or a few optical channels. This reduces the number of bumps and area footprint, increases bandwidth density and routing flexibility, and alleviates routing congestion, especially noticeable when accessing key-value caches in high-speed AI models.

[0044] In some embodiments, the optical waveguide structure includes multiple optical waveguides, and the photonic switching router is disposed at the nodes between the optical waveguides; the photonic switching router routes the optical signal of the target wavelength to the channel in the multi-channel photodetector corresponding to the target HBM stack through a tunable ring resonator network.

[0045] Tunable ring resonator networks include microring resonator networks. A microring resonator network consists of multiple micro-resonators. Tunable ring resonator networks can dynamically route optical signals of different wavelengths to the corresponding channels of the target HBM stack. This enables physical layer priority control and path reconfigurability.

[0046] Mapping the priority of cached data to different wavelengths allows high-priority cached data to be scheduled independently, avoiding competition with low-priority cached data for modulator, channel, and buffer resources, thus reducing queuing time. It also allows for the allocation of higher-speed modems or the binding of multiple wavelength channels (wavelength aggregation) to specific wavelengths to ensure high-bandwidth tasks, improving throughput and timeliness. At the receiving end, the wavelengths corresponding to high-priority cached data can be demodulated first, and the cache mapping scheduler prioritizes processing the wavelength channels corresponding to high-priority cached data, reducing scheduling and decoding latency for high-priority cached data.

[0047] In some embodiments, the cache mapping scheduler is further configured to determine, when the priority of cached data stored in the HBM stack is increased, to migrate the stored cached data to an HBM stack whose priority matches that of the stored cached data.

[0048] The cache mapping scheduler supports hardware scheduling and migration of high-priority cached data. When cached data stored in the HBM stack becomes hot data and its priority is increased, the cached data can be dynamically migrated to an HBM stack with lower latency access. For example, it supports prioritizing the scheduling of hot key-value cached data in the token stream to the HBM stack closer to the compute die. This can further reduce inference latency.

[0049] In some embodiments, the cache mapping scheduler is specifically used to avoid channels of HBM stacks that are currently saturated when allocating the interconnect paths. This avoids path conflicts and further reduces latency.

[0050] In some embodiments, the cache mapping scheduler is further configured to determine, when the temperature of the compute die exceeds a first preset temperature, to migrate a portion of the cached data in the HBM stack closest to the compute die to the HBM stack furthest away. When the temperature of the HBM stack exceeds a second preset temperature, it is determined that some cached data in the HBM stack will be migrated to other HBM stacks.

[0051] Some of the cached data can be the lowest priority cached data.

[0052] The first and second preset temperatures can be set according to actual conditions, and no specific limitations are made here.

[0053] A remote HBM stack refers to an HBM stack with a longer access latency than the HBM stack closer to the compute die.

[0054] Other HBM stacks include HBM stacks with temperatures below or equal to a second preset temperature.

[0055] In this embodiment, when the temperature of a certain HBM stack is too high or the temperature of the compute die rises sharply, the cache mapping scheduler will move low-priority cache data away from the HBM stack close to the compute die and put it into the HBM stack at a distance, thereby preventing hot spot aggregation through dynamic storage scheduling of cache data.

[0056] The silicon interposer-based cache structure provided by this solution can significantly shorten the latency of high-priority cache data access, reduce channel congestion, and increase interconnect throughput density. It supports programmable cache scheduling and dynamic migration through a cache mapping scheduler, thereby improving the utilization of the silicon interposer and reducing the package area.

[0057] This embodiment also provides a caching method based on a silicon interposer structure, applicable to caching systems based on silicon interposer structures as described in any of the above embodiments, such as... Figure 2 As shown, the method includes: Step S201: The cache mapping scheduler determines the priority of the current cached data; Step S202: The cache mapping scheduler maps the current cache data to a target HBM stack from multiple HBM stacks according to the priority of the current cache data; and allocates an interconnect path between the computing die and the target HBM stack.

[0058] In some embodiments, the method further includes: When the priority of cached data stored in the HBM stack is increased, the cache mapping scheduler determines to migrate the stored cached data to an HBM stack whose priority matches that of the stored cached data.

[0059] In some embodiments, the method further includes: When allocating the interconnect path, the cache mapping scheduler avoids channels of HBM stacks that are currently saturated.

[0060] In some embodiments, the method further includes: When the temperature of the compute die exceeds a first preset temperature, the cache mapping scheduler determines to migrate a portion of the cached data in the HBM stack closest to the compute die to the HBM stack at a distance; when the temperature of the HBM stack exceeds a second preset temperature, it determines to migrate a portion of the cached data in the HBM stack to other HBM stacks.

[0061] In some embodiments, the method further includes: The photonic wavelength mapping scheduler maps the priority of the current cached data to the corresponding target wavelength according to a preset correspondence between the priority of the cached data and the wavelength. The electro-optic modulator uses the laser to modulate the electrical signal corresponding to the current cached data into an optical signal based on the target wavelength, and inputs it into the optical waveguide structure. The at least one photonic switching router selects an optical channel matching the target wavelength from the optical waveguide structure according to the target wavelength, so as to route the optical signal of the target wavelength to the channel in the multi-channel photodetector corresponding to the target HBM stack; The multi-channel detector, based on a wavelength demultiplexer, separates the optical signal of the target wavelength from the received optical signal and demodulates it into an electrical signal for transmission to the target HBM stack.

[0062] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing this application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of this application.

Claims

1. A caching system based on a silicon interposer structure, characterized in that, include: A silicon interposer, a compute die, multiple HBM stacks, and a cache mapping scheduler embedded in the silicon interposer; The silicon interposer has a first surface and a second surface opposite to each other, the plurality of HBM stacks are distributed on the first surface and / or the second surface, and the computing die is located on the first surface; All of the plurality of HBM stacks are interconnected with the computing die through a photonic interconnect structure; or, some of the plurality of HBM stacks are interconnected with the computing die through a photonic interconnect structure, and another part of the HBM stacks are interconnected with the computing die through an electrical interconnect structure. The cache mapping scheduler is used to determine the priority of the current cached data, and based on the priority of the current cached data, map the current cached data to a target HBM stack among the plurality of HBM stacks, wherein the access latency of the target HBM stack matches the priority of the current cached data; and allocate an interconnect path between the computing die and the target HBM stack.

2. The caching system based on a silicon interposer structure according to claim 1, characterized in that, Among the plurality of HBM stacks, the HBM stacks interconnected with the computing die via the photonic interconnect structure have higher priority for cached data mapped to them than the HBM stacks interconnected via the electrical interconnect structure.

3. The caching system based on a silicon interposer structure according to claim 1 or 2, characterized in that, It also includes a photonic wavelength mapping scheduler embedded in the silicon interposer, which is used to map the priority of the current cached data to the corresponding target wavelength according to a preset correspondence between the priority of the cached data and the wavelength. The photonic interconnect structure is constructed based on wavelength division multiplexing technology, and includes at least a laser, multiple electro-optic modulators, an optical waveguide structure, at least one photonic switching router, and a multi-channel photodetector. Each of the electro-optic modulators corresponds to one of the HBM stacks; Each channel of the multi-channel photodetector corresponds to one of the HBM stacks; The electro-optic modulator is used to modulate the electrical signal corresponding to the current cached data into an optical signal based on the target wavelength using the laser, and input it into the optical waveguide structure. The at least one photonic switching router is used to select an optical channel matching the target wavelength from the optical waveguide structure according to the target wavelength, so as to route the optical signal of the target wavelength to the channel in the multi-channel photodetector corresponding to the target HBM stack; The multi-channel detector is used to separate the optical signal of the target wavelength from the received optical signal and demodulate it into an electrical signal based on the wavelength demultiplexer for transmission to the target HBM stack.

4. The caching system based on a silicon interposer structure according to claim 3, characterized in that, The optical waveguide structure includes multiple optical waveguides, and the photonic switching router is disposed at the node between the optical waveguides. The photonic switching router routes the optical signal of the target wavelength to the channel in the multi-channel photodetector corresponding to the target HBM stack via a tunable ring resonator network.

5. The caching system based on a silicon interposer structure according to claim 3, characterized in that, The optical waveguide structure is specifically used to simultaneously carry optical signals of the target wavelength corresponding to multiple buffered data in one optical channel using wavelength division multiplexing technology, or to transmit optical signals of multiple target wavelengths corresponding to one buffered data in parallel in multiple optical channels.

6. The caching system based on a silicon interposer structure according to claim 3, characterized in that, The optical waveguide structure includes symmetrical optical waveguides or multi-layered waveguides.

7. The caching system based on a silicon interposer structure according to claim 1, characterized in that, The cache mapping scheduler is also configured to determine, when the priority of cached data stored in the HBM stack is increased, to migrate the stored cached data to an HBM stack whose priority matches that of the stored cached data.

8. The caching system based on a silicon interposer structure according to claim 1, characterized in that, The cache mapping scheduler is specifically used to avoid channels of HBM stacks that are currently saturated when allocating the interconnect path.

9. The caching system based on a silicon interposer structure according to claim 1, characterized in that, The cache mapping scheduler is also used to determine, when the temperature of the computing die exceeds a first preset temperature, to migrate a portion of the cached data in the HBM stack close to the computing die to the HBM stack at a distance. When the temperature of the HBM stack exceeds a second preset temperature, it is determined that some cached data in the HBM stack will be migrated to other HBM stacks.

10. A caching method based on a silicon interposer structure, characterized in that, The method, applied to a caching system based on a silicon interposer structure as described in any one of claims 1 to 9, comprises: The cache mapping scheduler determines the priority of the current cached data; The cache mapping scheduler maps the current cache data to a target HBM stack from multiple HBM stacks based on the priority of the current cache data; and allocates interconnect paths between the compute die and the target HBM stack.

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