Reconfigurable SRAM (Static Random Access Memory) storage computing structure

Abstract

The invention discloses a reconfigurable SRAM (Static Random Access Memory) storage and calculation structure, relates to the technical field of storage and calculation, and aims to solve the technical problems of complex calculation unit structure and large area overhead in a reconfigurable SRAM in the prior art. The reconfigurable SRAM storage and calculation structure comprises a storage unit, a calculation unit and an input configuration circuit, the storage unit comprises a cross-coupled inverter and an access transistor; the calculation unit comprises a group of calculation transistors shared by each column; the calculation unit is of a static logic structure; the calculation transistor is connected with the storage unit and the input configuration circuit; and the input configuration circuit is used for configuring an input signal, so that the storage unit and the calculation unit are matched to realize logic AND and logic OR functions. The method is used for reducing the circuit area of the SRAM storage calculation structure.

Description

Technical Field

[0001] This invention relates to the field of storage computing technology, and more particularly to a reconfigurable SRAM storage computing architecture. Background Technology

[0002] With the rapid development of artificial intelligence, the Internet of Things, and edge computing technologies, the traditional von Neumann architecture faces the memory wall bottleneck. In this architecture, data needs to be frequently moved between memory and processor, resulting in high power consumption and long latency in the computing process, which seriously restricts the application and development of related technologies.

[0003] To overcome this limitation, the industry has proposed a storage-computing architecture that embeds computational functions into memory cells, performing operations directly at the data storage location, thereby eliminating data transfer overhead. For SRAM-based storage-computing architectures, the core requirement is to enable SRAM memory cells to simultaneously possess storage and logical computation capabilities. Since the multiplication and accumulation calculation process of neural networks can be implemented through logical AND, OR, and OR operations, SRAM cells must balance storage and logical computation capabilities.

[0004] In existing technologies, research has proposed memory computing methods that separate the computing unit from the storage unit. These methods typically employ a six-transistor SRAM storage unit, while the computing unit consists of a PMOS precharge transistor and a four-transistor pull-down network. By configuring the input data, bitwise operations such as AND, OR, and XOR can be performed. However, this computing unit structure is complex, with a large number of transistors, resulting in a large overall circuit area, which makes it difficult to meet the compact structure requirements of memory computing chips.

[0005] Therefore, there is an urgent need for a reconfigurable SRAM storage and computing structure with a simple structure and small area ratio, which can solve the technical problems of complex computing unit structure and large area overhead in existing reconfigurable SRAM technologies, while realizing logical AND and logical OR functions. Summary of the Invention

[0006] The purpose of this invention is to provide a reconfigurable SRAM storage computing structure to solve the technical problems of complex computing unit structure and large area overhead in existing reconfigurable SRAMs.

[0007] To achieve the above objectives, the present invention provides the following technical solution: This invention provides a reconfigurable SRAM memory computing structure, comprising: a memory cell, a computing unit, and an input configuration circuit; the memory cell includes a cross-coupled inverter and an access transistor; the computing unit includes a set of computing transistors shared by each column; the computing unit is a static logic structure; The computing transistor is connected to the memory cell and the input configuration circuit; the input configuration circuit is used to configure the configuration input signal of the input computing cell, so that the memory cell and the computing transistor cooperate to implement the logical AND and logical OR functions.

[0008] Optionally, the cross-coupled inverter includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor to form a first storage node; the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor to form a second storage node.

[0009] Optionally, the access transistor includes a third NMOS transistor and a fourth NMOS transistor; the drain of the third NMOS transistor is connected to the first memory node; the drain of the fourth NMOS transistor is connected to the second memory node. The gates of the third and fourth NMOS transistors are both connected to the word line; the source of the third NMOS transistor is connected to the bit line; and the source of the fourth NMOS transistor is connected to the bit line.

[0010] Optionally, the configuration input signal includes a first configuration input signal and a second configuration input signal; The computing transistors include the fifth NMOS transistor and the sixth NMOS transistor; The gate of the fifth NMOS transistor is connected to the bit line, and the drain of the fifth NMOS transistor is connected to the first configuration input signal; The gate of the sixth NMOS transistor is connected to the bit line NOT, and the drain of the sixth NMOS transistor is connected to the second configuration input signal; The source of the fifth NMOS transistor and the source of the sixth NMOS transistor are connected together to the signal output terminal of the computing unit.

[0011] Optionally, the first configuration input signal is configured as an operation data signal and the second configuration input signal is configured as 0 through the input configuration circuit. When the first storage node is 0 and the second storage node is 1, the fifth NMOS transistor is turned off and the sixth NMOS transistor is turned on, and the signal output terminal of the computing unit outputs 0. When the first storage node is 1 and the second storage node is 0, the fifth NMOS transistor is turned on and the sixth NMOS transistor is turned off, and the signal output terminal of the computing unit outputs the operation data signal.

[0012] Optionally, the first configuration input signal is configured to be 1 and the second configuration input signal is configured to be an operation data signal through the input configuration circuit. When the first storage node is 0 and the second storage node is 1, the fifth NMOS transistor is turned off and the sixth NMOS transistor is turned on, and the signal output terminal of the computing unit outputs the operation data signal. When the first storage node is 1 and the second storage node is 0, the fifth NMOS transistor is turned on and the sixth NMOS transistor is turned off, and the signal output terminal of the computing unit outputs 1.

[0013] Optionally, the input configuration circuit includes a first data selector, a second data selector, a first D flip-flop, and a second D flip-flop; wherein the first data selector and the second data selector are both two-to-one selectors; The output of the first data selector is connected to the signal input of the first D flip-flop, and the output of the second data selector is connected to the signal input of the second D flip-flop.

[0014] Optionally, both the first data selector and the second data selector are connected to the operational data signal, and the first data selector and the second data selector, under the control of the first control signal and the second control signal, respectively select to output the operational data signal or a fixed level. The two selected signals are input to the first D flip-flop and the second D flip-flop respectively. When triggered by the rising edge of the clock, the first D flip-flop and the second D flip-flop output the first configuration input signal and the second configuration input signal respectively, thereby completing the selection of AND mode and OR mode.

[0015] Optionally, when the word line is low, the access transistor is turned off, and the first and second storage nodes are disconnected from the corresponding bit lines, respectively, to achieve data retention.

[0016] Optionally, before the read operation, the bit line and bit line NOT are precharged to a high level; during the read operation, the word line is set to a high level to turn on the access transistor. The complementary levels stored in the memory cell will cause one of the bit line and bit line NOT to form a discharge path to ground through the turned access transistor and generate a read current, while the other has no current due to the lack of voltage difference. The level difference between the bit line and bit line NOT is amplified by the sensitive amplifier to output a full-swing signal and complete the read operation.

[0017] Compared to existing technologies, the reconfigurable SRAM memory computing structure provided by this invention requires only one set of computing transistors shared by each column for the computing unit. This eliminates the need for the complex structure of PMOS precharge transistors and four-transistor pull-down networks found in existing technologies, significantly reducing the number of transistors and simplifying the circuitry and area footprint from a hardware perspective. Furthermore, the computing transistors are directly connected to the memory cells, eliminating the need for separate configurations and avoiding space waste caused by additional circuit connections, resulting in a more compact overall structure. In addition, by configuring input signals through the input configuration circuit, the memory cells and computing units can directly implement logical AND and OR functions without the need for additional inverters, complex control modules, or other redundant circuits. This maximizes area reduction while meeting core computing requirements. Ultimately, through structural simplification and integrated design, the area overhead problem of existing reconfigurable SRAM computing units is completely solved. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 A schematic diagram of a reconfigurable SRAM storage computing structure provided for one embodiment of the present invention; Figure 2 A diagram showing the holding operation state is provided for one embodiment of the present invention; Figure 3 One of the read operation state diagrams provided in an embodiment of the present invention; Figure 4 A second read operation state diagram provided for one embodiment of the present invention; Figure 5 One of the write operation state diagrams provided in an embodiment of the present invention; Figure 6 A second write operation state diagram provided for one embodiment of the present invention; Figure 7 One of the computational operation state diagrams provided in an embodiment of the present invention; Figure 8 A second computational operation state diagram provided for one embodiment of the present invention; Figure 9 This is a schematic diagram of the structure of an input configuration circuit provided in one embodiment of the present invention.

[0019] Reference numerals: 1-Storage unit; 2-Computation unit; 3-Input configuration circuit; 4-First data selector; 5-Second data selector; 6-First D flip-flop; 7-Second D flip-flop. Detailed Implementation

[0020] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0021] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0022] In this invention, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between the associated objects, indicating that three relationships can exist.

[0023] like Figure 1 As shown, this embodiment of the invention provides a reconfigurable SRAM storage and computing structure, which may include: a storage unit 1, a computing unit 2, and an input configuration circuit 3; the storage unit 1 includes a cross-coupled inverter and an access transistor; the computing unit 2 includes a set of computing transistors shared by each column; the computing unit is a static logic structure. The computing transistor is connected to the memory cell and the input configuration circuit; the input configuration circuit is used to configure the configuration input signal of the input computing cell, so that the memory cell and the computing transistor cooperate to implement the logical AND and logical OR functions.

[0024] See Figure 1 It is understandable that in a reconfigurable SRAM memory computing architecture, a set of computing transistors and an input configuration circuit are shared by a column of memory cells, and a column of memory cells includes at least one memory cell.

[0025] Specifically, the storage nodes include a first storage node Q and a second storage node QB. See also Figure 1 As can be seen, the cross-coupled inverter includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN2; the drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1 to form a first storage node Q; the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2 to form a second storage node QB; the source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are both connected to the power supply VDD.

[0026] The gates of the first PMOS transistor MP1 and the first NMOS transistor MN1 are connected and then connected to the second memory node QB. The gates of the second PMOS transistor MP2 and the second NMOS transistor MN2 are connected and then connected to the first memory node Q. The drains of the first NMOS transistor MN1 and the second NMOS transistor MN2 are both grounded.

[0027] See Figure 1 It can be seen that the access transistors include a third NMOS transistor MN3 and a fourth NMOS transistor MN4; the drain of the third NMOS transistor MN3 is connected to the first memory node; the drain of the fourth NMOS transistor MN4 is connected to the second memory node; the gates of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are both connected to the word line WL; the source of the third NMOS transistor MN3 is connected to the bit line BL; and the source of the fourth NMOS transistor MN4 is connected to the bit line ∠BLB.

[0028] The configuration input signals include a first configuration input signal and a second configuration input signal; see [link / reference] Figure 1 It is known that the computing transistors include a fifth NMOS transistor and a sixth NMOS transistor; the gate of the fifth NMOS transistor is connected to a bit line, and the drain of the fifth NMOS transistor is connected to a first configuration input signal; the gate of the sixth NMOS transistor is connected to a non-BLB bit line, and the drain of the sixth NMOS transistor is connected to a second configuration input signal; the source of the fifth NMOS transistor and the source of the sixth NMOS transistor are connected together to the signal output terminal of computing unit 2.

[0029] See Figure 2 In specific implementation, when the reconfigurable SRAM storage computing structure performs a hold operation, the word line WL is set to a low level. When the word line WL is low, the access transistor is turned off, and the first and second storage nodes are not disconnected from the corresponding bit lines, respectively. They cannot read signals or write signals, that is, the storage nodes are not coupled to external signals, so as to achieve data retention.

[0030] In practical implementation, when the reconfigurable SRAM memory computing structure performs a read operation, firstly, before the read operation, the bit line BL and the non-BLB bit line are pre-charged to a high level; secondly, during the read operation, the word line WL is set to a high level, causing the access transistors MN3 and MN4 to conduct. The complementary levels stored in the memory cell cause one of the bit lines BL and the non-BLB bit line to form a discharge path to ground through the conducting access transistor and generate a read current, while the other line has no current due to the lack of voltage difference. The level difference between the bit line BL and the non-BLB bit line is amplified by a sensitive amplifier, and a full-swing signal is output to complete the read operation.

[0031] Read operations can be divided into the following two data storage scenarios: Case 1: See Figure 3 The storage unit stores the data "1", that is, the storage node Q=1 and QB=0. 0 represents a low level and 1 represents a high level, which will not be repeated below.

[0032] Before the read operation, BL and BLB are precharged to high level, WL is initially low level, MN3 and MN4 are disconnected, and the memory cell is isolated from the bit line; when WL is set high, MN3 and MN4 are turned on, and the memory cell is connected to the bit line.

[0033] On the non-BLB side of the bit line: Since QB=0, and BLB is high level after pre-charging, there is a voltage difference between the source (BLB side) and drain (QB side) of MN4. MN4 is turned on, and the current flows from BLB to MN4 to QB (QB is at 0 level, equivalent to ground). The level of BLB is pulled low and a read current is generated.

[0034] Bit line BL side: Since Q=1, it is consistent with the BL level after pre-charging. There is no voltage difference between the source (BL side) and drain (Q side) of MN3. MN3 is effectively disconnected. BL maintains the high level of pre-charging and has no current.

[0035] Ultimately, BL remains high and BLB is pulled low. The sensitive amplifier amplifies the level difference between the two and outputs the data "1".

[0036] Case 2: See Figure 4 The storage unit stores data "0", that is, storage node Q=0, QB=1.

[0037] Before the read operation, BL and BLB are precharged to high level, WL is initially low level, and MN3 and MN4 are disconnected; when WL is set high, MN3 and MN4 are turned on, and the memory cell is connected to the bit line.

[0038] Bit line BL side: Since Q=0, and BL is high level after pre-charging, there is a voltage difference between the source (BL side) and drain (Q side) of MN3. MN3 is turned on, and the current flows from BL→MN3→Q. Q is at 0 level, which is equivalent to ground. The level of BL is pulled low and a read current is generated.

[0039] On the non-BLB side of the bit line: Since QB=1, it is consistent with the pre-charged BLB level. There is no voltage difference between the source (BLB side) and drain (QB side) of MN4. MN4 is effectively disconnected, and BLB maintains the pre-charged high level with no current.

[0040] Ultimately, BLB remains high while BL is pulled low, and the sensitive amplifier amplifies the level difference between the two, outputting data "0".

[0041] In practice, data writing operations are also involved. These include two scenarios: writing 0 and writing 1.

[0042] In the first case, the "0" write operation aims to eventually stabilize the storage unit at Q=0 and QB=1.

[0043] See Figure 5 Before the write operation, the memory cell contains the old data "1", that is, the first memory node Q is kept at 1 (high level) and the second memory node QB is kept at 0 (low level). At this time, the bit line BL and the non-BLB bit line are in an idle state, the word line WL is at a low level, the access transistors MN3 and MN4 are disconnected, and the memory cell and the bit line are isolated from each other.

[0044] When writing "0", the input module first sets BL to 0 and BLB to 1, then sets the word line WL to high level, turning on MN3 and MN4, connecting the memory cell and the bit line. At this time, Q is originally high level and BL is low level. The two form a path through MN3, and the high level of Q flows to BL, Q begins to discharge, and the level gradually decreases. Meanwhile, QB is originally low level and BLB is high level. The two form a path through MN4, and the high level of BLB flows to QB, QB begins to charge, and the level gradually increases.

[0045] Then the positive feedback of the cross-coupled inverter kicks in: a decrease in Q level lowers the gate level of the second PMOS transistor MP2, turning MP2 on. The high level of VDD charges QB through MP2, further increasing the QB level. The increase in QB level, in turn, raises the gate level of MN1, turning on NMOS transistor MN1. Q is grounded through MN1, further decreasing the level. This positive feedback loop of "Q decreases → QB increases → Q decreases further → QB increases further" continues to strengthen until Q rapidly drops to 0 and QB rapidly rises to 1.

[0046] When Q is stable at 0 and QB is stable at 1, the cross-coupled inverter enters a new latch state, and the memory cell is successfully written with "0". After that, WL returns to low level, MN3 and MN4 are disconnected, the memory cell is isolated from the bit line, and the data that was just written is retained.

[0047] In the second case, the "1" is written, with the goal that the storage unit eventually stabilizes at Q=1 and QB=0.

[0048] See Figure 6 Before the write operation, the storage cell contains the old data "0", the first storage node Q is kept at 0 and the second storage node QB is kept at 1; the bit line BL and the non-BLB bit line are idle, the word line WL is low, MN3 and MN4 are disconnected, and the storage cell is isolated from the bit line.

[0049] When writing a "1", the input module first sets BL to 1 and BLB to 0, then sets WL to a high level, turning on MN3 and MN4, connecting the storage unit to the bit line. At this time, QB is originally at a high level and BLB is at a low level. The two form a path through MN4, and the high level of QB flows to BLB, causing QB to start discharging and its level to gradually decrease. Meanwhile, Q is originally at a low level and BL is at a high level. The two form a path through MN3, and the high level of BL flows to Q, causing Q to start charging and its level to gradually increase.

[0050] Then, the positive feedback of the cross-coupled inverter is activated: the increase in the Q level of the first storage node causes the gate level of the second PMOS transistor MP2 to go high, turning MP2 off. At the same time, the gate level of MN2 goes high, turning on the NMOS transistor MN2. QB is grounded through MN2, and the level further decreases. The decrease in the QB level causes the gate level of MN1 to go low, turning off the NMOS transistor MN1. At the same time, the gate level of MP1 goes low, turning on the PMOS transistor MP1. The high level of VDD charges Q through MP1, causing the Q level to rise further. This cycle of "Q rises → QB falls → Q rises even more → QB falls even more" continues to reinforce until Q rises rapidly to 1 and QB falls rapidly to 0.

[0051] When Q is stable at 1 and QB is stable at 0, the cross-coupled inverter enters a new latch state, and the memory cell is successfully written with "1". After that, WL returns to low level, MN3 and MN4 are disconnected, the memory cell is isolated from the bit line, and the data that was just written is retained.

[0052] In the implementation of logical AND, see Figure 7 The first configuration input signal IN1 is configured to be the operation data signal IN and the second configuration input signal IN2 is configured to be 0 through the input configuration circuit. When the first storage node Q is 0 and the second storage node QB is 1, the fifth NMOS transistor MN5 is turned off and the sixth NMOS transistor MN6 is turned on, and the signal output terminal outputs 0; when the first storage node Q is 1 and the second storage node QB is 0, the fifth NMOS transistor MN5 is turned on and the sixth NMOS transistor MN6 is turned off, and the signal output terminal of the computing unit outputs the operation data signal IN.

[0053] In practice, during the calculation operation, the word line WL is set high, which turns on the access transistors MN3 and MN4. The complementary states of the first storage node Q and the second storage node QB are transmitted to the bit line BL and the bit line not BLB through MN3 and MN4, respectively. Then, the result of the AND logic operation is directly output through the turn-on and turn-off logic of the calculation transistors MN5 and MN6.

[0054] When the first storage node Q=0 and the second storage node QB=1, the low level of Q is transmitted to BL through MN3, making BL=0, and the high level of QB is transmitted to BLB through MN4, making BLB=1. MN5 acts as an NMOS transistor. The gate (g) of MN5 is connected to the low level of BL=0, the drain (D) of MN5 is connected to IN1=IN (potential is 0 or 1), and the source (S) of MN5 is connected to OUT. The NMOS conduction condition is "Vg≥Vs+Vth": at this time, Vs (initial potential of OUT ≈ 0), Vg=0, 0≥0+Vth does not hold, so MN5 is turned off, cutting off the path between IN1 and OUT. Here, Vg is the gate voltage, Vs is the source voltage, and Vth is the threshold voltage.

[0055] MN6 is also an NMOS transistor. The gate of MN6 is connected to the high level of BLB=1, the drain of MN6 is connected to the fixed low level of IN2=0, and the source of MN6 is connected to OUT. Vs=0, Vg=1≥0+Vth, the conduction condition is met, MN6 conducts and forms the path "IN2 (D=0)→S→OUT". The fixed low level of IN2 is transmitted to OUT through the conducting MN6, causing OUT to be pulled to 0. The operation rule of matching and logic "0×IN=0" is met, without any additional inversion or conversion steps.

[0056] When the first storage node Q=1 and the second storage node QB=0, the high level of Q is transmitted to BL through MN3 to make BL=1, and the low level of QB is transmitted to BLB through MN4 to make BLB=0; the gate of MN6 is connected to the low level of BLB=0, the drain of MN6 is connected to the fixed low level of IN2=0, the source of MN6 is connected to OUT, Vg=0≥Vs(0)+Vth does not hold, MN6 is turned off and the path between IN2 and OUT is cut off.

[0057] The gate of MN5 is connected to a high level (BL=1), the drain of MN5 is connected to IN1=IN (potential is 0 or 1), and the source of MN5 is connected to OUT. When IN=0, the drain of MN5 D=0, Vg=1≥0+Vth, the conduction condition is met, MN5 conducts, and the 0 of IN1 is transferred to OUT through the drain D→source S, outputting 0; when IN=1, the drain of MN5 D=1, Vg=1≥0+Vth (Vs is still the initial potential of OUT 0, which is independent of the potential of D), the conduction condition is still met, MN5 conducts, and the 1 of IN1 is transferred to OUT through D→S, outputting 1; making the potential of OUT completely follow the potential change of IN, directly reflecting the core rule of the AND logic "1×IN=IN".

[0058] In the implementation of logical OR, see Figure 8 The first configuration input signal IN1 is configured to be 1 and the second configuration input signal IN2 is configured to be the operation data signal IN through the input configuration circuit. When the first storage node Q is 0 and the second storage node QB is 1, the fifth NMOS transistor MN5 is turned off and the sixth NMOS transistor MN6 is turned on, and the signal output terminal of the computing unit outputs the operation data signal IN; when the first storage node Q is 1 and the second storage node QB is 0, the fifth NMOS transistor MN5 is turned on and the sixth NMOS transistor MN6 is turned off, and the signal output terminal of the computing unit outputs 1.

[0059] In practice, during the calculation operation, the word line WL is set high, which turns on the access transistors MN3 and MN4. The complementary states of the first storage node Q and the second storage node QB are transmitted to the bit line BL and the bit line not BLB through MN3 and MN4, respectively. Then, the result of the OR logic operation is directly output through the turn-on and turn-off logic of the calculation transistors MN5 and MN6.

[0060] When the first storage node Q=0 and the second storage node QB=1, the low level of Q is transmitted to BL through MN3, making BL=0, and the high level of QB is transmitted to BLB through MN4, making BLB=1. MN5 is an NMOS transistor. The gate of MN5 is connected to the low level of BL=0, the drain of MN5 is connected to the fixed high level of IN1=1, and the source of MN5 is connected to OUT. According to the NMOS conduction condition Vg≥Vs+Vth, at this time Vs (OUT initial potential≈0), Vg=0, 0≥0+Vth does not hold. Therefore, MN5 is turned off, cutting off the path between IN1 (IN1=1) and the signal output terminal OUT.

[0061] MN6 is also an NMOS transistor. The gate of MN6 is connected to a high level of BLB=1, the drain of MN6 is connected to IN2=IN (potential is 0 or 1), and the source of MN6 is connected to OUT. Vs=0, Vg=1≥0+Vth, the conduction condition is met, MN6 conducts and forms a path of "IN2 (D=IN)→S→OUT". The potential of IN is transmitted to OUT through the conducting MN6, so that OUT follows the potential change of IN. The operation rule of matching OR logic "0+IN=IN" is met without any additional inversion or conversion steps.

[0062] When the first storage node Q=1 and the second storage node QB=0, the high level of Q is transmitted to BL through MN3 to make BL=1, and the low level of QB is transmitted to BLB through MN4 to make BLB=0; the gate of MN6 is connected to the low level of BLB=0, the drain of MN6 is connected to IN2=IN (potential is 0 or 1), the source of MN6 is connected to OUT, Vg=0≥Vs(0)+Vth does not hold, MN6 is turned off and cuts off the path between IN2 (IN2=IN) and OUT; the gate of MN5 is connected to the high level of BL=1, the drain of MN5 is connected to the fixed high level of IN1=1, the source of MN5 is connected to OUT, and its conduction state is determined by “Vg≥Vs+Vth” (Vs is the OUT potential, initially ≈0): Vg=1≥0+Vth, the conduction condition is met, MN5 conducts, the 1 of IN1 is transmitted to OUT through D→S, output 1, directly reflecting the core rule of OR logic “1+IN=1”.

[0063] It should be noted that static logic refers to periodic pre-charge / discharge without clock signal drive. Stable logic output can be achieved solely through the on / off state of transistors, and the output state is uniquely determined by the input signal and circuit topology. This is the core design logic of the computing unit of this invention. During operation, the computing unit of this invention does not rely on clock signals for control. It precisely controls the on / off state of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 by simply configuring the complementary states of the input signals IN1 / IN2 and the storage nodes Q / QB. It eliminates the need for pre-charge transistors required for dynamic logic and a dedicated discharge network, thus structurally eliminating dependence on clock signals. Furthermore, the output of the computing unit is unique and stable. In AND mode, the output is fixed at 0 when Q=0 and follows the operation data signal IN when Q=1. In OR mode, the output is fixed at 1 when Q=1 and follows the operation data signal IN when Q=0. The output state is not lost due to signal drift or charge leakage throughout the process.

[0064] Furthermore, since there is no need for periodic pre-charging and discharging operations, the computing unit of the present invention also avoids the inherent defects such as charge leakage and clock feedthrough that are common in dynamic logic. The switching activity of the transistors is lower, which not only matches the high reliability characteristics of static logic, but also effectively reduces power consumption, making the overall circuit performance more suitable for the needs of storage computing scenarios.

[0065] Analysis of the beneficial effects of this implementation: 1) Precisely overcomes the problems of complex structure and large area overhead in existing technologies. This invention fundamentally solves the core defects of complex structure and large area overhead in existing reconfigurable SRAMs through a simplified computing unit design and integrated storage and computing architecture. Each computing unit in existing technologies needs to be composed of a PMOS precharge transistor and a transistor pull-down network (the transistor pull-down network includes at least 5 transistors), and an additional inverter is required to implement AND / OR logic, resulting in redundant transistors and a bloated structure. In contrast, the computing unit of this invention only needs to share a set of computing transistors per column, and the number of computing transistors in a set is less than the number of existing computing units. That is, there is no need for complex components such as precharge transistors and pull-down networks, which greatly reduces the number of transistors in the computing unit and achieves extreme simplification in hardware structure. Meanwhile, this invention directly connects the computing transistor to the memory cell, adopting an integrated storage and computing design. This avoids the additional circuit connections and space occupation caused by the separate setting of the memory cell and computing cell in the prior art, making the overall structure more compact. Furthermore, the AND / OR logic output is directly realized through the input configuration circuit without the need for additional inverter conversion, further reducing the area waste of redundant circuits. Ultimately, with only two additional transistors, the minimalist design meets the requirements of logical AND and logical OR functions while maximizing the reduction of area ratio, perfectly meeting the compact structure requirements of storage and computing chips.

[0066] 2) Static logic design reduces dynamic power consumption and static losses. Existing technologies use dynamic logic circuits, relying on clock signals to control periodic pre-charging and discharging operations, resulting in high circuit switching activity and significant dynamic power consumption. Furthermore, dynamic logic is susceptible to issues such as charge leakage and charge sharing, further increasing power consumption. This invention employs a static logic architecture, where the calculation process directly achieves signal transmission and logic operations through the on / off switching of transistors, eliminating the need for clock-driven periodic charging and discharging, thus significantly reducing dynamic power consumption caused by switching activity. Simultaneously, the static logic structure is more stable, reducing static losses caused by issues such as charge leakage. Compared to existing dynamic logic designs, it offers a more advantageous overall power consumption and is better suited to the needs of low-power scenarios such as the Internet of Things and edge computing.

[0067] 3) Direct output of target logic, reducing latency overhead. Existing computing units directly output NAND or NOR results, requiring additional inverters for signal conversion to obtain AND / OR logic. This extra step not only increases area but also introduces signal delay. This invention, through the collaborative design of storage and computing units, leverages the complementary states of storage nodes Q and QB and the conduction logic of computing transistors to directly output the final results of AND and OR logic without any intermediate conversion steps. This shortens the signal transmission path and computation cycle, improves the real-time performance of storage computation, and is more suitable for scenarios with high computational efficiency requirements, such as neural network multiplication and accumulation.

[0068] 4) Simplified structure reduces failure risk and adapts to complex application environments. Existing computing units contain multiple transistors and complex pull-down networks, and dynamic logic is more sensitive to interference such as charge leakage and capacitive coupling, resulting in lower circuit reliability. The computing unit structure of this invention is extremely simple, reducing the number of transistors and circuit connection nodes, thus reducing the risk of computational errors due to the failure of a single device or line interference. At the same time, the static logic architecture itself has stronger anti-interference capabilities and is not affected by dynamic logic-specific problems such as clock feedthrough, significantly improving circuit stability and reliability, and adapting to complex application environments with high requirements for operational stability, such as industrial control and smart terminals.

[0069] 5) Superior scalability and compatibility. The computing unit of this invention adopts a modular design shared by each column. The input configuration circuit can flexibly switch AND / OR logic functions through control signals without modifying the core hardware structure, resulting in stronger scalability. At the same time, the storage unit retains the basic hold, read, and write functions of traditional 6TSRAM. While adding computing functions, it does not affect the original storage performance, and is compatible with existing SRAM array designs, reducing the cost of technology upgrades and product iterations. It can be widely used in diverse storage and computing scenarios such as AI chips, edge computing devices, and IoT terminals.

[0070] In an exemplary embodiment, see Figure 9 The input configuration circuit includes a first data selector 4, a second data selector 5, a first D flip-flop 6, and a second D flip-flop 7; wherein the first data selector 4 and the second data selector 5 are both two-to-one selectors.

[0071] The output of the first data selector 4 is connected to the signal input of the first D flip-flop 6, and the output of the second data selector 5 is connected to the signal input of the second D flip-flop 7.

[0072] The first data selector 4 and the second data selector 5 are both connected to the operational data signal IN, and under the control of the first control signal CLR_P_H and the second control signal CLR_N_H respectively, they select to output the operational data signal IN or a fixed level; fixed to 0 or 1.

[0073] The two selected signals are input to the first D flip-flop 6 and the second D flip-flop 7 respectively. When triggered by the rising edge of the clock, the first D flip-flop 6 and the second D flip-flop 7 output the first configuration input signal IN1 and the second configuration input signal IN2 respectively, thereby completing the selection of AND mode and OR mode.

[0074] See details Figure 9It can be seen that the input terminal "IN1" of the first data selector 4 is connected to the operational data signal IN, and the input terminal "IN2" is connected to the power supply VDD. That is, the two selectable inputs are "operational data IN" or "fixed level 1".

[0075] The control terminal "CLR_P_H" of the first data selector 4 is the selection control terminal, and its level state determines whether the selector is turned on "IN" or "VDD".

[0076] The output terminal of the first data selector 4 is directly connected to the signal input terminal of the first D flip-flop 6 to transmit the selected signal.

[0077] See Figure 9 The second data selector 5 has its input terminal “IN1” connected to the operational data signal IN, and its input terminal “IN2” connected to the ground terminal GND (corresponding to a fixed level 0). That is, the two selectable inputs are “operational data IN” or “fixed level 0”.

[0078] The control terminal "CLR_N_H" of the second data selector 5 is the selection control terminal, and its level state determines whether the selector is turned on "IN" or "GND".

[0079] The output terminal of the second data selector 5 is directly connected to the signal input terminal of the second D flip-flop 7 to transmit the selected signal.

[0080] See Figure 9 The terminals of the first D flip-flop 6 and the second D flip-flop 7 have the same structure and synchronized function: the signal input terminal "D" receives the signal output from the corresponding data selector (first selector → first flip-flop, second selector → second flip-flop); the clock input terminal "CLK" allows the two flip-flops to share the same clock signal for synchronous trigger signal latching (latching is performed only on the rising edge of the clock); the signal output terminal "Q" outputs the first configuration input signal IN1 and the second configuration input signal IN2 respectively, providing mode configuration input signals for the computing unit.

[0081] Table 1: Truth table for memory cell calculation under different configurations It should be noted that Table 1, serving as the "control signal-configuration input signal" mapping rule table for the input configuration circuit, clarifies the correspondence between different combinations of control signals and the output values ​​of IN1 and IN2, and is the core logical basis for achieving precise switching between AND and OR modes. The 2-to-1 data selector acts like an "electronic switch," determining the conduction path based on the level of the control signal, while the D flip-flop stably latches the selector's output signal as IN1 and IN2 at the rising edge of the clock, preventing signal fluctuations from affecting operational stability. Together with the rules in Table 1, the mode configuration can be completed.

[0082] The implementation logic of the AND mode is as follows: According to the definition in Table 1, when the control signal combination is CLR_P_H=0 and CLR_N_H=1, the system triggers the "AND mode" configuration. At this time, under the control of CLR_P_H=0, the first data selector selects to connect the operation data signal IN and outputs it; under the control of CLR_N_H=1, the second data selector selects to connect the fixed level 0 and outputs it. After the rising edge of the clock arrives, the first D flip-flop latches and outputs IN1=IN, and the second D flip-flop latches and outputs IN2=0. Combining the core rule of the AND operation that "the output is 1 only when all inputs are 1", this configuration, in conjunction with the complementary states of the storage nodes Q / QB, allows the computing unit to finally output the AND logic result of "IN×Q". For example, when Q=1, the output is consistent with IN, and when Q=0, the output is fixed as 0, which meets the logical requirements of the AND operation.

[0083] The implementation logic of OR mode. When the control signal combination is CLR_P_H=1 and CLR_N_H=0, the OR mode configuration is entered according to the rules in Table 1. At this time, the first data selector, under the control of CLR_P_H=1, selects to connect a fixed level 1 and outputs; the second data selector, under the control of CLR_N_H=0, selects to connect the operation data signal IN and outputs. After the rising edge of the clock triggers, the first D flip-flop outputs IN1=1, and the second D flip-flop outputs IN2=IN. According to the OR operation rule that "the output is 1 when any input is 1", this configuration works in conjunction with the complementary states of the storage node Q / QB to make the computing unit output the OR logic result of "IN+Q". For example, when Q=1, the output is fixed as 1, and when Q=0, the output is consistent with IN, precisely matching the logic characteristics of the OR operation.

[0084] In short, the input configuration circuit is the hardware carrier for mode switching, and Table 1 is the logical basis for clarifying the control rules. The two are combined through the process of "control signal gating → selector output → trigger latch" to stably output the IN1 and IN2 required for the target mode, and finally realize the reliable switching of the computing unit between AND mode and OR mode.

[0085] The beneficial effects of this embodiment are as follows: 1) Eliminate the high power consumption problem of dynamic logic and reduce switching activity. Existing computing units rely on dynamic logic, which requires clock signals to control periodic pre-charging and discharging. Each cycle involves signal flipping, resulting in high switching activity and significant total power consumption.

[0086] Although the input configuration circuit of this embodiment includes a clock-triggered D flip-flop, its core function implements a "pre-charge-discharge" cycle without dynamic logic: the 2-to-1 data selector statically selects the path based solely on the control signals CLR_P_H / CLR_N_H, without periodic level switching; the D flip-flop latches the signal only once on the rising edge of the clock, rather than continuously participating in the computation cycle. Combined with the static logic architecture of the computing unit, that is, by directly implementing AND / OR logic through the on / off state of MN5 / MN6, the overall circuit switching activity is significantly reduced, and the dynamic power consumption is significantly lower than that of existing dynamic logic solutions.

[0087] 2) Mitigating reliability risks of dynamic logic and improving operational stability. Existing dynamic logic is susceptible to issues such as charge leakage, charge sharing, and clock feedthrough. After precharging, node charge may be lost due to leakage, charge sharing between different nodes may lead to abnormal levels, and the coupling of clock signals and data signals may also cause feedthrough interference, ultimately reducing operational reliability.

[0088] This embodiment avoids the aforementioned risks at their source by using a static gating data selector and a D flip-flop latch design. Firstly, the path selection of the 2-to-1 data selector is directly determined by the control signal, eliminating the need for charge storage to maintain its state and preventing charge leakage and sharing issues. Secondly, the D flip-flop stably latches the configuration input signals IN1 / IN2 on the rising edge of the clock, ensuring stable output signal amplitude and eliminating clock-data coupling interference in dynamic logic, thus naturally eliminating clock feedthrough problems. Furthermore, the unique mapping relationship between "control signal - configuration input signal" clearly defined in Table 1 ensures that the IN1 / IN2 outputs will not deviate from the target value due to signal fluctuations, further improving operational reliability.

[0089] 3) Simplify the circuit structure, reduce area overhead, and avoid dependence on additional inverters.

[0090] The existing technology has two major area drawbacks: First, the computing unit requires a PMOS pre-charge transistor + a four-transistor pull-down network (a total of 5 transistors), which makes the structure complex; second, it directly outputs the AND / OR result, which requires an additional inverter to obtain the AND / OR logic, further increasing the area.

[0091] This embodiment optimizes area in two ways. ① Simplified input configuration circuit design: It uses only two 2-to-1 data selectors and two D flip-flops, eliminating the inverters found in existing input configuration circuits and reducing redundant components. Furthermore, the data selectors only need to select IN or a fixed level based on the control signal, eliminating the need for complex topologies and resulting in a more compact hardware structure. ② No need for additional inverter conversion: Through the configuration rules defined in Table 1, combined with the MN5 / MN6 conduction logic of the computing unit, the AND / OR logic result can be directly output. For example, in AND mode, OUT=IN when Q=1 and OUT=0 when Q=0; in OR mode, OUT=1 when Q=1 and OUT=IN when Q=0. Unlike existing technologies, there is no need to invert the AND / OR results, completely eliminating the area overhead of additional inverters. Compared to a traditional 6TSRAM cell, it only adds two computing transistors, MN5 and MN6, resulting in a significant area advantage.

[0092] 4) Improve the flexibility of mode switching and the adaptability of operation.

[0093] While existing computing units can perform AND, OR, and XOR operations, they require complex input data reconstruction. For example, OR mode requires configuring INP=0 and INN=IN NOT, and it relies on a separate architecture for computing and storage units, resulting in poor hardware adaptability for mode switching.

[0094] This embodiment achieves flexible mode switching through control signals and the rules in Table 1: only the level combination of CLR_P_H and CLR_N_H needs to be adjusted. For example, CLR_P_H=0, CLR_N_H=1 corresponds to AND mode, and CLR_P_H=1, CLR_N_H=0 corresponds to OR mode. The target path can be selected by the data selector, and then the stable combination of IN1 and IN2 is latched by the D flip-flop without modifying the hardware structure. This design not only adapts to the core requirements of neural network multiplication and accumulation calculations for AND and OR logic, but also quickly responds to the switching needs of different operation scenarios, improving the practicality and adaptability of the SRAM storage computing architecture.

[0095] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0096] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A reconfigurable SRAM storage computing architecture, characterized in that, include: The system includes a storage unit, a computing unit, and an input configuration circuit; the storage unit includes a cross-coupled inverter and an access transistor. The computing unit includes a set of computing transistors shared by each column; the computing unit has a static logic structure. The computing transistor is connected to the memory cell and the input configuration circuit; the input configuration circuit is used to configure the configuration signal input to the computing cell, so that the memory cell and the computing transistor cooperate to implement logical AND and logical OR functions.

2. The reconfigurable SRAM storage computing structure according to claim 1, characterized in that, The cross-coupled inverter includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor to form a first storage node; the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor to form a second storage node.

3. The reconfigurable SRAM storage computing structure according to claim 2, characterized in that, The access transistor includes a third NMOS transistor and a fourth NMOS transistor; the drain of the third NMOS transistor is connected to the first memory node; the drain of the fourth NMOS transistor is connected to the second memory node. The gates of the third NMOS transistor and the fourth NMOS transistor are both connected to word lines; the source of the third NMOS transistor is connected to a bit line; and the source of the fourth NMOS transistor is connected to a non-bit line.

4. The reconfigurable SRAM storage computing structure according to claim 3, characterized in that, The configuration input signal includes a first configuration input signal and a second configuration input signal; The computing transistors include a fifth NMOS transistor and a sixth NMOS transistor; The gate of the fifth NMOS transistor is connected to the bit line, and the drain of the fifth NMOS transistor is connected to the first configuration input signal; The gate of the sixth NMOS transistor is connected to the bit line NOT, and the drain of the sixth NMOS transistor is connected to the second configuration input signal; The source of the fifth NMOS transistor and the source of the sixth NMOS transistor are both connected to the signal output terminal of the computing unit.

5. The reconfigurable SRAM storage computing structure according to claim 4, characterized in that, The input configuration circuit configures the first configuration input signal as an operation data signal and the second configuration input signal as 0. When the first storage node is 0 and the second storage node is 1, the fifth NMOS transistor is turned off and the sixth NMOS transistor is turned on, and the signal output terminal of the computing unit outputs 0. When the first storage node is 1 and the second storage node is 0, the fifth NMOS transistor is turned on and the sixth NMOS transistor is turned off, and the signal output terminal of the computing unit outputs the computation data signal.

6. The reconfigurable SRAM storage computing architecture according to claim 5, characterized in that, The first configuration input signal is configured to be 1 and the second configuration input signal is configured to be the operation data signal through the input configuration circuit. When the first storage node is 0 and the second storage node is 1, the fifth NMOS transistor is turned off and the sixth NMOS transistor is turned on, and the signal output terminal of the computing unit outputs the operation data signal. When the first storage node is 1 and the second storage node is 0, the fifth NMOS transistor is turned on and the sixth NMOS transistor is turned off, and the signal output terminal of the computing unit outputs 1.

7. The reconfigurable SRAM storage computing architecture according to claim 5, characterized in that, The input configuration circuit includes a first data selector, a second data selector, a first D flip-flop, and a second D flip-flop; wherein the first data selector and the second data selector are both 2-to-1 selectors; The output of the first data selector is connected to the signal input of the first D flip-flop, and the output of the second data selector is connected to the signal input of the second D flip-flop.

8. The reconfigurable SRAM storage computing architecture according to claim 7, characterized in that, Both the first data selector and the second data selector are connected to the computational data signal, and the first data selector and the second data selector, under the control of the first control signal and the second control signal, respectively select to output the computational data signal or a fixed level; The two selected signals are input to the first D flip-flop and the second D flip-flop, respectively. When triggered by the rising edge of the clock, the first D flip-flop and the second D flip-flop output the first configuration input signal and the second configuration input signal, respectively, thereby completing the selection of AND mode and OR mode.

9. The reconfigurable SRAM storage computing architecture according to claim 3, characterized in that, When the word line is low, the access transistor is turned off, and the first storage node and the second storage node are respectively disconnected from the corresponding bit line to achieve data retention.

10. The reconfigurable SRAM storage computing architecture according to claim 4, characterized in that, Before the read operation, the bit line and the bit line NOT are precharged to a high level. During the read operation, the word line is set to a high level to turn on the access transistor. The complementary levels stored in the memory cell cause one of the bit line and the bit line NOT to form a discharge path to ground through the turned access transistor and generate a read current. The other line has no current because there is no voltage difference. The level difference between the bit line and the bit line NOT is amplified by a sensitive amplifier to output a full-swing signal and complete the read operation.

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