Prediction method for minimum working voltage of static memory
By simulating and obtaining the static noise margin of static memory under predetermined temperature and operating conditions, and performing linear fitting, the problem of accurately predicting the minimum operating voltage of static memory is solved, ensuring its normal operation and yield under different conditions.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2026-04-21
- Publication Date
- 2026-05-19
AI Technical Summary
Existing technology cannot accurately predict the minimum operating voltage of static memory, causing static memory to malfunction when the voltage drops.
Within a predetermined temperature range and operating conditions, the static noise margin of the static memory under multiple operating voltages is obtained through simulation. The ratio of the median to the standard deviation is calculated, and linear fitting is performed. The minimum operating voltage is then predicted using the fitted line.
It enables accurate prediction of the minimum operating voltage of static memory, ensuring its normal operation under different temperatures and operating conditions, and improving the yield of static memory.
Smart Images
Figure CN122067580A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically to a method for predicting the minimum operating voltage of a static memory. Background Technology
[0002] Static Random-Access Memory (SRAM) is widely used in Very Large Scale Integration (VLSI) circuits due to its performance and compatibility advantages. During the manufacturing process of SRAM, factors such as the manufacturing process can affect the minimum operating voltage (Vmin) of the SRAM.
[0003] Currently, static memory (SRAM) can usually work normally under its rated operating voltage. However, when the voltage drops to 10% or 20% below the rated operating voltage, SRAM may not work properly. Therefore, only by predicting the minimum operating voltage of SRAM can we ensure its normal operation. However, it is currently impossible to accurately predict the minimum operating voltage of SRAM. Summary of the Invention
[0004] In view of this, the embodiments of this application aim to provide a method for predicting the minimum operating voltage of static memory, so as to solve the problem that the prior art cannot accurately predict the minimum operating voltage of static memory.
[0005] This application provides a method for predicting the minimum operating voltage of a static memory, including: Within a predetermined temperature range and under predetermined operating conditions, the static noise margin of the static memory is obtained by simulation at at least two predetermined operating voltages, and at least two static noise margins are obtained under each predetermined operating voltage. Obtain the ratio of the median to the standard deviation of the static noise tolerance at each of the predetermined operating voltages; A linear fit is performed on all the stated ratios to obtain the fitted line; and, The minimum operating voltage of the static memory is predicted based on the fitted line within the predetermined temperature range and under the predetermined operating conditions.
[0006] In some embodiments, the predetermined working state includes a read state and / or a write state.
[0007] In some embodiments, after obtaining the fitted line, the prediction method further includes: Set at least two variable factors related to the minimum operating voltage; The fitted line is described using a linear function, where the independent variable of the linear function is the operating voltage of the static memory, and the slope of the linear function is the sum of the products of each variable factor and its corresponding weight factor; and, The variable factors are adjusted sequentially according to the weight factors in descending order.
[0008] In some embodiments, the variable factors include at least two of the following: threshold voltage mismatch of the static memory, threshold voltage of the linear region, saturation current, leakage current, and read current.
[0009] In some embodiments, when the minimum operating voltage is greater than a predetermined value, it is determined that the minimum operating voltage needs to be adjusted, and the variable factors are adjusted sequentially according to the weighting factors in descending order, so as to increase the slope of the linear function until the minimum operating voltage is less than or equal to the predetermined value.
[0010] In some embodiments, the variable factors are increased sequentially in descending order of weighting factors, but the variable factors that would cause a decrease in the overall performance of the static memory remain unchanged after being increased.
[0011] In some embodiments, when it is necessary to optimize the process of the static memory, the variable factors are adjusted sequentially according to the weight factors in descending order, while keeping the slope of the linear function constant.
[0012] In some embodiments, when adjusting the variable factors, the variable factors that would cause a decrease in the overall performance of the static memory when increased are decreased, and the variable factors that would cause an increase in the overall performance of the static memory when increased are increased.
[0013] In some embodiments, the magnitude of the ratio is positively correlated with the yield of the static memory.
[0014] In some embodiments, the predetermined temperature range is at least one of 115°C to 135°C, 20°C to 40°C, and -20°C to -50°C; the predetermined operating voltage is at least two of the rated operating voltage of the static memory, ±10% of the rated operating voltage of the static memory, and ±20% of the rated operating voltage of the static memory.
[0015] This application provides a method for predicting the minimum operating voltage of a static memory (SMC), comprising: simulating and obtaining the static noise margin of the SMC under at least two predetermined operating voltages within a predetermined temperature range and under predetermined operating conditions, wherein at least two static noise margins are obtained for each predetermined operating voltage; obtaining the ratio of the median to the standard deviation of the static noise margin under each predetermined operating voltage; performing linear fitting on all the ratios to obtain a fitted line; and predicting the minimum operating voltage of the SMC under the predetermined temperature range and under the predetermined operating conditions based on the fitted line. An unexpected effect of this application is that the ratios in this application can characterize the yield of the SMC, and by performing linear fitting on all the ratios, the minimum operating voltage of the SMC under the predetermined operating conditions can be accurately predicted based on the fitted line. Attached Figure Description
[0016] Figure 1 A flowchart illustrating a method for predicting the minimum operating voltage of a static memory according to an embodiment of this application.
[0017] Figure 2 This is a schematic diagram of the cell structure of a static memory provided in an embodiment of this application in the read state.
[0018] Figure 3 and Figure 4 This is a schematic diagram of the cell structure of a static memory provided in an embodiment of this application in the write state.
[0019] Figure 5 This is a schematic diagram illustrating the acquisition of read static noise tolerance according to an embodiment of this application.
[0020] Figure 6 This is a schematic diagram illustrating the acquisition of write static noise tolerance according to an embodiment of this application.
[0021] Figure 7 A table showing the relationship between ratios, static memory bits, and static memory yield provided in one embodiment of this application.
[0022] Figure 8 This application provides a data table for reading static noise tolerance and a first ratio in different temperature ranges, as provided in one embodiment of the present application.
[0023] Figure 9 According to Figure 8 A schematic diagram of the three first fitting lines obtained from the data table.
[0024] Figure 10 This application provides a data table for reading static noise tolerance and second ratio in different temperature ranges, as part of an embodiment of the present application.
[0025] Figure 11 According to Figure 10 A schematic diagram of the three second fitting lines obtained from the data table. Detailed Implementation
[0026] Experience suggests that the operating voltage of static memory (SRAM) may be related to multiple variable factors, but the relative proportions of these factors are unclear. While it's possible to adjust the SRAM's operating voltage by changing a single variable factor during simulation, this process requires extensive simulation and data processing, and it's difficult to identify the dominant variable factor. Therefore, it's challenging to accurately predict the minimum operating voltage of SRAM.
[0027] Based on this, this application provides a method for predicting the minimum operating voltage of a static memory (SMC), comprising: simulating and obtaining the static noise margin of the SMC under at least two predetermined operating voltages within a predetermined temperature range and under predetermined operating conditions, wherein at least two static noise margins are obtained for each predetermined operating voltage; obtaining the ratio of the median to the standard deviation of the static noise margin under each predetermined operating voltage; performing linear fitting on all ratios to obtain a fitted line; and predicting the minimum operating voltage of the SMC under the predetermined temperature range and under predetermined operating conditions based on the fitted line. The ratios in this application can characterize the yield of the SMC, and by performing linear fitting on all ratios, the minimum operating voltage of the SMC under the predetermined operating conditions can be accurately predicted based on the fitted line.
[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0029] One embodiment of this application provides a method for predicting the minimum operating voltage of a static memory, used to predict the minimum operating voltage of a static memory. Figure 1 A flowchart of a method for predicting the minimum operating voltage of a static memory provided in an embodiment of this application is shown below. Figure 1 As shown, the method for predicting the minimum operating voltage of static memory includes: Step S100: Under a predetermined temperature range and a predetermined operating state, simulate and obtain the static noise margin of the static memory at at least two predetermined operating voltages, and obtain at least two static noise margins at each predetermined operating voltage. Step S200: Obtain the ratio of the median to the standard deviation of the static noise tolerance at each predetermined operating voltage; Step S300: Perform linear fitting on all ratios to obtain the fitted line; and, Step S400: Predict the minimum operating voltage of the static memory within a predetermined temperature range and under a predetermined operating condition based on the fitted line.
[0030] Specifically, in step S100, the predetermined temperature range, predetermined operating state, and at least two predetermined operating voltages can be determined first.
[0031] In some embodiments, the predetermined temperature range is typically a temperature range of interest to researchers or users. For example, researchers or users are typically interested in the performance of static memory at high, normal, and low temperatures. High temperatures could be, for example, 115°C to 135°C, normal temperatures could be, for example, 20°C to 40°C, and low temperatures could be, for example, -20°C to -50°C. Therefore, the predetermined temperature range can be at least one of 115°C to 135°C, 20°C to 40°C, and -20°C to -50°C. Static memory has multiple operating states, such as read and write states; therefore, the predetermined operating states can include read and / or write states. The predetermined operating voltage can be at least two of the static memory's rated operating voltage, ±10% of the static memory's rated operating voltage, and ±20% of the static memory's rated operating voltage.
[0032] Furthermore, within a predetermined temperature range and under predetermined operating conditions, the static noise tolerance of the static memory is simulated and obtained at least two predetermined operating voltages, and at least two static noise tolerances are obtained for each predetermined operating voltage. In some embodiments, to improve data accuracy, the number of static noise tolerances obtained for each predetermined operating voltage can be increased, for example, more than 1000 static noise tolerances can be obtained for each predetermined operating voltage.
[0033] It is important to emphasize that the static noise margin obtained in this step is the static noise margin under a predetermined temperature range and a predetermined operating state. As explained above, the predetermined temperature range can be at least one of 115℃~135℃, 20℃~40℃, and -20℃~-50℃. The predetermined operating state can be a read state and / or a write state. In this case, the static noise margin can be the static noise margin of the static memory under the following conditions: 115℃~135℃ and read state; 20℃~40℃ and read state; -20℃~-50℃ and read state; 115℃~135℃ and write state; 20℃~40℃ and write state; and -20℃~-50℃ and write state. For ease of distinction, the static noise margin of static memory in the read state will be referred to as the read static noise margin (RSNM), and the static noise margin of static memory in the write state will be referred to as the write static noise margin (WSNM).
[0034] For example, assuming a predetermined temperature range of 20℃ to 40℃, predetermined operating states of read and write, and predetermined operating voltages of the static memory (SMemory), ±10% of the SMemory's rated operating voltage, and ±20% of the SMemory's rated operating voltage (a total of 5 different operating voltages), 1000 static noise margins are obtained for each predetermined operating voltage. In this case, simulating the SMemory's static noise margins at at least two predetermined operating voltages includes: within the 20℃ to 40℃ range, and when the SMemory is in read state, simulating the SMemory's read static noise margins at 5 different predetermined operating voltages, obtaining 1000 read static noise margins for each predetermined operating voltage, for a total of 5... 1000 read static noise margins were obtained. Simultaneously, within the temperature range of 20℃ to 40℃, and while the static memory was in write mode, the write static noise margins of the static memory were simulated and obtained at five different predetermined operating voltages. For each predetermined operating voltage, 1000 write static noise margins were obtained, for a total of five... 1000 write static noise tolerances.
[0035] In some embodiments, the simulation can be an Hspice circuit simulation, that is, within a predetermined temperature range and under predetermined operating conditions, at least two Monte Carlo results are obtained by Hspice simulation for the static noise margin of the static memory at each predetermined operating voltage.
[0036] In some embodiments, the predetermined operating state can be a read state or a write state. In this case, the read static noise tolerance or write static noise tolerance of the static memory under at least two predetermined operating voltages can be obtained separately in the read state or the write state.
[0037] Figure 2 This is a schematic diagram of the cell structure of a static memory provided in an embodiment of this application in the read state. Figure 2 As shown, the static memory includes a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first transmission gate transistor PG1, and a second transmission gate transistor PG2. The first and second transmission gate transistors PG1 and PG2 can be N-type transistors. The gates of the first and second transmission gate transistors PG1 and PG2 are connected to and controlled by the word line WL, which determines whether to select the cell structure. A latch formed by the first pull-up transistor PU1, the second pull-up transistor PU2, the first pull-down transistor PD1, and the second pull-down transistor PD2 is used to store bits. The bits are stored in the first storage node Q, and the complementary value of the bit is stored in the second storage node QB. The stored bits can be written to or read from the cell structure via the bit line BL and the complementary bit line BLB (bit-line bar, reverse bit line), where the bit line BL and the complementary bit line BLB can carry complementary bit line signals.
[0038] This unit structure is powered by a voltage V. DD Power supply: The sources of the first pull-up transistor PU1 and the second pull-up transistor PU2 are respectively connected to the power supply voltage V. DD The sources of the first pull-down transistor PD1 and the second pull-down transistor PD2 are grounded. The gates of the first pull-up transistor PU1 and the first pull-down transistor PD1 are connected to the drains of the second pull-up transistor PU2 and the second pull-down transistor PD2, forming a connection node as the first memory node Q. The gates of the second pull-up transistor PU2 and the second pull-down transistor PD2 are connected to the drains of the first pull-up transistor PU1 and the first pull-down transistor PD1, forming a connection node as the second memory node QB. The source / drain of the first transmission gate transistor PG1 is connected to the bit line BL, and the source / drain of the second transmission gate transistor PG2 is connected to the complementary bit line BLB.
[0039] Please continue reading. Figure 2Assuming the first storage node Q stores 0 data and the second storage node QB stores 1 data, when the static memory is in read mode, BL / BLB=1 and WL=1. At this time, the potential difference between BL and BLB can be detected using the sensing amplifier SA to determine the data stored in the first storage node Q. The read current Iread flows to the first pull-down transistor PD1 and the second pull-down transistor PD2, and then to ground.
[0040] Figure 3 and Figure 4 This is a schematic diagram of the cell structure of a static memory provided in an embodiment of this application in the write state. Figure 3 and Figure 4 As shown, for a write operation, assuming the data stored in the first storage node Q is 0 and needs to be changed to 1, then BL=1, BLB=0, WL=1. The first process is that the first pull-up transistor PU1 and the second pull-down transistor PD2 are turned off, and the second pull-up transistor PU2 and the first pull-down transistor PD1 are turned on. The second process is that the first pull-up transistor PU1 and the second pull-down transistor PD2 are turned on, and the second pull-up transistor PU2 and the first pull-down transistor PD1 are turned off.
[0041] Figure 5 This is a schematic diagram illustrating the acquisition of read static noise tolerance according to an embodiment of this application. Figure 5 As shown, the voltages of the second storage node QB and the first storage node Q are used as the x and y axes, respectively. The Beta ratio, obtained by dividing the saturation current of the pull-down transistor PD (including the first pull-down transistor PD1 or the second pull-down transistor PD2) by the saturation current of the transmission gate transistor PG (including the first transmission gate transistor PG1 or the second transmission gate transistor PG2), is plotted on the coordinate axis. Figure 5 The side length of the smallest rectangle drawn in the diagram is the static noise tolerance for reading.
[0042] Figure 6 This is a schematic diagram illustrating the acquisition of write static noise tolerance according to an embodiment of this application. Figure 6 As shown, the voltages of the complementary bit line BLB and the first memory node Q / second memory node QB are used as the x and y axes, respectively, and the voltages of the first memory node Q / second memory node QB are plotted on the coordinate axis. Figure 6 The horizontal axis value corresponding to the point where the voltage curves of the first storage node Q and the second storage node QB overlap is the write static noise margin.
[0043] It should be noted that the methods for obtaining the read static noise tolerance and write static noise tolerance provided above are only examples. In some embodiments, other methods can also be used to obtain the read static noise tolerance and write static noise tolerance of the static memory, which will not be illustrated here.
[0044] Further, step S200 is executed to obtain the ratio of the median to the standard deviation (Stdev) of the static noise margin at each predetermined operating voltage. For example, the static noise margins of the static memory at five different predetermined operating voltages under read conditions at temperatures ranging from 20°C to 40°C were obtained above, with 1000 read static noise margins obtained for each predetermined operating voltage, for a total of 5... 1000 read static noise margins were obtained; simultaneously, under conditions of 20℃~40℃ and in write mode, the write static noise margins of the static memory were obtained at five different predetermined operating voltages, with 1000 write static noise margins obtained for each predetermined operating voltage, for a total of 5... 1000 write quiescent noise margins; next, obtain the median and standard deviation of 1000 read quiescent noise margins at each predetermined operating voltage, and obtain a ratio. A total of 5 ratios can be obtained for 5 predetermined operating voltages. Then obtain the median and standard deviation of 1000 write quiescent noise margins at each predetermined operating voltage, and obtain a ratio. A total of 5 ratios can be obtained for 5 predetermined operating voltages.
[0045] Figure 7 This application provides a table showing the relationship between the ratio Sigma No., the static memory of each bit, and the yield of the static memory, as provided in one embodiment. From... Figure 7 As can be seen, regardless of the number of bits in a static memory, the value of Sigma No. is positively correlated with the yield of the static memory. Therefore, the value of Sigma No. can characterize the yield of the static memory. As long as the value of Sigma No. remains unchanged, the yield of the static memory will not change.
[0046] For ease of distinction, the ratio of the median to the standard deviation of the read static noise margin at each predetermined operating voltage is referred to as the first ratio, and the ratio of the median to the standard deviation of the write static noise margin at each predetermined operating voltage is referred to as the second ratio.
[0047] In step S300, a linear fit is performed on the comparison values to obtain a fitted line. Specifically, a linear fit is performed on all first ratios to obtain a first fitted line, and a linear fit is performed on all second ratios to obtain a second fitted line. Both the first and second fitted lines are straight lines and can be described by a linear function (a linear function in one variable).
[0048] Figure 8 This application provides a data table showing the static noise tolerance and first ratio for reading in different temperature ranges according to an embodiment of the present application. Figure 9 According to Figure 8A schematic diagram of the three first fitted lines obtained from the data table. (See attached diagram.) Figure 8 and Figure 9 As shown, the static noise tolerance of the static memory at five predetermined operating voltages is obtained at high temperature (125℃), normal temperature (25℃), and low temperature (-40℃). Then, the first ratio (Sigma No.) of the median and standard deviation of the static noise tolerance at each predetermined operating voltage is obtained. Linear fitting is then performed on the five first ratios (Sigma No.) at high temperature, at normal temperature, and at low temperature, yielding the first fitting line corresponding to the high temperature. Figure 9 The red fitted line), the first fitted line corresponding to room temperature ( Figure 9 The black fitted line in the middle) and the first fitted line corresponding to low temperature ( Figure 9 (The fitted line in green).
[0049] Figure 10 This application provides a data table of write static noise tolerance and second ratio under different temperature ranges, as provided in one embodiment of the application. Figure 11 According to Figure 10 A schematic diagram of the three second-fit lines obtained from the data table. (See attached diagram.) Figure 10 and Figure 11 As shown, the write static noise margins of the static memory at five predetermined operating voltages are obtained at high temperature (125℃), normal temperature (25℃), and low temperature (-40℃). Then, the second ratio (Sigma No.) of the median and standard deviation of the write static noise margin at each predetermined operating voltage is obtained. Linear fitting is then performed on the five second ratios (Sigma No.) at high temperature, at normal temperature, and at low temperature, yielding the corresponding second fitting lines for each high temperature. Figure 11 The red fitted line), and the second fitted line corresponding to room temperature ( Figure 11 The black fitted line in the middle) and the second fitted line corresponding to low temperature ( Figure 11 (The fitted line in green).
[0050] Step S400 is executed to predict the minimum operating voltage of the static memory within a predetermined temperature range and under predetermined operating conditions based on the fitted curve. Combined with... Figure 9 As shown, the first fitted line is extended until it intersects the X-axis. The intersection points of the first fitted line and the X-axis represent the minimum operating voltage Read Vmin of the static memory under predetermined temperature ranges (125℃, 25℃, or -40℃) and in read mode. Combined with... Figure 11As shown, the second fitting line is extended until it intersects the X-axis. The intersection points of the second fitting line and the X-axis are the minimum operating voltage Write Vmin of the static memory under a predetermined temperature range (125℃, 25℃ or -40℃) and in the write state.
[0051] Furthermore, after obtaining the fitted line, the prediction method may further include setting at least two variable factors related to the minimum operating voltage. These variable factors are parameters of the static memory that affect the minimum operating voltage. In some embodiments, the variable factors may include at least two of the static memory's threshold voltage mismatch (Mismatch), the threshold voltage (Vtl) of the linear region, the saturation current (Idsat), the leakage current (Idoff), and the read current (Iread), but are not limited thereto.
[0052] Next, a linear function is used to describe the fitted line. The independent variable of the linear function is the operating voltage Vcc of the static memory, and the slope of the linear function is the sum of the products of each variable factor and its corresponding weight factor. That is, assuming the variable factors are x1, x2, x3…xn, where n is the number of variable factors, and the weight factors corresponding to the variable factors x1, x2, x3…xn are a1, a2, a3…an respectively, then the linear function can be expressed as Sigma No. (Vcc) = {a1…an}. x1+a2 x2+a3 x3+…+an xn} Vcc+b, where the working voltage Vcc is the independent variable of the linear function Sigma No. (Vcc), {a1 x1+a2 x2+a3 x3+…+an xn} is the slope of the linear function Sigma No. (Vcc), and b is the fitting constant.
[0053] Furthermore, depending on the actual situation, the variable factors can be adjusted sequentially according to the order of their weights from largest to smallest. For example, assuming a1>a2>a3>…an (a1~an gradually decreases), when it is necessary to adjust the minimum operating voltage under a predetermined operating state, the variable factors can be adjusted sequentially in the order of x1, x2, x3…xn. It is understandable that the larger the weight of a variable factor, the greater its influence on the linear function Sigma No. (Vcc). Adjusting the variable factors sequentially in descending order of their weights allows for rapid adjustment of the linear function Sigma No. (Vcc).
[0054] Furthermore, when the minimum operating voltage exceeds the predetermined value, it indicates that the minimum operating voltage of the static memory is too high, which is detrimental to the normal operation of the static memory. In this case, it can be determined that the minimum operating voltage needs to be adjusted. Next, the variable factors can be adjusted sequentially according to the weighting factors from large to small to increase the slope of the linear function. After the slope of the linear function increases, the operating voltage corresponding to the same ratio Sigma will decrease, so the minimum operating voltage can also be reduced. By adjusting the variable factors to reduce the slope of the linear function until the minimum operating voltage is less than or equal to the predetermined value, the minimum operating voltage can be adjusted to the appropriate level.
[0055] It should be noted that the minimum operating voltage also needs to be differentiated between the predetermined temperature range and the predetermined operating state. For example, assuming that at room temperature, the minimum operating voltage Read Vmin of the static memory in read mode is greater than the predetermined value, it indicates that the minimum operating voltage Read Vmin of the static memory in read mode at room temperature is too high, which is not conducive to the normal operation of the static memory during reading. In this case, it can be determined that the minimum operating voltage Read Vmin of the static memory in read mode at room temperature needs to be adjusted. The above steps can obtain the first fitting line at room temperature ( Figure 9 The linear function (the black fitted line in the middle) is used to adjust the variable factors in descending order of the weight factors of the linear function so that the slope of the linear function increases. This reduces the minimum operating voltage Read Vmin of the static memory in the read state at room temperature until the minimum operating voltage Read Vmin of the static memory in the read state at room temperature is less than or equal to a predetermined value. This adjusts the minimum operating voltage Read Vmin of the static memory in the read state at room temperature to the correct value.
[0056] In some embodiments, to increase the slope of the linear function, when adjusting variable factors in descending order of weight, the variable factors can be increased sequentially to increase the overall slope of the linear function. However, variable factors that would degrade the overall performance of the static memory after being increased need to remain unchanged. That is, when adjusting variable factors, those variable factors that would degrade the overall performance of the static memory after being increased are skipped (not adjusted), thus avoiding a decline in the overall performance of the static memory after adjusting the variable factors. For example, suppose the variable factors include the threshold voltage mismatch and leakage current Idoff of the static memory. The larger the threshold voltage mismatch, the worse the overall performance of the static memory. Conversely, the larger the saturation current Ids, the better the overall performance of the static memory. In this case, when adjusting the variable factors, the saturation current Ids can be increased, but the threshold voltage mismatch can be kept unchanged, thus avoiding the problem of a decline in the overall performance of the static memory after the threshold voltage mismatch is increased.
[0057] In some embodiments, even if the minimum operating voltage meets the requirements, when it is necessary to optimize the static memory process, the variable factors can still be adjusted sequentially according to the weighting factors from largest to smallest. However, when adjusting the variable factors, the slope of the linear function can be kept constant, so that the static memory yield is not changed while optimizing the static memory process. That is to say, after obtaining the linear function, it can provide a direction for improving the static memory process, while ensuring that the static memory yield remains unchanged.
[0058] Furthermore, when adjusting variable factors, factors that increase will decrease the overall performance of the static memory, while factors that increase will increase the overall performance of the static memory. For example, suppose the variable factors include the threshold voltage mismatch (Mismatch) and saturation current (Ids) of the static memory. The smaller the threshold voltage mismatch (Mismatch), the better the overall performance of the static memory. Conversely, the larger the saturation current (Ids), the better the overall performance of the static memory. In this case, when adjusting the variable factors, the saturation current (Ids) can be increased and the threshold voltage mismatch (Mismatch) can be decreased, while the slope of the linear function remains unchanged. This optimizes the process while ensuring that the yield of the static memory remains constant.
[0059] In summary, one embodiment of this application provides a method for predicting the minimum operating voltage of a static memory (SMC), comprising: simulating and obtaining the static noise margin of the SMC under at least two predetermined operating voltages within a predetermined temperature range and under predetermined operating conditions, wherein at least two static noise margins are obtained for each predetermined operating voltage; obtaining the ratio of the median to the standard deviation of the static noise margin under each predetermined operating voltage; performing linear fitting on all ratios to obtain a fitted line; and predicting the minimum operating voltage of the SMC under the predetermined temperature range and under predetermined operating conditions based on the fitted line. The ratios in this application can characterize the yield of the SMC, and by performing linear fitting on all ratios, the minimum operating voltage of the SMC under the predetermined operating conditions can be accurately predicted based on the fitted line.
[0060] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.
[0061] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.
[0062] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.
[0063] Furthermore, it should be recognized that the terminology described herein is used only to describe predetermined embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.
Claims
1. A method for predicting the minimum operating voltage of a static memory, characterized in that, include: Within a predetermined temperature range and under predetermined operating conditions, the static noise margin of the static memory is obtained by simulation at at least two predetermined operating voltages, and at least two static noise margins are obtained under each predetermined operating voltage. Obtain the ratio of the median to the standard deviation of the static noise tolerance at each of the predetermined operating voltages; A linear fit is performed on all the stated ratios to obtain the fitted line; and, The minimum operating voltage of the static memory is predicted based on the fitted line within the predetermined temperature range and under the predetermined operating conditions.
2. The method for predicting the minimum operating voltage of a static memory according to claim 1, characterized in that, The predetermined working states include read state and / or write state.
3. The method for predicting the minimum operating voltage of a static memory according to claim 1, characterized in that, After obtaining the fitted line, the prediction method further includes: Set at least two variable factors related to the minimum operating voltage; The fitted line is described using a linear function, where the independent variable of the linear function is the operating voltage of the static memory, and the slope of the linear function is the sum of the products of each variable factor and its corresponding weight factor; and, The variable factors are adjusted sequentially according to the weight factors in descending order.
4. The method for predicting the minimum operating voltage of a static memory according to claim 3, characterized in that, The variable factors include at least two of the following: threshold voltage mismatch of the static memory, threshold voltage of the linear region, saturation current, leakage current, and read current.
5. The method for predicting the minimum operating voltage of a static memory according to claim 3 or 4, characterized in that, When the minimum operating voltage is greater than a predetermined value, it is determined that the minimum operating voltage needs to be adjusted. The variable factors are adjusted sequentially according to the weighting factors in descending order to increase the slope of the linear function until the minimum operating voltage is less than or equal to the predetermined value.
6. The method for predicting the minimum operating voltage of a static memory according to claim 5, characterized in that, The variable factors are increased sequentially in descending order of their weighting factors, but the variable factors that would cause a decrease in the overall performance of the static memory remain unchanged after the increase.
7. The method for predicting the minimum operating voltage of a static memory according to claim 3 or 4, characterized in that, When it is necessary to optimize the process of the static memory, the variable factors are adjusted sequentially according to the weight factors in descending order, while keeping the slope of the linear function constant.
8. The method for predicting the minimum operating voltage of a static memory according to claim 3 or 4, characterized in that, When adjusting the variable factors, the variable factors that would decrease the overall performance of the static memory when increased will be decreased, and the variable factors that would increase the overall performance of the static memory when increased will be increased.
9. The method for predicting the minimum operating voltage of a static memory according to claim 1, characterized in that, The magnitude of the ratio is positively correlated with the yield of the static memory.
10. The method for predicting the minimum operating voltage of a static memory according to claim 1, characterized in that, The predetermined temperature range is at least one of 115℃~135℃, 20℃~40℃, and -20℃~-50℃; the predetermined operating voltage is at least two of the rated operating voltage of the static memory, ±10% of the rated operating voltage of the static memory, and ±20% of the rated operating voltage of the static memory.