Read-only memory (ROM) repair

Abstract

A read-only memory (ROM) receives an instruction address from a requester and provides a fetched instruction from the instruction address. The ROM repairer includes storage circuitry to store a group of entries, each entry having a corresponding group address and being configurable as a repair address entry or a repair replacement entry. The first entry of the group is configured as a first patching address entry that stores address information indicating a first range of ROM addresses for a first patch of the instruction. A plurality of entries of the group following the first entry are configured as a plurality of patching replacement entries, each patching replacement entry storing a replacement instruction for the first patch. Control circuitry determines whether the instruction address hits in the group, and when hits, the replacement instruction from one of the plurality of repair replacement entries is returned to the requestor in place of the fetched instruction.

Description

Technical Field

[0001] This disclosure generally relates to memory, and more specifically to read-only memory (ROM) patching. Background Technology

[0002] In many applications, read-only memory (ROM) is used to store code or other information used within a data processing system. Once programmed, it is impossible to change the information within the ROM, such as updating or correcting the code. Therefore, in one solution, a fixed-size additional memory is used to store pairs of patchable ROM addresses and corresponding replacement instructions. In this solution, each replacement instruction requires a corresponding patchable ROM address; however, this leads to inefficient use of the additional memory space. Therefore, there is a need for ROM patching with improved efficiency to increase coverage without increasing memory size requirements. Summary of the Invention

[0003] The following are various embodiments of the present invention. It should be noted that any of the following aspects can be used in any combination with each other and with any of the disclosed embodiments.

[0004] In one embodiment, a data processing system includes: a read-only memory (ROM) configured to receive an instruction address from a requester of the data processing system and provide extracted instructions from the instruction address in the ROM; and a ROM patcher. The ROM patcher includes: a storage circuitry configured to store a group of entries, each entry having a corresponding group address and configurable as a patch address entry or a patch replacement entry, wherein a first entry in the group is configured as a first patch address entry, the first patch address entry storing address information indicating a first range of ROM addresses for a first patch for the instruction, and a plurality of entries in the group following the first entry are configured as a plurality of patch replacement entries, each patch replacement entry storing a replacement instruction for the first patch; and a control circuitry configured to determine whether the instruction address matches the group of entries, wherein when the instruction address matches the address information of the first patch address entry, the replacement instruction from one of the plurality of patch replacement entries is returned to the requester in place of the extracted instructions. In one aspect of the embodiment, each patch address entry in the group is configured to store address information indicating a corresponding range of ROM addresses for a corresponding patch for the replacement information. In another aspect, the address information in each patch address entry of the group includes a prefix portion of the corresponding patch and indicates a tag range for the corresponding patch, wherein the prefix portion corresponds to the most significant bit (MSB) portion of the corresponding range of the ROM address, and the tag in the tag range corresponds to the least significant bit (LSB) portion of the corresponding range of the ROM address. In yet another aspect, each patch address entry of the group is followed by a corresponding set of patch replacement entries for the corresponding patch, the patch replacement entries being configured to store replacement instructions or replacement data for each ROM address in the corresponding range of the ROM address. In yet another aspect, for each patch address entry of the group, the patch range is defined by a lower bound and an upper bound, the lower bound indicating the tag of the start ROM address of the corresponding patch, and the upper bound indicating the tag of the end ROM address of the corresponding patch. In yet another aspect, the address information in each patch address entry of the group further includes a patch offset, the patch offset indicating the difference between the tag of the corresponding group address of the first patch replacement entry in the corresponding set of replacement entries for the corresponding patch and the tag of the base address of the corresponding patch. In another aspect, the label of the base address corresponds to the label of the start ROM address of the corresponding range of the ROM address for the corresponding patch. In yet another aspect, when the instruction address is hit in the first patch address entry, one of the plurality of patch replacement entries is selected from the plurality of patch replacement entries based on the patch offset.In another aspect, each patch / replacement entry in the group is configured to store replacement information as a replacement instruction or replacement data value for a corresponding patch address entry in the group, wherein the group includes multiple patch / replacement entries that store replacement information for the same corresponding patch address entry in the group. In yet another aspect, when multiple patch / replacement entries store a replacement instruction for the same corresponding patch address entry in the group, the stored replacement instruction for the same corresponding patch address entry in the group is a consecutive instruction corresponding to a consecutive address location in the ROM. In another aspect of the above embodiments, the ROM patcher further includes a multiplexer configured to receive the extracted instruction from the ROM at a first input and the replacement instruction from one of the plurality of patch instruction entries in the group at a second input, wherein when the instruction address is hit in the first patch address entry, the multiplexer provides the replacement instruction from one of the plurality of patch instruction entries at the second input as a return instruction to the requester, and when the instruction address is not hit in the group of entries, the multiplexer provides the extracted instruction at the first input as the return instruction to the requester. In another aspect, the ROM patcher further includes a configuration entry configured to store a configuration indicator for each entry in the group to indicate whether the entry is configured as a patch address entry or a patch instruction entry.

[0005] In another embodiment, a data processing system includes: a read-only memory (ROM) configured to receive an instruction address from a requester of the data processing system and to provide extracted instructions from the instruction address of the ROM; and a ROM patcher. The ROM patcher includes: a storage circuit system configured to store: a group of entries, each entry having a corresponding group address; and a configuration entry configured to store a configuration indicator for each entry in the group to indicate whether the entry is configured as a patch address entry or a patch instruction entry, wherein each patch address entry in the group is configured to store address information indicating a range of patchable ROM addresses for a corresponding instruction patch, and each patch address entry in the group has a set of one or more corresponding patch instruction entries in the group, each corresponding patch instruction entry being configured to store a corresponding replacement instruction for the corresponding instruction patch; and a control circuit system configured to determine whether the instruction address hits in the group of entries by comparing the instruction address with each patch address entry in the group, and when a hit occurs for a patch address entry having at least two corresponding patch instruction entries, to select one of the at least two corresponding patch instruction entries to replace the extracted instruction with the corresponding replacement instruction and return it to the requester. In one aspect of another embodiment, the address information in each patch address entry of the group includes a prefix portion of the start ROM address of the range of patchable ROM addresses for the corresponding instruction patch, a patch range, and a patch offset. In yet another aspect, the patch offset of each patch address entry of the group indicates the difference between the corresponding group address of the first instruction entry of the set of one or more corresponding patch instruction entries and the tag of the start ROM address of the range of patchable ROM addresses for the corresponding instruction patch. In yet another aspect, the patch range of each patch address entry of the group indicates a tag range for the corresponding instruction patch, wherein the prefix portion corresponds to the most significant bit (MSB) portion of the start ROM address, and the tag in the tag range corresponds to the least significant bit (LSB) portion of the range of patchable ROM addresses for the corresponding instruction patch. In yet another aspect, the patching range of each patch address entry in the group is defined by a lower bound and an upper bound, the lower bound indicating the label of the start ROM address of the range of patchable ROM addresses for the corresponding patch, and the upper bound indicating the label of the end ROM address of the range of patchable ROM addresses for the corresponding patch.In another aspect, the control circuitry is configured to determine whether an instruction address hits a group of entries by comparing a prefix portion of the instruction address with a ROM prefix portion of each patch address entry in the group and comparing a tag of the instruction address with the patch range of each patch address entry in the group. In yet another aspect, the control circuitry is configured to select one of the at least two corresponding patch instruction entries using the patch offset of the hit entry when a hit occurs for a hit entry that is a patch address entry having at least two corresponding patch instruction entries. In another aspect of a further embodiment, for each patch address entry in a group having a set of multiple corresponding patch instruction entries, the corresponding replacement instructions of the multiple corresponding patch instruction entries are consecutive instructions. Attached Figure Description

[0006] The invention is illustrated by way of example and is not limited to the drawings, in which similar reference numerals indicate similar elements. Elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale.

[0007] Figure 1 A data processing system having a read-only memory (ROM) and a corresponding ROM patcher according to an embodiment of the present invention is shown in block diagram form.

[0008] Figure 2 A block diagram illustrates an embodiment of the present invention. Figure 1 A more detailed view of the ROM patcher between the ROM and the CPU.

[0009] Figure 3 The invention is illustrated in diagram form for various embodiments thereof. Figure 2 Different layouts of the register group of the ROM repairer.

[0010] Figure 4 The patch address word in the register group of a ROM patcher according to an embodiment of the present invention is illustrated in diagram form.

[0011] Figure 5 An embodiment of the present invention is shown in partial schematic and partial block diagram form. Figure 2 A more detailed view of the ROM patcher. Detailed Implementation

[0012] In one aspect, in a data processing system having a ROM and a processor, each coupled to a system interconnect, a ROM patcher resides between the ROM and the system interconnect, enabling the ROM patcher to monitor addresses provided to the ROM and selectively replace return data elements from the ROM with replacement data elements (each data element may represent a replacement instruction or replacement data). In one embodiment, assuming the ROM stores instructions fetched by the processor, the ROM patcher includes a register set configured to store one or more instruction addresses of the ROM and one or more replacement instructions for each of the stored instruction addresses. In this way, when the ROM address used for instruction fetching from the processor matches a range of patchable addresses stored in the register set, the ROM patcher, in response to instruction fetching, selects an appropriate replacement instruction corresponding to the patchable address range from the register set to return to the processor, rather than returning the instruction stored in the ROM. At startup, the register set may be initialized via a dedicated bus or via another direct connection to the register set. In one embodiment, the register set can store one or more replacement instructions for each patchable ROM address range. In this way, the register set does not need to store the ROM address corresponding to each replacement instruction, thus allowing for improved configurability of the ROM patcher and improved use of the patch register set.

[0013] Figure 1 A data processing system 100 according to an embodiment of the present invention is illustrated in block diagram form. System 100 includes a processor 10, a system interconnect 12, and a ROM system 26, wherein the ROM system 26 includes a ROM 22 and a ROM patcher 20. The processor 10 is bidirectionally coupled to the system interconnect 12, and the ROM system 26 is bidirectionally coupled to the system interconnect 12 via an address bus 14 and a data bus 16. Each of the ROM 22 and the ROM patcher 20 is coupled to the address bus 14, the ROM patcher 20 is coupled to the system interconnect 12 via the data bus 16, and the ROM 22 is coupled to the ROM patcher 20. It should be noted that the processor 10 can be any type of processor, such as a central processing unit (CPU). The system interconnect 12 can be any type of system interconnect, such as a system bus, crossbar switch, and interconnect structure. Regardless of how the system interconnect 12 is implemented, the ROM patcher 20 is configured to monitor addresses on the address bus 14 and intercept data returned from the ROM 22 in order to selectively provide replacement data to the system interconnect 12 instead of data returned from the ROM 22.

[0014] Although ROM 22 can store any type of information, such as instructions or data values ​​(where data values ​​may include, for example, operands, table values, operation values, results, etc.), for ease of description, it will be assumed that ROM 22 stores instructions (i.e., code), and therefore, ROM patcher 20 intercepts instructions returned from ROM 22 in order to selectively provide replacement instructions back to system interconnect 12. Since processor 10 can request or retrieve information (e.g., instructions) from ROM 20, processor 10 may also be referred to as a requester or requesting device. And, although... Figure 1 It has been shown as including a processor and a ROM system, but it should be noted that in alternative embodiments, system 100 may include additional elements, such as additional memory, additional processor, or other requesters capable of requesting information from ROM 20 or any other memory, other modules, or peripheral devices.

[0015] Figure 2 A block diagram illustrates the coupling between ROM 22 and processor 10 according to an embodiment of the present invention. Figure 1 A more detailed view of the ROM patcher 20. ROM 22 receives read access addresses (e.g., read instruction addresses) from processor 10 via system interconnect 12 and address bus 14, and ROM 22 provides return data (e.g., instructions) from the read access addresses as ROM_data. ROM patcher 20 includes a storage circuitry 202 comprising a configuration entry 204 and a patch entry set 206, wherein each patch entry can be configured to patch an address entry or patch an instruction entry. In one embodiment, the storage circuitry 202 is implemented as a register set (and thus may be referred to as register set 202, which includes a configuration register 204 and a patch register set 206). In this embodiment, each patch entry may be referred to as a patch register, wherein each patch register can be configured to patch an address register or patch an instruction register. It should be noted that in alternative embodiments, although in Figure 2 The register group is shown as a register group, but the storage circuitry 202 can be implemented with any type of storage circuitry, such as any type of memory or register, fuse, etc. The storage circuitry 202 may include additional circuitry as needed to write entries or registers and can receive information for storage in registers via initialization path 18. For the purposes of this description, the storage circuitry 202 will be referred to as register group 202. In one embodiment, initialization path 18 may be accessed by the processor 10, other elements of the system 100 (e.g., the security subsystem of the system 100), or via an external pin to initialize register group 202.

[0016] In addition to register set 202, ROM patcher 20 includes a master control multiplexer (MUX) 210 and control circuitry 208. MUX 210 receives patch_data at a first data input, ROM_data at a second data input, and a patch master control signal (patch_ovr) at a control input. ROM 22 receives access addresses from processor 10 via system interconnect 12 and address bus 14, such as the instruction fetch address corresponding to a fetch request (i.e., INST ADDR). ROM 22 then provides the fetched instruction from the fetch address as ROM_data to the second data input of MUX 210. (Note that the fetched instruction provided from ROM 22 to MUX 210 as ROM_data may also be referred to as a patchable instruction.) Control circuitry 208 is configured to monitor access addresses (e.g., fetch addresses) on instruction bus 14. In response to each monitored address, control circuitry 208 determines whether the monitored address matches the patch address range within register set 202. If there is no match (i.e., if the detected address is not hit in group 202), patch_ovr is negated, causing the fetched instruction, provided as the second input of ROM_data from ROM 22 to MUX 210, to return as a return instruction in response to the fetch request to processor 10. However, if the detected address matches the patch address range within register group 202 (hit within group 202), the control circuitry 208 provides the patch instruction (i.e., the replacement instruction) as patch_data from register group 202 to MUX 210 as the first input, and asserts patch_ovr, causing the patch instruction from register group 202 to return as a return instruction via overriding MUX 210 to processor 10 in response to the fetch request. That is, in this case, the patch instruction from group 202 overrides (i.e., replaces) the fetched patchable instruction from ROM 22.

[0017] It should be noted that once ROM patcher 20 is enabled, ROM system 26 operates transparently for access to ROM 22 because, from the requester's perspective, there is no difference in the timing of the returned instructions, whether provided by ROM 22 or group 202. In one embodiment, control circuitry system 208 and supercontrol MUX 210 are implemented with combinational logic to replace original data (e.g., original instructions) with patched data (e.g., replacement instructions) at runtime. In this way, ROM patcher 20 does not introduce additional delays to ROM access time (i.e., no additional clock cycles). In one embodiment, additional sequential logic, such as one or more register levels, is included along with the combinational logic to match the timing of the ROM.

[0018] Figure 3The following diagram illustrates a method for repairing register sets (e.g., according to an embodiment of the invention) Figure 2 Example layout of group 202). In the illustrated embodiment, it is assumed that the patch register group comprises 8 patch registers, each of which can be configured as a patch address register (ADDRx) or a patch instruction register (DATAy), where x is an index of the patch address register starting from 0 up to 3, and y is an index of the patch instruction register starting from 0 up to 6. Column 300 includes the register group address of each register within the register group. Since there are 8 registers, the register group addresses are numbered from 0x0 (=b000) to 0x7 (=b111), where, as used herein, a "0x" preceding the number indicates that the number is in hexadecimal form, and a "b" preceding the number indicates that the number is in binary form. Therefore, in the illustrated embodiment, a 3-bit address value is sufficient to address all 8 registers in the group.

[0019] Column 302 shows a first example of an 8-register set, where the first, third, and seventh patch registers (at 0x0, 0x2, and 0x6 respectively) are configured as patch address registers, and the second, fourth, fifth, sixth, and eighth patch registers (at 0x1, 0x3, 0x4, 0x5, and 0x7 respectively) are configured as patch instruction registers. Each patch address register (i.e., patch address entry) indicates a patch address range for ROM22, where a patch address range can refer to a range of one or more addresses. Where a patch address register indicates a range of addresses, it simply indicates a single address. Figure 3 In the example of column 302, each of ADDR0 and ADDR2 indicates a single patch address (i.e., a range of one patch address), and ADDR1 indicates a range of three patch addresses. Figure 3 Column 304 illustrates a second example, where only the first patch register corresponds to the patch address register (at 0x0), and the remaining seven patch registers correspond to patch instruction registers storing patches of seven consecutive instructions. In the example of column 304, ADDR0 indicates the range of the seven patch addresses.

[0020] Each patch address register (i.e., patch address entry) is followed by one or more corresponding patch instruction registers (i.e., patch instruction entries), wherein a patch instruction register for each patch address is within the patch address range indicated by the patch address register. As will be described in more detail below, an instruction located at a position in ROM 22 falling within the range indicated by the patch address register will be replaced by a patch instruction located in the one or more corresponding patch instruction registers. The one or more replacement instructions may be referred to as a patch of instructions, and if there is more than one instruction in a patch of instructions, the instructions must be consecutive (e.g., located at consecutive address positions in ROM 22 and thus executed consecutively) and must be stored in the same order as the original instructions in ROM 22. It should be noted that each patch address register, together with its one or more corresponding patch instruction registers, may be stored in any order within the group (as long as the instruction order within the patch of instructions is maintained). For example, ADDR1 may precede ADDR0.

[0021] In operation, column 302 is used as an example layout for group 202. When an instruction fetch for an address in ROM 22 hits in group 202 (i.e., matches the patch address range specified by ADDR0, ADDR1, or ADDR2), the corresponding replacement instruction is returned instead of the instruction stored in ROM 22. For example, if the instruction fetch address matches a single address indicated by ADDR0, the instruction stored in DATA0 is returned instead of the instruction stored in ROM 22. Similarly, if the instruction fetch address matches an address range specified by ADDR1 (i.e., falls within the range), the instruction stored in one of DATA1 to DATA3 is returned instead of the instruction stored in ROM 22. In the case of multiple consecutive instructions, which consecutive instruction to return is determined based on the received instruction fetch address. It should also be noted that random access is still retained because jumps to patch instructions in the middle of consecutive instructions are still supported without executing previous instructions within the patch. In this manner, it should be noted that group 202 implements a 1:N scheme, where if there are consecutive blocks of N replacement instructions to be specified, only one patch address register is needed to do so (e.g., by specifying the address range of the blocks of N replacement instructions). However, in one embodiment, if the patch crosses a prefix boundary, the patch is split into two, where additional patch addresses also need to be specified for the split patch. Furthermore, in one embodiment, the patch address ranges specified by the patch address register of group 202 cannot overlap. It should be noted that in one embodiment, the values ​​in group 202 can be configured at runtime (e.g., during the startup process) via initialization path 18.

[0022] In one embodiment, see reference Figure 5The configuration register 204 is configured to specify whether a register in group 202 is a patch address register or a patch instruction register. Configuration register 204 includes a number of bits, reg_num, where each register in group 202 has a corresponding configuration bit (also called a configuration indicator) in configuration register 204. Therefore, reg_num is equal to the number of registers in group 202 (e.g., for...). Figure 3 The layout example is 8). When the corresponding configuration bit of the register in group 202 is set to the first value (e.g., 1), the register is limited to the patch address register; otherwise, when the corresponding bit is set to the second value (e.g., zero), the register is limited to the patch instruction register.

[0023] In one embodiment, each instruction address received by the ROM patcher 20 via the address bus 14 is split (i.e., parsed) by the ROM patcher 20 into an address prefix and an address tag. The address tag is log2(reg_num) bits wide (corresponding to the least significant bit (LSB) of the instruction address), while the address prefix uses the remaining bits (corresponding to the remaining most significant bit (MSB) of the instruction address). Thus, in the example where reg_num = 8 in this paper, the tag bits = log2(8) = 3 bits, and the prefix bits are the instruction address bits without the tag bits (instruction address bits - tag bits). In the example in this paper, it is assumed that each instruction address is 12 bits, such that the prefix bits = 12 - 3 = 9 bits.

[0024] To determine whether the address of the received instruction matches (i.e., hits) an instruction patch (limited by address range) in group 202, ROM patcher 20 is configured to determine whether the parsed prefix of the received instruction address matches the prefix of any patch address register in group 202, and if so, indicate a prefix hit. Next, ROM patcher 20 is configured to check, in the case of a prefix hit, whether the parsed tag of the received instruction falls within the address range of any of the patches in group 202. If so, indicate a tag hit. If a prefix hit and a tag hit occur at the same index (at the same register group address for the same patch), patch_ovr is asserted, and data from group 202 is inserted onto data bus 16 (e.g., patch instructions from group 202 are inserted onto data bus 16, replacing the fetched instructions from ROM 22). It should be noted that all instructions in the patches of instructions in group 202 correspond to ROM locations with the same address prefix. For this reason, if an instruction patch crosses a prefix boundary, the patch is split into two patches, as described above, resulting in the need to use the additional register in group 202 as the patch address register. That is, an instruction patch cannot contain replacement instructions with corresponding ROM addresses having different prefixes.

[0025] Figure 4 The layout of a patch address register of group 202 according to an embodiment of the present invention is illustrated in diagram form, wherein each patch address register of group 202 identifies an address range of ROM 22 for a corresponding patch and is followed by one or more patch instruction registers, each patch instruction register containing a replacement instruction for the corresponding patch. In one embodiment, each patch address register corresponds to a different patch base address, wherein the base address of the patch corresponds to the first (i.e., start) instruction address of the patch in ROM 22. For the illustrated embodiment, it is assumed that each instruction address is 12 bits, wherein the tag bit is 3 (LSB) bits and the prefix bit is 9 (MSB) bits. Each register of group 202 configured as a patch address register includes a plurality of bit fields configured to store address information including a patch offset (the same width as the tag bit, e.g., 3 in the illustrated embodiment), a patch prefix (the same width as the prefix bit, e.g., 9 in the illustrated embodiment), a patch lower bound, and a patch upper bound (where each of the lower and upper bounds is the same width as the tag bit, e.g., 3). The patch offset indicates the difference between the register set address (i.e., entry set address) of the first corresponding instruction register and the tag bit of the corresponding patch base address (i.e., the register set address of the first corresponding patch instruction register minus the tag bit of the corresponding base address). The patch prefix indicates the prefix bit of the corresponding patch base address. The lower and upper bounds indicate the tag bits of the first (i.e., start) patch instruction register and the last (i.e., end) patch instruction register of the corresponding patch, respectively. That is, the lower and upper bounds correspond to the tag bits of the start ROM address and the end ROM address of the patch, respectively. Therefore, it should be noted that the patch prefix combined with the patch lower bound is provided to the corresponding base address. It should be noted that in alternative embodiments, more or different fields may be used in the patch address register to indicate information. For example, instead of lower and upper bounds, the patch address register may define the address range of ROM 22 used for the corresponding patch in different ways.

[0026] Figure 5A more detailed view of a ROM patcher 20 according to an embodiment of the present invention is shown in partial block diagram and partial schematic form. In the illustrated embodiment, the example includes eight registers for register set 202, wherein the first (i.e., the far left) column indicates the corresponding register set (RB) address. The third (i.e., the far right) column, labeled REG TYPE, indicates whether each register is configured as a patch address register type or a patch instruction register type. As indicated by REG TYPE, the first, third, and fifth registers (corresponding to RB addresses 0x0, 0x2, and 0x4) are configured as patch address registers, and the remaining registers are configured as patch instruction registers. In the illustrated example, ADDR0 (indicating a range of addresses) is followed by the corresponding patch instruction register DATA0, which defines a patch with one instruction; ADDR1 (also indicating a range of addresses) is followed by the corresponding patch instruction register DATA1, which defines a patch with one instruction; and ADDR3 (indicating a range of three addresses) is followed by the corresponding patch instruction registers DATA2, DATA3, and DATA4, which define patches with three consecutive instructions. According to the example of the illustrated embodiment, the second (i.e., the middle) column provides the corresponding ROM address for each register. For each patch instruction register, the corresponding ROM address indicates the instruction address of the patch instruction, and for each patch address register, the corresponding ROM address indicates the base address of the corresponding patch. For example, for patch address register ADDR2 (at RB 0x4), the base address is b1000 1011 1011. For DATA2 to DATA4, the instruction addresses for the replacement instructions are therefore b1000 1011 1011, b1000 1011 1100, and b1000 1011 1101, where they correspond to consecutive address locations, and the address of the first instruction corresponding to the patch at DATA2 is the same as the base address. The following will use... Figure 5 Example values ​​of register group 202 are used to describe Figure 5 The operation.

[0027] Figure 5 The diagram also shows configuration register 204 with example values ​​corresponding to the example configuration of register group 202 described in the previous paragraph. Configuration register 204 consists of 8 bits, where the far rightmost bit is the configuration bit for RB 0x0 and the far leftmost bit is the configuration bit for RB 0x7. A "1" indicates that the corresponding register in group 202 is configured as a patch address register, and a "0" indicates that it is a patch instruction register. Therefore, from right to left, the first, third, and fifth bits of configuration register 204 are set to 1 to indicate that the registers at 0x0, 0x2, and 0x4 are configured as patch address registers, and the remaining registers are configured as patch instruction registers. Figure 5The control circuitry system (e.g., control circuitry system 208) of the ROM repairer 20 includes a data multiplexer 502, an adder 504, an 1HOT MUX 506, comparators (COMP) MUXs 508 and 510, equality comparators 512 (including CE_0, CE_1, CE_2, and CE_3), a range comparator 514 (including CR_0, CR_1, CR_2, and CR_3), AND gates 516, 518, 520, 522, 524, 526, and 528, and OR gates 530, 536, and 538. The control circuitry system is coupled to the overclocking MUX 210 via registers 534 and 532 to ensure that data is returned from the ROM system 26 to the processor 10 at appropriate timing.

[0028] ROM patcher 20 is configured to receive an instruction address via address bus 14, the instruction address being parsed into a 9-bit prefix (labeled RECEIVED INST ADDR PREFIX[11:3]) and a 3-bit tag (labeled RECEIVED INST TAG[2:0]). RECEIVED INST ADDR PREFIX is provided to equality comparator 512, and RECEIVED INST ADDR TAG is provided to the first input of adder 504 and range comparator 514. The second input of adder 504 is coupled to receive a 3-bit offset value from 1HOTMUX 506, and the output of adder 504 provides the sum of its inputs as a selection signal to the control input of data MUX 502. The data MUX 502 has: a data input coupled to each register of register group 202 to receive 32 bits of the corresponding register, except for the first group (which must be configured as a patch address register and therefore cannot be used as a patch instruction register); and an output coupled to provide the contents of the selected register as patch_data[31:0]. The selected register corresponds to the register whose register group address is indicated by the 3-bit input from adder 504. (It should be noted that in the illustrated embodiment, each register in group 202 is assumed to have 32 bits because each instruction returned from ROM system 26 is a 32-bit instruction; however, in alternative embodiments, the registers of group 202 may be smaller or larger as needed, depending on the size of the return instruction or return data.)

[0029] Each equality comparator in comparator 512 is a 9-bit comparator that receives RECEIVEDINST ADDR PREFIX [11:3] at its first input and a 9-bit prefix field of the corresponding register of group 202, wherein the output of the comparator is asserted as logic level one if the two 9-bit values ​​match, and negated as logic level zero otherwise. It should be noted that the corresponding register, when configured as a patch address register (rather than a path instruction register), will only have a valid 9-bit prefix field; therefore, the comparator-based matching indicator is provided as needed by gated logic 542 (including AND gates 524, 526, and 528, whose operation will be described in more detail below) to provide the matching result.

[0030] Each range comparator of comparator 514 is a 3-bit range comparator that receives RECEIVEDINST ADDR TAG[2:0] at its first input and 3-bit patched upper bound field / 3-bit patched lower bound field of the corresponding register of group 202 at its second and third inputs. The output of the range comparator is asserted as logic level one if the first input is within the range defined by the second and third inputs (i.e., >= lower bound and <= upper bound), otherwise it is negated as logic level zero. Thus, it should be noted that if "lower bound >= tag <= upper bound", the tag is considered to match (i.e., hit) the range defined by the upper and lower bounds. As described above, it should be noted that the corresponding register will only have valid 3-bit upper and lower bound fields when it is configured as a patched address register; therefore, the corresponding match indicator based on the range comparator is gated as needed by gating logic 542 (as described in more detail below) to provide the match result.

[0031] The outputs of the equality comparators (CE_0 to CE_3) and the range comparators (CR_0 to CR_3) are combined with corresponding AND gates 516, 518, 520, and 522 such that the output of the corresponding AND gate is asserted as logic high only if both RECEIVED INSTR ADDR PREFIX and RECEIVED INSTR ADDR TAG match the prefix field and range defined by the upper and lower bound fields of the same corresponding register in group 202, respectively. AND gate 516 receives the output of CE_0 at its first input and the output of CR_0 at its second input, and outputs a match_0 indicator. AND gate 518 receives the output of CE_1 at its first input and the output of CR_1 at its second input, and outputs a match_1 indicator. AND gate 520 receives the output of CE_2 at its first input and the output of CR_2 at its second input, and outputs a match_2 indicator. AND gate 522 receives the output of CE_3 at its first input and the output of CR_3 at its second input, and outputs a match_3 indicator.

[0032] The matching indicator is used in conjunction with configuration register 204 via gating logic 542 to generate corresponding hit signals (HIT BUS[3:0]). In the illustrated embodiment, it should be noted that the corresponding prefix and tag fields of RB 0x0 of group 202 are provided to CE_0 and CR_0, and the corresponding prefix and tag fields of RB 0x2 are provided to CE_1 and CR_1. However, the contents of RB 0x3 and RB 0x4 are provided as input to COMP MUX 0 508, where one of these contents is selected to provide the corresponding field of the corresponding register to CE_2 and CR_2. Similarly, one of RB 0x5 and RB 0x6 provides the corresponding field of the corresponding register to CE_3 and CR_3 via COMP MUX 1 510. The selection signals for MUX 0 508 and MUX 1 510 are provided by configuration register 204.

[0033] Since neither of the two adjacent registers in group 202 can be configured as patch address registers (because each patch address register is followed by at least one patch instruction register), it can be assumed that only one of RB 0x3 and RB 0x4 can be a patch address register, and only one of RB 0x5 and RB 0x6 can be a patch address register. Therefore, for MUX 0 508, the configuration bit of configuration register 204 corresponding to RB 0x3 is used as a selection signal, such that if the configuration bit is 0, RB 0x3 is configured as a patch instruction register, and MUX 0 508 instead provides RB 0x4 as the corresponding register to CE_2 and CR_2. Otherwise, if the configuration bit is 1, RB 0x3 is configured as a patch address register, such that MUX 0 508 provides RB 0x3 as the corresponding register to CE_2 and CR_2. Similarly, for the MUX 1 510, the configuration bit corresponding to RB 0x5 in configuration register 204 is used as a selection signal, such that if the configuration bit is 0, RB 0x6 is configured as the patch instruction register, and therefore the MUX 0 508 instead provides RB 0x5 as the corresponding register to CE_3 and CR_3. Otherwise, if the configuration bit is 1, RB 0x5 is configured as the patch address register, such that the MUX 1 510 provides RB 0x5 as the corresponding register to CE_3 and CR_3.

[0034] Regarding the match indicator, gating logic 542 is used to generate the appropriate hit signal, where the outputs of AND gates 518, 520, and 522 are gated (i.e., disabled or masked) based on configuration register 204, since not all registers in group 202 are configured as patch address registers. It should be noted that RB 0x1 and RB 0x7 are not provided to the equality comparator in comparator 512, nor to any range comparator in comparator 514, because these specific registers cannot be configured as patch address registers (because RB 0x1 must be the patch instruction register corresponding to the patch address register of RB 0x0, and RB 0x7 can only be a patch instruction register, as it is the last register in group 202, meaning no additional patch instruction register can follow it). Due to these presumable aspects of group 202, each of comparators 512 and 514 only needs to include reg_num / 2 comparators instead of reg_num comparators. Furthermore, since RB 0x0 can be assumed to be the patch address register, the output of AND gate 516 (corresponding to CE_0 and CR_0) is ungated, allowing match_0 to be provided directly as HIT BUS[0]. HIT BUS[0] indicates a life event with respect to RB 0x0 if asserted as logic level one.

[0035] Regarding RB 0x2, it can be configured as a patch address register or a patch instruction register, wherein the configuration bit for RB 0x2 is provided as the first input to AND gate 524 as gate C0, and match_1 is provided as the second input to AND gate 524. In this way, if RB 0x2 is configured as a patch address register, the value of gate C0 is logic level one, thereby allowing the value of match_1 to be provided as HIT BUS[1]. HIT BUS[1], if asserted as logic level one, indicates a hit with respect to RB 0x2. Otherwise, if HIT BUS[1] is denied as logic level zero, it indicates a miss with respect to RB 0x2, or RB 0x2 is configured not to be used as a patch instruction register to determine a hit / miss.

[0036] Regarding RB 0x3 and RB 0x4, at most one can be configured as a patch address register. As described above, the configuration bit for RB 0x3 selects which register is provided to CE_2 and CR_2 via COMP MUX 0 508 as the selected corresponding register. In this case, the configuration bits for RB 0x3 and 0x4 are ORed together via OR gate 538 and provided as the first input to AND gate 526 as C1 gate, and match_2 is provided as the second input to AND gate 526. If either RB 0x3 or RB 0x4 is configured as a patch address register, C1 gate is asserted to logic level one, thereby allowing the value of match_2 to be provided as HIT BUS[2]. HIT BUS[2], when asserted to logic level one, indicates that the selected one of RB 0x3 or RB 0x4 is configured as a patch address register, and a life is triggered with respect to the selected register. Otherwise, if HITBUS[2] is denied to logic level zero, it indicates a miss with respect to one of RB 0x3 and RB 0x4, or RB 0x3 and RB 0x4 are configured not to be used to determine the patch instruction register for a hit / miss.

[0037] Regarding RB 0x5 and RB 0x6, at most one can be configured as a patch address register. As described above, the configuration bit for RB 0x5 selects which register is provided to CE_3 and CR_3 via COMP MUX 1 510 as the selected corresponding register. In this case, the configuration bits for RB 0x5 and 0x6 are ORed together via OR gate 536 and provided as the first input to AND gate 528 as C2 gate, and match_3 is provided as the second input to AND gate 528. If either RB 0x5 or RB 0x6 is configured as a patch address register, C2 gate is asserted to logic level one, thereby allowing the value of match_3 to be provided as HIT BUS[3]. HIT BUS[3], when asserted to logic level one, indicates that the selected one of RB 0x5 or RB 0x6 is configured as a patch address register, and a life is triggered with respect to the selected register. Otherwise, if HITBUS[3] is denied to logic level zero, it indicates a miss with respect to one of RB 0x5 and RB 0x6, or RB 0x5 and RB 0x6 are configured not to be used to determine the patch instruction register for a hit / miss.

[0038] The value of the HIT BUS is then used to control the overclocking MUX 210 to output the correct instruction (rom_data[31:0] fetched from ROM 22 or patch_data[31:0] from group 202) as a return instruction [31:0] to the requester via data bus 16. If any of the hit values ​​is asserted as logic level one, a hit is indicated, and a hit indicator is asserted. For example, OR gate 530 has inputs coupled to each bit of the HIT BUS such that if any is asserted, the output of OR gate 530 asserts the hit indicator at its output as logic level one. The hit indicator is provided to MUX 210 as patch_ovr via register 532. The value of HIT BUS[3:0] is used to generate (via 1HOT MUX 526) a select signal for data MUX 502 to select the correct replacement instruction from group 202. It should be noted that even in the case of a miss in group 202 (i.e., if the hit indicator is negated to logic level zero), the HIT BUS is used to generate a selection signal for the data MUX 502, resulting in an undefined output. However, in this case, this has no effect on the system because, if properly controlled by the hit indicator, the overdrive MUX 210 does not select the output of the data MUX 502.

[0039] It should be noted that HIT BUS[3:0] should have at most one asserted signal (i.e., at most one of the hit signals should be at logic level one). 1HOT MUX 506 is coupled to receive a 3-bit offset field from one of RB 0x0, RB 0x2, RB 0x3 / 0x4 and one of RB 0x5 / 0x6. HIT BUS[3:0] is provided to 1HOT MUX 506 to select one of the 3-bit offset values ​​as OFFSET[2:0] to adder 504 based on which of the HIT BUS hit signals is asserted, since the asserted hit signal corresponds to the patch address register that caused the hit. For example, if HIT BUS[3:0] = b0001, the offset field from RB 0x0 is selected; if HIT BUS[3:0] = b0010, the offset field from RB 0x2 is selected; if HIT BUS[3:0] = b0100, the offset field from one of RB 0x3 / 0x4 is selected; and if HIT BUS[3:0] = b1000, the offset field from one of RB 0x5 / 0x6 is selected.

[0040] Adder 504 adds the OFFSET[2:0] from 1HOT MUX 506 to RECEIVED INST ADDR TAG to obtain the appropriate register set address for the replacement instruction. This register set address is provided as a select signal to data MUX 502, which selects the patch instruction register from RB 0x1 to 0x7 to provide as patch_data[31:0]. The value of patch_data[31:0] is provided to the second input of the overdrive MUX 210 via register 534. At the appropriate time (e.g., the next clock cycle), the values ​​of registers 534 and 532 are provided to MUX 210 so that MUX 210 can provide the selected value as a return instruction. In the illustrated embodiment, registers 534 and 532 thus provide an additional register level, which is necessary because ROM 22 is expected to spend one cycle to output rom_data. It should be noted that in alternative embodiments, ROM 22 can spend any number of cycles to output rom_data. Therefore, ROM patcher 20 can be adapted to include any number of registers as needed to match the behavior of ROM 22 (e.g., timing).

[0041] It should be noted that, assuming a single prefix hit and tag hit exist at the same register set address, patch_data[31:0] represents the correct replacement instruction. If the prefix hit and tag hit are not at the same register set address, or if multiple prefix hits and tag hits exist at the same register set address, then patch_data may not be the correct replacement instruction. These error conditions can be determined, for example, based on the output of the comparator.

[0042] In operation, for each received INST ADDR from address bus 14, ROM patcher 20 determines whether the received INST ADDR is a hit within group 202 by determining whether the received INST ADDR falls within an address range identified by any of the patch address registers in group 202. This includes comparing the prefix and tag of the received INST ADDR with the patch address registers of group 202. For example, in one embodiment, ROM patcher 20 determines whether RECEIVED INSTADDR PREFIX hits (i.e., matches) the prefix field of any of the registers in group 202, where the register that caused the hit may be referred to as the hit register. (In Figure 5 In the illustrated embodiment, this is performed by comparator 512. If a prefix hit is determined, the ROM patcher 20 determines whether a tag hit has occurred by determining whether the RECEIVED INST ADDR TAG hits the corresponding range of the patch defined by the hit register. Figure 5 In the illustrated embodiment, this is performed by comparator 514. Therefore, if a prefix hit and a tag hit occur at the same register in group 202, patch_ovr is asserted such that a replacement instruction for the patch from the instruction corresponding to the hit register can be sent instead of the patchable instruction fetched from ROM 22.

[0043] As a use Figure 5 The example shown is for a sample value used for group 202, where the instruction fetch address is received by ROM patcher 20 as b1000 10111101 (=0x8BD). In this example, RECEIVED INST ADDR PREFIX is parsed as b100010111, and RECEIVED INST ADDR TAG is parsed as b101. Figure 5In the example, RB 0x4 is configured to store the patch address register for ADDR2 (specifying a range of 3 addresses), where the patch base address for ADDR2 is b10001011 1011 (which is the ROM address of the first instruction of the patch located in RB 0x5, configured as the patch instruction address). The patch address register storing ADDR2 (i.e., RB 0x4) has a patch offset field set to b010 (which is determined to be the register set address of the first instruction of the patch (i.e., b101) minus the tag bit of the base address (i.e., b011)). Therefore, the patch offset field = b101 - b011 = b010. RB 0x4 also has a patch prefix field set to b100010111, a patch lower bound field set to b011 (the tag of the first instruction of the corresponding patch in RB0x5), and a patch upper bound field set to b101 (the tag of the last instruction of the corresponding patch in RB 0x7).

[0044] In this example, due to the corresponding Figure 5 The configuration bit of RB 0x3 in configuration register 204 is set to 0, so COMP MUX 508 provides the prefix field bit (b100010111) from RB 0x4 (not RB 0x3) to CE_2. In this case, CE_2 outputs a logic level one, indicating a prefix hit, because the prefix bit from RB 0x4 matches RECEIVEDINST ADDR PREFIX. The upper and lower bound fields of RB 0x4 are provided to CR_2, and in this case, CR_2 outputs a logic level one, indicating a tag hit, because RECEIVED INST ADDR TAG is hit within the range defined by the upper and lower bounds (e.g., b101 is within the range b011 to b101). Since both inputs of AND gate 520 are one, match_2 is asserted as one. Since the configuration bit for RB 0x4 is one, HIT BUS[2] at the output of AND gate 526 is asserted as logic level one (while the remaining hit signal remains logic level zero). Therefore, HIT BUS[3:0] becomes b0100, which selects the patch offset field from the third input (from RB 0x4) of 1HOTMUX 506 and adds this offset value (b010) to RECEIVEDINST ADDR TAG (b101) to obtain b111 (the RB address of the selected register). This result is used to select the patch instruction register RB 0x7 to provide the replacement instruction as patch_data. Since the hit indicator at the output of OR gate 530 is also asserted as one, the MUX 210 selects patch_data instead of rom_data as the return instruction to data bus 16.

[0045] It should be noted that in alternative embodiments, the ROM patcher 20 may be implemented using different configurations of digital logic, such as more or fewer gates or elements compared to the illustrated case. For example, Figure 5 The illustrated embodiment utilizes assumptions about how certain registers or entries in group 202 must be configured (or how certain registers or entries cannot be configured) to reduce the number of comparators required to determine prefix and tag hits. For example, in an alternative embodiment, instead of using a number of comparators of reg_num / 2 in each of the equality comparator 512 and the range comparator 514, the equality comparator and the range comparator can be implemented for each register within group 202. Furthermore, instead of using the gating logic of AND gates 524, 526, and 528 to gate the match indicator, other embodiments can mask appropriate registers based on configuration registers to determine which registers are used for prefix and tag comparisons to determine hits / misses within group 202 (e.g., by restricting comparisons to only those registers in group 202 configured as patch address registers).

[0046] Furthermore, the above example is described with reference to replacement information from group 202, which is used to replace information from ROM 22 as an instruction, causing group 202 to store a patch of replacement instructions. However, in alternative embodiments, the same method and circuitry can be used to replace other types of information (e.g., data values) with corrected data values, wherein the patch instruction register of group 202 will actually store a patch of replacement data values ​​to replace or supplement the replacement instructions. Therefore, the patch address entries of group 202 can more broadly correspond to patches of replacement information, where the replacement information can be a replacement instruction or a replacement data value. In this case, the patch instruction entry or patch instruction register can actually be referred to as a patch replacement entry or patch replacement register (where the "replacement" information can describe an instruction or a data value, depending on the type of information being patched). Although the above description of group 202 is relative to a register group, any type of storage circuitry can be used. In this case, the patch address register or patch instruction register can actually be referred to as a patch address entry or patch address storage element, or as a patch instruction entry or patch instruction storage element, respectively. It should also be noted that group 202 can include any number of entries, whether fewer or greater than eight.

[0047] Therefore, it is now understood how to implement patching using efficiently configured patch memory circuitry systems, where fewer patch address memory elements can be used to define the patch. For example, a single patch address register can be used to define a patch with one or more patch instruction registers. In this way, a 1:1 relationship does not need to be present for each patch data element. That is, not every patch instruction register requires a separate patch address register. In this way, patching can be implemented with improved memory efficiency of the patch ROM without increasing latency or efficiency.

[0048] As used herein, the term "bus" refers to a plurality of signals or conductors that can be used to transmit one or more information of various types, such as data, address, control, or status. Conductors discussed herein may be shown or described with reference to a single conductor, multiple conductors, unidirectional conductors, or bidirectional conductors. However, different embodiments may vary the implementation of the conductors. For example, a single unidirectional conductor may be used instead of a bidirectional conductor, and vice versa. Furthermore, a single conductor carrying multiple signals may be used instead of multiple conductors that transmit multiple signals in a continuous or time-division multiplexed manner. Similarly, a single conductor carrying multiple signals may be divided into various different conductors carrying subsets of those signals. Therefore, many options exist for transmitting signals.

[0049] In this document, the terms "assertion" or "set" and "negation" (or "revoke assertion" or "clear") are used to refer to a signal, status bit, or similar device to its logical true or logical false state. If the logical true state is logic level one, then the logical false state is logic level zero. And if the logical true state is logic level zero, then the logical false state is logic level one.

[0050] Each signal described herein can be designed as either positive or negative logic, where negative logic may be indicated by an asterisk (*) or a "b" following its name. In the case of a negative logic signal, the signal is active low, where a true logic state corresponds to logic level zero. In the case of a positive logic signal, the signal is active high, where a true logic state corresponds to logic level one. It should be noted that any signal described herein can be designed as either a negative or positive logic signal. Therefore, in alternative embodiments, those signals described as positive logic signals may be implemented as negative logic signals, and those signals described as negative logic signals may be implemented as positive logic signals.

[0051] In this document, brackets are used to indicate the position of conductors or bits of a bus value. For example, “bus 60 [7:0]” or “conductors of bus 60 [7:0]” indicates the eight low-order conductors of bus 60, and “address bits [7:0]” or “ADDRESS [7:0]” indicates the eight low-order bits of an address value. The symbol “$” or “0x” preceding a number indicates that the number is represented in hexadecimal or digit-major form. The symbol “%” or “b” preceding a number indicates that the number is represented in binary or digit-major form.

[0052] Since the apparatus for implementing this invention consists mostly of electronic components and circuits known to those skilled in the art, circuit details will not be described to any greater extent than is deemed necessary in the above figures in order to understand and comprehend the basic concepts of this invention and to avoid obscuring or departing from its teachings.

[0053] Although the present invention has been described with respect to the polarity of a particular type of conductivity or potential, those skilled in the art will understand that the polarity of the type of conductivity or potential can be reversed.

[0054] Furthermore, the terms “front,” “back,” “top,” “bottom,” “on,” “under,” etc., as used in the specification and claims (if applicable), are for descriptive purposes and are not necessarily used to describe permanent relative positions. It should be understood that such terms are interchangeable where appropriate, so that embodiments of the invention described herein (e.g.) can operate in orientations other than those described or otherwise depicted herein.

[0055] Where appropriate, some of the above embodiments can be implemented using a variety of different information processing systems. For example, although Figure 1 The description herein presents an exemplary information processing architecture, but this exemplary architecture is presented merely to provide useful reference in discussing various aspects of the invention. Of course, for illustrative purposes, the description of the architecture has been simplified, and it is only one of many different types of suitable architectures that can be used according to the invention. Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative, and alternative embodiments may combine logic blocks or circuit elements, or impose alternative functional decompositions on various logic blocks or circuit elements. Therefore, it should be understood that the architecture depicted herein is merely exemplary, and in practice, many other architectures can be implemented to achieve the same functionality.

[0056] Moreover, for example, in one embodiment, the illustrated elements of system 100 are circuit systems located on a single integrated circuit or within the same device. Alternatively, system 100 may include any number of individual integrated circuits or individual devices interconnected with each other. For example, ROM system 26 may be located on the same integrated circuit as processor 10, or on a separate integrated circuit, or within another peripheral device or dependent device discretely separate from other elements of system 100.

[0057] Furthermore, those skilled in the art will recognize that the boundaries between the functionalities of the above operations are merely illustrative. The functionality of multiple operations can be combined into a single operation, and / or the functionality of a single operation can be distributed across other operations. Additionally, alternative embodiments may include multiple instances of a particular operation, and the order of the operations may be varied in different other embodiments.

[0058] While the invention has been described herein with reference to specific embodiments, various modifications and alterations may be made without departing from the scope of the invention as set forth in the appended claims. For example, a memory circuit system storing patch address entries and patch data (e.g., instruction) entries may include any number of entries, and is not limited to eight entries or registers. Therefore, the specification and drawings should be considered illustrative and not restrictive, and all such modifications are intended to be included within the scope of the invention. It is not intended that any benefit, advantage, or solution to a problem described herein with respect to specific embodiments be construed as a critical, necessary, or essential feature or element of any or all claims.

[0059] As used in this article, the term “coupling” is not intended to be limited to direct coupling or mechanical coupling.

[0060] Furthermore, as used herein, the term "a" is defined as one or more. Moreover, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed as implying that another claim element introduced by the indefinite article "a" limits any particular claim containing this introduced claim element to an invention containing only one of that element, even when the same claim includes the introductory phrase "one or more" or "at least one" and an indefinite article such as "a". The same applies to the use of definite articles.

[0061] Unless otherwise stated, terms such as “first” and “second” are used to arbitrarily distinguish the elements described by these terms. Therefore, these terms are not necessarily intended to indicate the temporal or other priority order of such elements.

Claims

1. A data processing system, characterized in that, The data processing system includes: A read-only memory (ROM) configured to receive an instruction address from a requester of the data processing system, and to provide a fetched instruction from the instruction address in the ROM; and ROM repair tool, which includes: A storage circuit system configured to store groups of entries, each entry having a corresponding group address and configurable as a patch address entry or a patch replacement entry, wherein a first entry of the group is configured as a first patch address entry, the first patch address entry storing address information indicating a first range of ROM addresses for a first patch for instructions, and multiple entries of the group following the first entry are configured as multiple patch replacement entries, each patch replacement entry storing a replacement instruction for the first patch, and... A control circuit system is configured to determine whether the instruction address matches in the group of entries, wherein when the instruction address matches the address information of the first patch address entry, the replacement instruction from one of the plurality of patch replacement entries is returned to the requester in place of the extracted instruction.

2. The data processing system according to claim 1, characterized in that, Each patch address entry in the group is configured to store address information indicating a corresponding range of ROM addresses for the corresponding patch used to replace the information.

3. The data processing system according to claim 2, characterized in that, The address information in each patch address entry of the group includes a prefix portion of the corresponding patch and indicates a tag range for the corresponding patch, wherein the prefix portion corresponds to the most significant bit (MSB) portion of the corresponding range of the ROM address, and the tag in the tag range corresponds to the least significant bit (LSB) portion of the corresponding range of the ROM address.

4. The data processing system according to claim 3, characterized in that, Each patch address entry in the group is followed by a corresponding set of patch replacement entries for the corresponding patch, the patch replacement entries being configured to store replacement instructions or replacement data for each ROM address in the corresponding range of ROM addresses.

5. The data processing system according to claim 2, characterized in that, Each patch / replacement entry in the group is configured to store replacement information as a replacement instruction or replacement data value for a corresponding patch address entry in the group, wherein the group includes multiple patch / replacement entries that store replacement information for the same corresponding patch address entry in the group.

6. The data processing system according to claim 1, characterized in that, The ROM repairer also includes: A multiplexer configured to receive the extracted instruction from the ROM at a first input and the replacement instruction from one of the plurality of patch instruction entries in the group at a second input, wherein: When the instruction address is matched in the first patch address entry, the multiplexer provides the replacement instruction from one of the plurality of patch instruction entries at the second input as a return instruction to the requester, and When the instruction address is not matched in the group of the entry, the multiplexer provides the extracted instruction at the first input as the return instruction to the requester.

7. A data processing system, characterized in that, The data processing system includes: A read-only memory (ROM) configured to receive an instruction address from a requester of the data processing system, and to provide a fetched instruction from the instruction address in the ROM; and ROM repair tool, which includes: A storage circuit system configured to store: groups of entries, each entry having a corresponding group address; and configuration entries configured to store configuration indicators for each entry in the group to indicate whether the entry is configured as a patch address entry or a patch instruction entry, wherein: Each patch address entry in the group is configured to store address information indicating the range of patchable ROM addresses for the corresponding instruction patch, and Each patch address entry in the group has a set of one or more corresponding patch instruction entries in the group, each corresponding patch instruction entry being configured to store a corresponding replacement instruction for the corresponding instruction patch, and A control circuit system is configured to determine whether the instruction address is a hit in the group of entries by comparing the instruction address with each patch address entry of the group, and when a hit occurs for a patch address entry that has at least two corresponding patch instruction entries, to select one of the at least two corresponding patch instruction entries to replace the extracted instruction with the corresponding replacement instruction and return it to the requester.

8. The data processing system according to claim 7, characterized in that, The address information in each patch address entry of the group includes the prefix portion of the starting ROM address of the range of patchable ROM addresses for the corresponding instruction patch, the patch range, and the patch offset.

9. The data processing system according to claim 8, characterized in that, The patch offset of each patch address entry in the group indicates the difference between the corresponding group address of the first instruction entry of the set of one or more corresponding patch instruction entries and the tag of the starting ROM address of the range of patchable ROM addresses for the corresponding instruction patch.

10. The data processing system according to claim 9, characterized in that, The patch range of each patch address entry in the group indicates a tag range for the corresponding instruction patch, wherein the prefix portion corresponds to the most significant bit (MSB) portion of the start ROM address, and the tag in the tag range corresponds to the least significant bit (LSB) portion of the range of the patchable ROM address for the corresponding instruction patch.

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