Over-temperature protection circuit of interface chip

Abstract

The invention provides an over-temperature protection circuit of an interface chip, which comprises an over-temperature protection circuit main body, the main body comprises a temperature sensitive circuit, the temperature sensitive circuit comprises a first triode, a second triode, a first resistor, a second resistor, a third resistor and a fourth resistor, and the first triode and the second triode are used for generating a base voltage difference; the first resistor and the second resistor are used for determining a base voltage difference between the first triode and the second triode; the third resistor is used for determining the current of the branch; the fourth resistor is used for providing return difference of a temperature threshold of the interface chip, and the temperature threshold is obtained according to the ratio of the sum of the third resistor and the fourth resistor to the second resistor and the area ratio of the emitter of the first triode to the emitter of the second triode. According to the invention, the solution of the temperature threshold is simplified to be only related to the resistance ratio and the emitter area ratio of the triode, so that the extremely low linear error is realized, the threshold deviation is reduced, and the linearity of the temperature threshold and the temperature is improved.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to an over-temperature protection circuit for an interface chip. Background Technology

[0002] As automotive electronic and electrical architecture evolves from distributed systems to domain controllers and central computing platforms, the channel density, power density, and functional safety requirements of individual interface chips are increasing exponentially. For CAN FD transceivers, the bus short-circuit current can reach 70 mA, and for LIN transceivers, the current can surge to over 200 mA when shorted to power or ground. Under such high power stress, the chip junction temperature can rise by more than 20°C within milliseconds, far exceeding the response speed of traditional over-temperature protection circuits. Furthermore, AEC-Q100 Grade 0 requires chips to maintain full functionality in ambient temperatures ranging from -40°C to 150°C. Traditional over-temperature protection circuits, based on MOS threshold voltage or simple BJT VBE overheat detection schemes, are prone to large threshold deviations due to factors such as process drift, packaging stress, and aging effects, easily leading to either "false protection" or "delayed protection." Summary of the Invention

[0003] The technical problem to be solved by this disclosure is to overcome the defects of existing over-temperature protection circuits, such as large threshold deviation and low linearity, and to provide an over-temperature protection circuit for an interface chip.

[0004] This disclosure solves the above-mentioned technical problems through the following technical solution:

[0005] This disclosure provides an over-temperature protection circuit for an interface chip. The over-temperature protection circuit includes an over-temperature protection circuit body, which includes a temperature-sensitive circuit. The temperature-sensitive circuit includes a first transistor, a second transistor, a first resistor, a second resistor, a third resistor, and a fourth resistor. One end of the first resistor is electrically connected to the base of the second transistor, and the other end of the first resistor is electrically connected to one end of the second resistor. The other end of the second resistor is electrically connected to both the base of the first transistor and one end of the third resistor. The other end of the third resistor is electrically connected to one end of the fourth resistor. The other end of the fourth resistor and the emitter of the first transistor are both grounded.

[0006] The first transistor and the second transistor are used to generate a base voltage difference;

[0007] The first resistor and the second resistor are used to determine the base voltage difference between the first transistor and the second transistor;

[0008] The third resistor is used to determine the current in the branch it is located in;

[0009] The fourth resistor is used to provide hysteresis for the temperature threshold of the interface chip, wherein the temperature threshold is obtained by the ratio of the sum of the third resistor and the fourth resistor to the second resistor, and the area ratio of the emitter of the first transistor to the emitter of the second transistor.

[0010] Preferably, the temperature-sensitive circuit further includes a third transistor and a tenth PMOS transistor;

[0011] The base of the third transistor is electrically connected to the collector of the first transistor, and the emitter of the third transistor is electrically connected to the other end of the first resistor; the gate of the tenth PMOS transistor is electrically connected to the drain of the tenth PMOS transistor, and the drain of the tenth PMOS transistor is electrically connected to the collector of the second transistor.

[0012] The tenth PMOS transistor is used to control the output level change of the second transistor;

[0013] The third transistor is an active load.

[0014] Preferably, the over-temperature protection circuit further includes a test circuit, one end of which is electrically connected to the base of the first transistor, and the other end of which is electrically connected to the TXD pin of the interface chip.

[0015] The test circuit is used to test the function of the over-temperature protection circuit.

[0016] Preferably, the test circuit includes a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fifth resistor;

[0017] The drain of the second NMOS transistor is electrically connected to the base of the first transistor. The source of the second NMOS transistor is electrically connected to the source of the third NMOS transistor. The drain of the third NMOS transistor is electrically connected to the drains of the fourth and seventh NMOS transistors. The source of the fourth NMOS transistor is electrically connected to the source of the fifth NMOS transistor. The drain of the fifth NMOS transistor is electrically connected to the internal circuitry of the interface chip. The gates of the second, third, fourth, and seventh NMOS transistors are all electrically connected to the gate of the sixth NMOS transistor. The drain of the sixth NMOS transistor is electrically connected to the drain of the first PMOS transistor. The source of the first PMOS transistor... The first PMOS transistor is electrically connected to the power supply. The gate of the first PMOS transistor is electrically connected to the gate of the sixth NMOS transistor, and the source of the sixth NMOS transistor is grounded. The gate of the seventh NMOS transistor is electrically connected to the drain of the sixth NMOS transistor, and the drain of the seventh NMOS transistor is electrically connected to the drain of the third NMOS transistor, and the source of the seventh NMOS transistor is grounded. The gate of the second PMOS transistor is electrically connected to the gate of the third PMOS transistor, and the drain of the second PMOS transistor is electrically connected to the power supply. The source of the second PMOS transistor is electrically connected to the source of the third PMOS transistor. The drain of the third PMOS transistor is electrically connected to one end of the fifth resistor, and the other end of the fifth resistor is electrically connected to the TXD pin of the interface chip and the secondary ESD pin in the interface chip.

[0018] Preferably, the over-temperature protection circuit further includes a bandgap reference circuit and a bias circuit, wherein the bandgap reference circuit is electrically connected to the bias circuit, and the bias circuit is electrically connected to the temperature-sensitive circuit.

[0019] The bandgap reference circuit is used to generate a reference current and transmit the reference current to the bias circuit;

[0020] The bias circuit is used to replicate the reference current into multiple currents and transmit the multiple currents to the temperature-sensitive circuit.

[0021] The temperature-sensitive circuit is used to detect temperature changes in the interface chip.

[0022] Preferably, the bandgap reference circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a fourth transistor, a fifth transistor, a sixth transistor, a sixth resistor, and a seventh resistor;

[0023] The source of the fourth PMOS transistor is electrically connected to one end of the seventh resistor and the source of the fifth PMOS transistor, respectively. The gate of the fourth PMOS transistor is electrically connected to the gate of the fifth PMOS transistor, respectively. The drain of the fourth PMOS transistor is electrically connected to the gate of the fourth PMOS transistor and the collector of the fifth PMOS transistor, respectively. The emitter of the fifth PMOS transistor is electrically connected to one end of the sixth resistor, and the other end of the sixth resistor is grounded. The base of the fifth PMOS transistor is electrically connected to the emitter of the fourth PMOS transistor and the base of the sixth PMOS transistor, respectively. The collector of the fourth PMOS transistor is electrically connected to the other end of the seventh resistor, respectively. The base of the fourth PMOS transistor is electrically connected to the drain of the fifth PMOS transistor and the collector of the sixth PMOS transistor, respectively. The emitter of the sixth PMOS transistor is grounded.

[0024] Preferably, the bias circuit includes a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor;

[0025] The gate of the sixth PMOS transistor is electrically connected to the gate of the fifth PMOS transistor. The source of the sixth PMOS transistor is electrically connected to the source of the fifth PMOS transistor, the power supply, the source of the seventh PMOS transistor, and the source of the eighth PMOS transistor. The gate of the seventh PMOS transistor is electrically connected to the gate of the sixth PMOS transistor. The drain of the sixth PMOS transistor is electrically connected to the collector of the first transistor. The drain of the seventh PMOS transistor is electrically connected to the source of the tenth PMOS transistor. The gate of the eighth PMOS transistor is electrically connected to the gate of the seventh PMOS transistor.

[0026] Preferably, the interface chip includes an eighth NMOS transistor, the gate of which is electrically connected to the collector of the second transistor, the drain of which is electrically connected to the drain of the eighth PMOS transistor, and the source of which is grounded.

[0027] Preferably, the temperature-sensitive circuit further includes a first NMOS transistor, the source of which is grounded, and the drain of which is electrically connected to the other end of the third resistor.

[0028] Preferably, the interface chip further includes a ninth NMOS transistor and a ninth PMOS transistor. The gate of the ninth NMOS transistor is electrically connected to the drain of the eighth NMOS transistor and the gate of the first NMOS transistor, respectively. The source of the ninth NMOS transistor is grounded. The drain of the ninth NMOS transistor is electrically connected to the drain of the ninth PMOS transistor. The gate of the ninth PMOS transistor is electrically connected to the gate of the ninth NMOS transistor. The source of the ninth NMOS transistor is electrically connected to the power supply.

[0029] Based on common knowledge in the field, the above-mentioned preferred conditions can be combined arbitrarily to obtain various preferred embodiments of this disclosure.

[0030] The positive and progressive effects of this disclosure are as follows:

[0031] This disclosure simplifies the solution of the temperature threshold by using an innovative architecture of dual transistors and resistor ratio in a temperature-sensitive circuit. The solution is only related to the resistor ratio and the emitter area ratio of the transistors, achieving extremely low linearity error, reducing threshold deviation, and improving the linearity between the temperature threshold and temperature. Attached Figure Description

[0032] Figure 1 A schematic diagram of the over-temperature protection circuit body is provided for Embodiment 1 of this disclosure.

[0033] Figure 2 This is a schematic diagram of the over-temperature protection circuit of the interface chip provided in Embodiment 1 of this disclosure.

[0034] Figure 3 This is a schematic diagram of the structure of an over-temperature protection circuit in the prior art. Detailed Implementation

[0035] The present disclosure is further illustrated below by way of embodiments, but the present disclosure is not limited to the scope of the embodiments described herein.

[0036] The prefixes such as "first" and "second" used in this disclosure are merely for distinguishing different descriptive objects and do not limit the position, order, priority, quantity, or content of the described objects. The use of ordinal numbers and other prefixes used to distinguish descriptive objects in this disclosure does not constitute a limitation on the described objects. The description of the described objects is given in the claims or the context of the embodiments, and should not be construed as an unnecessary limitation. Furthermore, in the description of this embodiment, unless otherwise stated, "multiple" means two or more.

[0037] In this embodiment of the disclosure, the collection, storage, use, processing, transmission, provision, and disclosure of user personal information comply with relevant laws and regulations and do not violate public order and good morals.

[0038] Example 1

[0039] Figure 1 This is a schematic diagram of the over-temperature protection circuit for an interface chip provided in Embodiment 1 of this disclosure. The over-temperature protection circuit includes an over-temperature protection circuit body, such as... Figure 1As shown, the over-temperature protection circuit body 1 includes a temperature-sensitive circuit 11. The temperature-sensitive circuit 11 includes a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. One end of the first resistor R1 is electrically connected to the base of the second transistor Q2, and the other end of the first resistor R1 is electrically connected to one end of the second resistor R2. The other end of the second resistor R2 is electrically connected to the base of the first transistor Q1 and one end of the third resistor R3, respectively. The other end of the third resistor R3 is electrically connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 and the emitter of the first transistor Q1 are both grounded.

[0040] The first and second transistors are used to generate the base voltage difference;

[0041] The first resistor and the second resistor are used to determine the base voltage difference between the first transistor and the second transistor.

[0042] The third resistor is used to determine the current in the branch it is in;

[0043] The fourth resistor is used to provide hysteresis for the temperature threshold of the interface chip. The temperature threshold is obtained by the ratio of the sum of the third and fourth resistors to the second resistor, and the area ratio of the emitter of the first transistor to the emitter of the second transistor.

[0044] In the specific implementation process, we first consider the circuit operation under normal operating conditions. When the temperature is low, the second transistor Q2 is operating in the saturation region, and the collector level of the second transistor Q2 is low, which leads to a low level output when the temperature is too high.

[0045] Next, consider the circuit's operating state just above the overtemperature threshold. At this point, the collector level of transistor Q2 is high. Therefore, both transistors Q1 and Q2 operate in the amplification region. Transistors Q1 and Q2 are matched bipolar transistors of the same type, possessing the same β value. Furthermore, due to the higher temperature, the β value of the transistors is larger. Therefore, the collector currents of transistors Q1 and Q2 can be considered equal. Thus, the difference between the base voltages of transistors Q1 and Q2 at the just-overtemperature threshold has a positive temperature coefficient V. T The expression for the difference between the base voltages of the first transistor Q1 and the second transistor Q2 at the point of just exceeding the temperature is shown in formula (1):

[0046] (1)

[0047] in, This represents the difference between the base voltages of transistor Q1 and transistor Q2 when they have just exceeded their rated temperature. This represents the base voltage of the second transistor Q2. d represents the base voltage of the first transistor Q1, c represents the number of first transistors Q1, and d represents the number of second transistors Q2. Represents a constant.

[0048] Meanwhile, in the over-temperature protection circuit, the base voltage difference between the first transistor Q1 and the second transistor Q2 is also determined by the first resistor R1 and the second resistor R2. That is, the expression for the base voltage difference between the first transistor Q1 and the second transistor Q2 is shown in formula (2):

[0049] (2)

[0050] in, This represents the base current of the first transistor Q1 and the second transistor Q2. This represents the voltage across the first resistor R1. This represents the voltage across the second resistor R2.

[0051] It should be noted that the base current I of the first transistor Q1 and the second transistor Q2 B The collector current I of the first transistor Q1 and the second transistor Q2 C The base current I of the first transistor Q1 and the second transistor Q2 is determined by their β values. B The expression is shown in formula (3):

[0052] (3)

[0053] Where β represents the amplification factor, a represents the number of fifth transistors Q5, and b represents the number of sixth transistors Q6.

[0054] Furthermore, the equation satisfied by the circuit when it just reaches the over-temperature point can be obtained, as shown in formula (4):

[0055] (4)

[0056] in, This indicates the amplification factor of the second transistor Q2. This represents the amplification factor of the first transistor Q1.

[0057] When R1 = R2, equation (4) can be simplified to equation (5):

[0058] (5)

[0059] Among them, the base voltage of the first transistor Q1 The relationship with temperature changes can be obtained through simulation. It can be approximated as a linear function of the interface chip temperature T, as shown in formula (6):

[0060] (6)

[0061] And V T Determined by the Boltzmann constant k, the charge q of the electron, and the temperature T, the expression is shown in formula (7):

[0062] (7)

[0063] Then the temperature threshold T t The expression is shown in formula (8):

[0064] (8)

[0065] Equation (8) is in the form of a ratio of a linear function to a logarithmic function. It has excellent linearity and is determined only by the resistance ratio (R3+R4) / R2 and the emitter area ratio c / d of the first transistor Q1 and the second transistor Q2. It is independent of the absolute value of the process. With proper settings, different temperature thresholds can be easily achieved, and high linearity and high consistency are also achieved.

[0066] In an alternative implementation, such as Figure 1 As shown, the temperature-sensitive circuit 11 also includes a third transistor Q3 and a tenth PMOS transistor PM10;

[0067] The base of the third transistor Q3 is electrically connected to the collector of the first transistor Q1, and the emitter of the third transistor Q3 is electrically connected to the other end of the first resistor R1; the gate of the tenth PMOS transistor PM10 is electrically connected to the drain of the tenth PMOS transistor PM10, and the drain of the tenth PMOS transistor PM10 is electrically connected to the collector of the second transistor Q2.

[0068] The tenth PMOS transistor PM10 is used to control the output level change of the second transistor Q2;

[0069] The third transistor, Q3, is an active load.

[0070] In this embodiment, the temperature-sensitive circuit 11 mainly consists of a first transistor Q1, a second transistor Q2, a third transistor Q3, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The third transistor Q3 serves as an active load and provides the base current for the first transistor Q1 and the second transistor Q2. The fourth resistor R4 provides the hysteresis of the temperature threshold.

[0071] In an alternative implementation, such as Figure 2As shown, the over-temperature protection circuit also includes a test circuit 2. One end of the test circuit 2 is electrically connected to the base of the first transistor Q1, and the other end of the test circuit 2 is electrically connected to the TXD pin of the interface chip.

[0072] The test circuit is used to test the function of the over-temperature protection circuit.

[0073] In an alternative implementation, such as Figure 2 As shown, the test circuit 2 includes a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, and a fifth resistor R5;

[0074] The drain of the second NMOS transistor NM2 is electrically connected to the base of the first transistor Q1. The source of the second NMOS transistor NM2 is electrically connected to the source of the third NMOS transistor NM3. The drain of the third NMOS transistor NM3 is electrically connected to the drains of the fourth NMOS transistor NM4 and the seventh NMOS transistor NM7. The source of the fourth NMOS transistor NM4 is electrically connected to the source of the fifth NMOS transistor NM5. The drain of the fifth NMOS transistor NM5 is electrically connected to the internal circuit 3 in the interface chip. The gates of the second NMOS transistor NM2, the third NMOS transistor NM3, the fourth NMOS transistor NM4, and the seventh NMOS transistor are all electrically connected to the gate of the sixth NMOS transistor NM6. The drain of the sixth NMOS transistor NM6 is electrically connected to the drain of the first PMOS transistor PM1. The first PMOS transistor PM1... The source is electrically connected to the power supply. The gate of the first PMOS transistor PM1 is electrically connected to the gate of the sixth NMOS transistor NM6. The source of the sixth NMOS transistor NM6 is grounded. The gate of the seventh NMOS transistor NM7 is electrically connected to the drain of the sixth NMOS transistor. The drain of the seventh NMOS transistor NM7 is electrically connected to the drain of the third NMOS transistor NM3. The source of the seventh NMOS transistor NM7 is grounded. The gate of the second PMOS transistor PM2 is electrically connected to the gate of the third PMOS transistor PM3. The drain of the second PMOS transistor PM2 is electrically connected to the power supply. The source of the second PMOS transistor PM2 is electrically connected to the source of the third PMOS transistor PM3. The drain of the third PMOS transistor PM3 is electrically connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is electrically connected to the TXD pin of the interface chip and the secondary ESD4 pin in the interface chip.

[0075] In this embodiment, the over-temperature protection circuit detects the temperature change of the interface chip and outputs an OTP_Z signal to the control logic to maintain the normal operation of the interface chip and ensure the chip's state under abnormal conditions. The over-temperature protection circuit's function is tested using a test circuit in over-temperature protection mode. A two-stage ESD protection mechanism is used on the TXD pin to prevent electrostatic contact. One end of the test circuit is electrically connected to the base of the first transistor, and the other end is electrically connected to the TXD pin of the interface chip. The TXD pin is an essential pin for CAN / LIN transceivers; in normal mode, it is a digital input used to control the dominant or recessive state of the bus. The OTP_TEST signal controls whether to enter the over-temperature protection circuit's test mode. This OTP_TEST signal can come from a specific test PAD or from a related register. In the register instruction, the sources of the second NMOS transistor NM2 and the third NMOS transistor NM3, and the sources of the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 are connected to the over-temperature protection circuit. This ensures that the body diodes of the second NMOS transistor NM2 and the third NMOS transistor NM3, and the body diodes of the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5, are in opposite directions. This structure effectively isolates the voltage levels at both ends, preventing leakage during normal operation. The seventh NMOS transistor NM7 provides a defined voltage level to the midpoint of the two pairs of body diodes when the interface chip is operating normally. At the TXD pin, the sources of the second PMOS transistor PM2 and the third PMOS transistor PM3 are connected. This ensures that the body diodes of the second PMOS transistor PM2 and the third PMOS transistor PM3 are in opposite directions. In the over-temperature protection circuit test mode, this effectively prevents leakage from the power supply VDD to TXD. The fifth resistor R5 is the pull-up resistor for TXD under normal operating conditions. The second-level ESD4 is the second-level ESD protection circuit for the TXD pin. Internal circuit 3 contains the remaining internal circuitry of the chip.

[0076] When testing the main body of the over-temperature protection circuit, for example at 25℃, setting OTP_TEST to a high level allows the base voltage of the first transistor Q1 to be transmitted to an ATE tester outside the TXD pin, achieving "threshold conversion" and thus determining the magnitude of the over-temperature threshold deviation of the interface chip. Secondly, the ATE tester sends a "high-low-high" pulse sequence (e.g., high-low-high) to the TXD pin, and the internal logic collects the toggling of the OTP_Z signal to verify the normal operation of the over-temperature protection function. Specifically, sending a "high-low-high" level to the TXD pin and determining the on / off state of the power devices in the interface chip based on the low-high-low level output of OTP_Z (e.g., when the TXD pin sends a high level, the power devices are on; when the TXD pin sends a low level, the power devices are off, indicating an over-temperature condition), thus confirming the normal operation of the over-temperature protection function.

[0077] In an alternative implementation, such as Figure 1 As shown, the main body 1 of the over-temperature protection circuit also includes a bandgap reference circuit 12 and a bias circuit 13. The bandgap reference circuit 12 is electrically connected to the bias circuit 13, and the bias circuit 13 is electrically connected to the temperature-sensitive circuit 11.

[0078] The bandgap reference circuit 12 is used to generate a reference current and transmit the reference current to the bias circuit 13;

[0079] The bias circuit 13 is used to copy the reference current into multiple currents and transmit the multiple currents to the temperature-sensitive circuit 11.

[0080] Temperature-sensitive circuit 11 is used to detect temperature changes in the interface chip.

[0081] In an alternative implementation, such as Figure 1 As shown, the bandgap reference circuit 12 includes a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a sixth resistor R6, and a seventh resistor R7.

[0082] The source of the fourth PMOS transistor PM4 is electrically connected to one end of the seventh resistor R7 and the source of the fifth PMOS transistor PM5. The gate of the fourth PMOS transistor PM4 is electrically connected to the gate of the fifth PMOS transistor PM5. The drain of the fourth PMOS transistor PM4 is electrically connected to the gate of the fourth PMOS transistor PM4 and the collector of the fifth transistor Q5. The emitter of the fifth transistor Q5 is electrically connected to one end of the sixth resistor R6, and the other end of the sixth resistor R6 is grounded. The base of the fifth transistor Q5 is electrically connected to the emitter of the fourth transistor Q4 and the base of the sixth transistor Q6. The collector of the fourth transistor Q4 is electrically connected to the other end of the seventh resistor R7. The base of the fourth transistor Q4 is electrically connected to the drain of the fifth PMOS transistor PM5 and the collector of the sixth transistor Q6, and the emitter of the sixth transistor Q6 is grounded.

[0083] In this embodiment, the bandgap reference circuit is used as a standard module to provide the reference current I. b .

[0084] In an alternative implementation, such as Figure 1 As shown, the bias circuit 13 includes a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, and an eighth PMOS transistor PM8;

[0085] The gate of the sixth PMOS transistor PM6 is electrically connected to the gate of the fifth PMOS transistor PM5. The source of the sixth PMOS transistor PM6 is electrically connected to the source of the fifth PMOS transistor PM5, the power supply VDD, the source of the seventh PMOS transistor PM7, and the source of the eighth PMOS transistor PM8. The gate of the seventh PMOS transistor PM7 is electrically connected to the gate of the sixth PMOS transistor PM6. The drain of the sixth PMOS transistor PM6 is electrically connected to the collector of the first transistor Q1. The drain of the seventh PMOS transistor PM7 is electrically connected to the source of the tenth PMOS transistor PM10. The gate of the eighth PMOS transistor PM8 is electrically connected to the gate of the seventh PMOS transistor PM7.

[0086] In this embodiment, the reference current transmitted by the bandgap reference circuit is replicated into multiple currents by the bias circuit, and the multiple currents are transmitted to different branches of the temperature-sensitive circuit.

[0087] In an alternative implementation, such as Figure 1 As shown, the interface chip includes an eighth NMOS transistor NM8. The gate of the eighth NMOS transistor NM8 is electrically connected to the collector of the second transistor Q2. The drain of the eighth NMOS transistor NM8 is electrically connected to the drain of the eighth PMOS transistor NM8. The source of the eighth NMOS transistor NM8 is grounded.

[0088] In an alternative implementation, such as Figure 1 As shown, the temperature-sensitive circuit 11 also includes a first NMOS transistor NM1, the source of which is grounded, and the drain of which is electrically connected to the other end of the third resistor R3.

[0089] In an alternative implementation, such as Figure 1 As shown, the interface chip also includes a ninth NMOS transistor NM9 and a ninth PMOS transistor PM9. The gate of the ninth NMOS transistor NM9 is electrically connected to the drain of the eighth NMOS transistor NM8 and the gate of the first NMOS transistor NM1, respectively. The source of the ninth NMOS transistor NM9 is grounded. The drain of the ninth NMOS transistor NM9 is electrically connected to the drain of the ninth PMOS transistor PM9. The gate of the ninth PMOS transistor PM9 is electrically connected to the gate of the ninth NMOS transistor NM9. The source of the ninth NMOS transistor NM9 is electrically connected to the power supply.

[0090] The over-temperature protection circuit for the interface chip provided in this embodiment is applicable to interface chips such as CAN, LIN, and SBC. By optimizing the existing conventional bipolar transistor VBE structure over-temperature protection circuit and combining it with an over-temperature protection test circuit, an over-temperature protection circuit suitable for interface chips such as CAN, LIN transceivers, and SBC is formed. Figure 3The over-temperature protection circuit used in this embodiment is based on the conventional over-temperature protection circuit structure in the prior art. It retains the advantages of low area cost and simple structure of the conventional over-temperature protection circuit, while improving the linearity of the over-temperature protection threshold with temperature, greatly reducing the threshold deviation caused by process drift. The over-temperature protection circuit in this embodiment improves the structure of the temperature-sensitive circuit in the prior art over-temperature protection circuit based on the structure of the bandgap reference circuit and bias circuit. The core of the prior art over-temperature protection circuit lies in utilizing the negative temperature coefficient of VBE of the bipolar junction transistor (BJT) to detect temperature changes and then output an over-temperature signal to the logic control circuit, ultimately achieving high-temperature protection. Figure 3 As shown, the bandgap reference circuit 101 in the prior art over-temperature protection circuit is composed of the eleventh PMOS transistor PM11, the twelfth PMOS transistor PM12, the seventh transistor Q7, the eighth transistor Q8, the ninth transistor Q9, the eighth resistor R8, and the ninth resistor R9, wherein the number of the eighth transistor Q8 and the ninth transistor Q9 are a and b, respectively.

[0091] Therefore, the reference current I generated by this bandgap reference circuit b The size is as shown in formula (9): (9), among which, This represents the voltage difference between the base and emitter of transistor Q9. This represents the voltage difference between the base and emitter of transistor Q8, and the reference current I. b This is the positive temperature coefficient (PTAT) current.

[0092] like Figure 3 As shown, the bias circuit 102 in the prior art over-temperature protection circuit is composed of the thirteenth PMOS transistor PM13, the fourteenth PMOS transistor PM14, and the fifteenth PMOS transistor PM15. The temperature sensing circuit 103 in the prior art over-temperature protection circuit is composed of the thirteenth transistor Q10, the tenth resistor R10, the eleventh resistor R11, and the tenth NMOS transistor NM10. The prior art over-temperature protection circuit also includes the eleventh NMOS transistor NM11, the twelfth NMOS transistor NM12, the thirteenth NMOS transistor NM13, the sixteenth PMOS transistor PM16, and the seventeenth PMOS transistor PM17.

[0093] The thirteenth PMOS transistor PM13, the fourteenth PMOS transistor PM14, and the fifteenth PMOS transistor PM15 respectively replicate the reference current I generated from the bandgap reference circuit. bThe branch containing the thirteenth PMOS transistor PM13 is a critical branch for the VBE of the temperature-sensitive BJT. Its current is determined by VBE and the tenth and eleventh resistors R10 and R11, respectively. The thirteenth PMOS transistor PM13 provides the base current for the thirteenth transistor Q10. The fourteenth and fifteenth PMOS transistors PM14 and PM15 provide active loads for the two branches, respectively. When the temperature reaches the threshold point, the eleventh NMOS transistor NM11 will flip.

[0094] Furthermore, the VBE of the thirteenth transistor Q10 exhibits an inverse relationship with temperature. When the junction temperature of the interface chip is below the temperature threshold, it is in normal operation, and the over-temperature output is low. When the junction temperature of the interface chip is above the temperature threshold, it is in over-temperature protection mode, and the over-temperature output is high. To avoid frequent switching of the over-temperature output due to temperature oscillation near the temperature threshold, the eleventh resistor R11 is connected in parallel with a switch controlled by the output, serving as the hysteresis of the threshold. To restore normal operation, the junction temperature needs to be further reduced. The threshold of the over-temperature protection circuit structure in this prior art, under the control of the temperature coefficient of VBE, is also affected by I... b The influence of the current, specifically the PTAT current, leads to poor linearity of the threshold in traditional over-temperature protection circuits. Furthermore, the PTAT current's temperature coefficient deviates from the design value due to lithography errors, resulting in significant threshold dispersion. This implementation, however, achieves breakthroughs in three core indicators—high linearity, high consistency, and testability—through an innovative "bipolar junction transistor (BJT) + resistor ratio" architecture. This simplifies the temperature threshold equation to an expression only related to the resistor ratio and the transistor's emitter area ratio, achieving extremely low linearity error—a significant improvement over traditional solutions. This effectively reduces threshold shifts caused by process drift. The TXD pin multiplexing enables a test mode circuit that can be triggered at 25°C via digital commands or a PAD, converting the over-temperature threshold into a measurable quantity, achieving comprehensive over-temperature functional testing coverage, and significantly shortening the test cycle and reducing testing costs.

[0095] This implementation, through an innovative architecture using a dual transistor-to-resistor ratio in the temperature-sensitive circuit, simplifies the calculation of the temperature threshold to depend only on the resistance ratio and the emitter area ratio of the transistors. This achieves extremely low linearity error, reduces threshold deviation, and improves the linearity between the temperature threshold and temperature. Furthermore, the over-temperature protection test mode reuses the TXD pin of the interface chip, enabling preliminary assessment of the over-temperature protection circuit at room temperature, predicting the over-temperature threshold, and verifying the entire over-temperature protection function at room temperature, thus improving the testability of the interface chip. This implementation provides a reusable, scalable, and standardizable solution. The over-temperature protection circuit architecture in this implementation can be seamlessly extended to various high-speed interface chips and even migrated to over-temperature protection for wide-bandgap power devices such as GaN and SiC, demonstrating significant market potential and substantial socio-economic benefits.

[0096] While specific embodiments of this disclosure have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of this disclosure is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of this disclosure, but all such changes and modifications fall within the scope of protection of this disclosure.

Claims

1. An over-temperature protection circuit for an interface chip, characterized in that, The over-temperature protection circuit includes an over-temperature protection circuit body, which includes a temperature-sensitive circuit. The temperature-sensitive circuit includes a first transistor, a second transistor, a first resistor, a second resistor, a third resistor, and a fourth resistor. One end of the first resistor is electrically connected to the base of the second transistor, and the other end of the first resistor is electrically connected to one end of the second resistor. The other end of the second resistor is electrically connected to the base of the first transistor and one end of the third resistor, respectively. The other end of the third resistor is electrically connected to one end of the fourth resistor, and the other end of the fourth resistor and the emitter of the first transistor are both grounded. The first transistor and the second transistor are used to generate a base voltage difference; The first resistor and the second resistor are used to determine the base voltage difference between the first transistor and the second transistor; The third resistor is used to determine the current in the branch it is located in; The fourth resistor is used to provide hysteresis for the temperature threshold of the interface chip, wherein the temperature threshold is obtained by the ratio of the sum of the third resistor and the fourth resistor to the second resistor, and the area ratio of the emitter of the first transistor to the emitter of the second transistor.

2. The over-temperature protection circuit for the interface chip as described in claim 1, characterized in that, The temperature-sensitive circuit also includes a third transistor and a tenth PMOS transistor; The base of the third transistor is electrically connected to the collector of the first transistor, and the emitter of the third transistor is electrically connected to the other end of the first resistor; the gate of the tenth PMOS transistor is electrically connected to the drain of the tenth PMOS transistor, and the drain of the tenth PMOS transistor is electrically connected to the collector of the second transistor. The tenth PMOS transistor is used to control the output level change of the second transistor; The third transistor is an active load.

3. The over-temperature protection circuit for the interface chip as described in claim 1, characterized in that, The over-temperature protection circuit also includes a test circuit, one end of which is electrically connected to the base of the first transistor, and the other end of which is electrically connected to the TXD pin of the interface chip. The test circuit is used to test the function of the over-temperature protection circuit.

4. The over-temperature protection circuit for the interface chip as described in claim 3, characterized in that, The test circuit includes a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fifth resistor; The drain of the second NMOS transistor is electrically connected to the base of the first transistor. The source of the second NMOS transistor is electrically connected to the source of the third NMOS transistor. The drain of the third NMOS transistor is electrically connected to the drains of the fourth and seventh NMOS transistors. The source of the fourth NMOS transistor is electrically connected to the source of the fifth NMOS transistor. The drain of the fifth NMOS transistor is electrically connected to the internal circuitry of the interface chip. The gates of the second, third, fourth, and seventh NMOS transistors are all electrically connected to the gate of the sixth NMOS transistor. The drain of the sixth NMOS transistor is electrically connected to the drain of the first PMOS transistor. The source of the first PMOS transistor... The first PMOS transistor is electrically connected to the power supply. The gate of the first PMOS transistor is electrically connected to the gate of the sixth NMOS transistor, and the source of the sixth NMOS transistor is grounded. The gate of the seventh NMOS transistor is electrically connected to the drain of the sixth NMOS transistor, and the drain of the seventh NMOS transistor is electrically connected to the drain of the third NMOS transistor, and the source of the seventh NMOS transistor is grounded. The gate of the second PMOS transistor is electrically connected to the gate of the third PMOS transistor, and the drain of the second PMOS transistor is electrically connected to the power supply. The source of the second PMOS transistor is electrically connected to the source of the third PMOS transistor. The drain of the third PMOS transistor is electrically connected to one end of the fifth resistor, and the other end of the fifth resistor is electrically connected to the TXD pin of the interface chip and the secondary ESD pin in the interface chip.

5. The over-temperature protection circuit for the interface chip as described in claim 2, characterized in that, The over-temperature protection circuit also includes a bandgap reference circuit and a bias circuit. The bandgap reference circuit is electrically connected to the bias circuit, and the bias circuit is electrically connected to the temperature-sensitive circuit. The bandgap reference circuit is used to generate a reference current and transmit the reference current to the bias circuit; The bias circuit is used to replicate the reference current into multiple currents and transmit the multiple currents to the temperature-sensitive circuit. The temperature-sensitive circuit is used to detect temperature changes in the interface chip.

6. The over-temperature protection circuit for the interface chip as described in claim 5, characterized in that, The bandgap reference circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a fourth transistor, a fifth transistor, a sixth transistor, a sixth resistor, and a seventh resistor; The source of the fourth PMOS transistor is electrically connected to one end of the seventh resistor and the source of the fifth PMOS transistor, respectively. The gate of the fourth PMOS transistor is electrically connected to the gate of the fifth PMOS transistor, respectively. The drain of the fourth PMOS transistor is electrically connected to the gate of the fourth PMOS transistor and the collector of the fifth PMOS transistor, respectively. The emitter of the fifth PMOS transistor is electrically connected to one end of the sixth resistor, and the other end of the sixth resistor is grounded. The base of the fifth PMOS transistor is electrically connected to the emitter of the fourth PMOS transistor and the base of the sixth PMOS transistor, respectively. The collector of the fourth PMOS transistor is electrically connected to the other end of the seventh resistor, respectively. The base of the fourth PMOS transistor is electrically connected to the drain of the fifth PMOS transistor and the collector of the sixth PMOS transistor, respectively. The emitter of the sixth PMOS transistor is grounded.

7. The over-temperature protection circuit for the interface chip as described in claim 6, characterized in that, The bias circuit includes a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor; The gate of the sixth PMOS transistor is electrically connected to the gate of the fifth PMOS transistor. The source of the sixth PMOS transistor is electrically connected to the source of the fifth PMOS transistor, the power supply, the source of the seventh PMOS transistor, and the source of the eighth PMOS transistor. The gate of the seventh PMOS transistor is electrically connected to the gate of the sixth PMOS transistor. The drain of the sixth PMOS transistor is electrically connected to the collector of the first transistor. The drain of the seventh PMOS transistor is electrically connected to the source of the tenth PMOS transistor. The gate of the eighth PMOS transistor is electrically connected to the gate of the seventh PMOS transistor.

8. The over-temperature protection circuit for the interface chip as described in claim 7, characterized in that, The interface chip includes an eighth NMOS transistor, the gate of which is electrically connected to the collector of the second transistor, the drain of which is electrically connected to the drain of the eighth PMOS transistor, and the source of which is grounded.

9. The over-temperature protection circuit for the interface chip as described in claim 8, characterized in that, The temperature-sensitive circuit further includes a first NMOS transistor, the source of which is grounded, and the drain of which is electrically connected to the other end of the third resistor.

10. The over-temperature protection circuit for the interface chip as described in claim 9, characterized in that, The interface chip further includes a ninth NMOS transistor and a ninth PMOS transistor. The gate of the ninth NMOS transistor is electrically connected to the drain of the eighth NMOS transistor and the gate of the first NMOS transistor, respectively. The source of the ninth NMOS transistor is grounded. The drain of the ninth NMOS transistor is electrically connected to the drain of the ninth PMOS transistor. The gate of the ninth PMOS transistor is electrically connected to the gate of the ninth NMOS transistor. The source of the ninth NMOS transistor is electrically connected to the power supply.

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