Low-jitter pulse signal generation circuit

Abstract

The invention provides a low-jitter pulse signal generation circuit, which relates to the technical field of synchronous control signals and comprises an FPGA (Field Programmable Gate Array) chip U1 and a low-jitter clock phase-locked loop chip U2, the low-jitter clock phase-locked loop chip U2 is connected with the FPGA chip U1, and the low-jitter clock phase-locked loop chip U2 is connected with the crystal oscillator U5 or the external reference clock input interface U6; the low-jitter clock phase-locked loop chip U2 is connected to the FPGA chip U1; the clock fan-out chip U3 is connected to the low-jitter clock phase-locked loop chip U2; the high-speed driving chip U4 is connected to the clock fan-out chip U3, the high-speed driving chip U4 is connected to the FPGA chip U1, and the high-speed driving chip U4 is connected to the digital pulse signal output interface U7. The circuit has the advantages of extremely low output signal jitter, excellent time sequence margin and reliability, high flexibility and expandability, capability of supporting internal and external clock reference and wide application scene.

Description

Technical Field

[0001] This invention relates to the field of synchronization control signal technology, and more specifically, to a low-jitter pulse signal generation circuit. Background Technology

[0002] In many cutting-edge technology and industrial fields, such as phased array radar systems, particle collider experimental devices, high-precision time interval measurement, and high-speed data acquisition and synchronization, it is necessary to generate digital pulse signals with strict time synchronization relationships to coordinate and trigger multiple subsystems or devices. These applications place extremely stringent requirements on the key indicator of pulse signals—jitter—typically requiring picoseconds (ps). Currently, mainstream digital pulse signal generation technologies are mainly based on application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). While ASIC-based solutions offer superior performance, they suffer from inherent drawbacks such as long development cycles, high costs, and poor flexibility. In contrast, FPGA-based solutions are widely used due to their reconfigurability, ease of development, and cost advantages. A common FPGA-based implementation involves programming the FPGA to utilize its general-purpose input / output (GPIO) pins, along with external buffers or driver chips, to generate and amplify digital pulse signals. The advantage of this method is its ability to flexibly generate dozens or even hundreds of pulse signals at a relatively low cost, and the pulse period and width can be programmed in software. However, due to factors such as switching noise, power supply noise, uncertainty in clock network delays, and variations in the output delay of the GPIO pins themselves, pulse signals directly generated by FPGA GPIOs typically exhibit random time jitter on the order of nanoseconds (ns). This level of jitter cannot meet the stringent time accuracy requirements of the aforementioned high-end application scenarios.

[0003] Therefore, a contradiction exists in existing technologies: FPGA GPIO-based solutions are low-cost and have many channels but high jitter; solutions based on FPGA high-speed transceivers or dedicated ASICs have low jitter but are expensive and lack flexibility or scalability. How to generate digital pulse signals with extremely low jitter and scalable channel count with low complexity and cost without relying on expensive dedicated hardware has become a pressing technical problem to be solved in this field. Summary of the Invention

[0004] The present invention aims to solve the problems of high complexity and cost of existing low-jitter pulse signal generation circuits.

[0005] To address the aforementioned issues, this invention provides a low-jitter pulse signal generation circuit, comprising an FPGA chip U1, a low-jitter clock phase-locked loop chip U2, a clock fan-out chip U3, and a high-speed driver chip U4; the control port of the low-jitter clock phase-locked loop chip U2 is connected to the general-purpose input / output pins of the FPGA chip U1, and the reference clock input terminal of the low-jitter clock phase-locked loop chip U2 is connected to a crystal oscillator U5 or to an external reference clock input interface U6; The first clock output terminal of the low-jitter clock phase-locked loop chip U2 is connected to the dedicated clock input pin of the FPGA chip U1; the input terminal of the clock fan-out chip U3 is connected to the second clock output terminal of the low-jitter clock phase-locked loop chip U2. The data input terminal of the high-speed driver chip U4 is connected to the output terminal of the clock fan-out chip U3, the output enable pin of the high-speed driver chip U4 is connected to the general-purpose input / output pin of the FPGA chip U1, and the data output terminal of the high-speed driver chip U4 is connected to the digital pulse signal output interface U7.

[0006] The low-jitter pulse signal generation circuit provided by this invention has, but is not limited to, the following beneficial effects compared to the prior art: The FPGA chip U1 described in this invention is programmed to configure the output clock frequency of the low-jitter clock phase-locked loop chip U2, and to generate and output a control signal to the output enable pin of the high-speed driver chip U4. This invention utilizes the low-jitter output capability of the low-jitter clock phase-locked loop chip U2 and the clock fan-out chip U3 to generate a low-jitter periodic signal. By employing the FPGA chip U1 and the high-speed driver chip U4 with an output enable pin, pulse output control of the low-jitter periodic signal is achieved, thus realizing the effect of generating a low-jitter pulse signal.

[0007] This invention features extremely low output signal jitter: it utilizes a specialized low-jitter clock phase-locked loop chip and a clock fan-out chip to generate a periodic clock signal that inherently possesses extremely low jitter, typically ranging from hundreds of femtoseconds (fs) to picoseconds (ps). The final output pulse signal is essentially a time slice of this high-quality clock signal. By ensuring that the jitter of the control slice enable signal PULSE_EN does not affect the precise timing of the slice action, the jitter of the output pulse is locked at the jitter level of the CLK_OUT signal, achieving ultra-low jitter output at the picosecond level.

[0008] This invention eliminates the reliance on high-end FPGAs: it can be implemented using only conventional FPGAs or even low-cost FPGAs with general-purpose I / O and dedicated clock input pins. The FPGA primarily handles configuration management and low-frequency enable signal generation, with minimal requirements for its internal operating frequency and performance, significantly reducing system hardware costs.

[0009] This invention offers excellent timing margin and reliability: by setting the pulse period T to be much larger than the pulse width Tw, the edge transition of the FPGA-generated enable control signal PULSE_EN can have a very relaxed setup / hold time window. Even if there is some delay uncertainty in the FPGA's internal logic, i.e., its own I / O output has jitter, it can be completely ensured that this jitter will not cause metastability or erroneous switching actions at the enable terminal of the driver chip. Thus, the system design completely blocks the transmission path of FPGA jitter to the final output signal, ensuring stable and reliable system operation.

[0010] This invention offers high flexibility and scalability: the pulse width Tw can be continuously or incrementally adjusted by configuring the phase-locked loop (PLL) output frequency; the pulse period T can be flexibly set by modifying the modulus of the internal counter in the FPGA. Furthermore, a single low-jitter clock PLL chip can output multiple clock signals, a single clock fan-out chip can provide multiple fan-out signals, and a single driver chip may integrate multiple drivers. Therefore, the architecture of this invention can be easily expanded into a multi-channel low-jitter pulse generator with excellent synchronization characteristics between channels and low expansion costs.

[0011] This invention supports both internal and external clock references, making it suitable for a wide range of applications: the circuit design supports both internal crystal oscillator and external reference clock modes. The internal crystal oscillator mode ensures independent operation of the device; the external reference clock mode allows the device to lock onto a higher-level system master clock, achieving ultra-precise synchronization between multiple devices, which is particularly suitable for large-scale distributed systems.

[0012] Furthermore, the pulse width of the pulse signal generated by the FPGA chip U1 is set by the register of the low-jitter clock phase-locked loop chip U2, and the period of its output clock signal is twice the pulse width.

[0013] Furthermore, the FPGA chip U1 contains an enable signal generation logic module.

[0014] Furthermore, the FPGA chip U1 includes a counter module.

[0015] Furthermore, the low-jitter clock phase-locked loop chip U2 is a phase-locked loop chip with an integrated voltage-controlled oscillator.

[0016] Furthermore, the clock fan-out chip U3 is a clock buffer or fan-out buffer with ultra-low added jitter.

[0017] Furthermore, the high-speed driver chip U4 is a low-voltage differential signal driver, a current-mode logic driver, or a high-speed logic gate array with tri-state outputs.

[0018] Furthermore, the FPGA U1 is model XC7Z100-2FFG900I; the low-jitter clock phase-locked loop chip U2 is model HMC7044LP10BE; the clock fan-out chip U3 is model 5PB1110PGG; and the high-speed drive chip U4 is model CDCLVC1102PWR.

[0019] Furthermore, the crystal oscillator U5 is model NT0503EH3I507EN10; the external clock input interface U6 is of type SMA.

[0020] Furthermore, the digital pulse signal output interface U7 is of type SMA. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a low-jitter pulse signal generation circuit according to an embodiment of the present invention; Figure 2 This is a circuit diagram of a low-jitter pulse signal generation circuit according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the pulse generation timing relationship in an embodiment of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings showing multiple embodiments according to this application. It should be understood that the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments described in this application without creative effort will fall within the scope of protection of this application.

[0023] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used in the description of this application is for the purpose of describing specific embodiments only and is not intended to limit this application; the terms "comprising," "including," "having," "containing," etc., in the description, claims, and accompanying drawings of this application are open-ended terms. Therefore, "comprising," "including," or "having" refers to, for example, a method or apparatus having one or more steps or elements, but is not limited to having only these one or more elements. The terms "first," "second," etc., in the description, claims, or accompanying drawings of this application are used to distinguish different objects, not to describe a specific order or hierarchy. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0024] In the description of this invention, it should be understood that the terms "upper", "lower", "left", "right", "front", "rear", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0025] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "attachment" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0026] It should be emphasized that when the term "comprising / including" is used in this specification, it is used to explicitly indicate the presence of the stated feature, integer, step, or component, but does not exclude the presence or addition of one or more other features, integers, steps, parts, or groups of features, integers, steps, or parts.

[0027] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, in this application, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0028] See Figures 1-3 A low-jitter pulse signal generation circuit according to an embodiment of the present invention includes an FPGA chip U1, a low-jitter clock phase-locked loop chip U2, a clock fan-out chip U3, and a high-speed driver chip U4; the control port of the low-jitter clock phase-locked loop chip U2 is connected to the general-purpose input / output pin of the FPGA chip U1, and the reference clock input terminal of the low-jitter clock phase-locked loop chip U2 is connected to a crystal oscillator U5 or to an external reference clock input interface U6; The first clock output terminal of the low-jitter clock phase-locked loop chip U2 is connected to the dedicated clock input pin of the FPGA chip U1; the input terminal of the clock fan-out chip U3 is connected to the second clock output terminal of the low-jitter clock phase-locked loop chip U2. The data input terminal of the high-speed driver chip U4 is connected to the output terminal of the clock fan-out chip U3, the output enable pin of the high-speed driver chip U4 is connected to the general-purpose input / output pin of the FPGA chip U1, and the data output terminal of the high-speed driver chip U4 is connected to the digital pulse signal output interface U7.

[0029] The FPGA chip U1 described in this invention is programmed to configure the output clock frequency of the low-jitter clock phase-locked loop chip U2, and to generate and output a control signal to the output enable pin of the high-speed driver chip U4. This invention utilizes the low-jitter output capability of the low-jitter clock phase-locked loop chip U2 and the clock fan-out chip U3 to generate a low-jitter periodic signal. By employing the FPGA chip U1 and the high-speed driver chip U4 with an output enable pin, pulse output control of the low-jitter periodic signal is achieved, thus realizing the effect of generating a low-jitter pulse signal.

[0030] FPGA chip U1 is connected to the control pins of PLL / VCO U2 via general-purpose I / O to configure the output clock frequency of PLL / VCO U2. One clock output pin of PLL / VCO U2 is connected to the dedicated clock pin of FPGA chip U1 to send the clock to FPGA chip U1. Another clock output pin of PLL / VCO U2 is connected to the input pin of clock fan-out chip U3. The reference clock pin of PLL / VCO U2 is connected to crystal oscillator U5 or to external reference clock input interface U6.

[0031] The output pin of the clock fan-out chip U3 is connected to the input pin of the high-speed drive chip U4 with an output enable pin. The output pin of the high-speed drive chip U4 with an output enable pin is connected to the digital pulse signal output interface U7. The output enable pin of the high-speed drive chip U4 with an output enable pin is connected to the IO of the FPGA chip U1.

[0032] Program the FPGA chip U1 to configure the registers of the PLL / VCO U2. The main functions include but are not limited to: selecting the frequencies / periods of the reference clock input and the output clock signal. Depending on different usage scenarios, the reference clock input can be configured as the crystal oscillator U5 or the external reference clock input interface U6. When configured as the crystal oscillator U5, the circuit operates independently. When configured as the external reference clock input interface U6, it operates in coherent synchronization with an external system or circuit. Configure the registers of the PLL / VCO U2 according to the pulse width of the required generated pulse signal to set the period of its output clock signal to twice the pulse width.

[0033] Program the FPGA chip U1 to achieve dynamic control of the output enable pin of the high-speed drive chip U4 with an output enable pin. The following is a code implemented on the FPGA chip U1: reg[31:0] pulse_period = 1000; reg[31:0] pulse_cnt; assign sma_pulse_en = (pulse_cnt == 1’b1); always @(negedge SYNC_1M_TO_FPGA) begin if(pulse_cnt <pulse_period) pulse_cnt <= pulse_cnt + 1; else pulse_cnt <=0; end The FPGA code implements a counter function, that is, pulse_cnt is incremented at the falling edge of SYNC_1M_TO_FPGA until the condition pulse_cnt <pulse_period is not satisfied, and then pulse_cnt is cleared. Here, SYNC_1M_TO_FPGA is a clock signal sent from a clock output pin of the PLL / VCO U2 connected to a dedicated clock pin of the FPGA chip U1 to the FPGA chip U1.

[0034] The pulse_period defines the period of the pulse signal.

[0035] When sma_pulse_en is high, the output pin of the high-speed driver chip U4 with the output enable pin is allowed to output a signal, which is in the same state as the clock output pin of the PLL / VCO U2. That is, when the clock output pin of the PLL / VCO U2 is high, the output pin of the high-speed driver chip U4 with the output enable pin is high, and when the clock output pin of the PLL / VCO U2 is low, the output pin of the high-speed driver chip U4 with the output enable pin is low.

[0036] This invention utilizes the low-jitter characteristics of PLL / VCO chips and clock fan-out chips to generate low-jitter periodic signals. An FPGA and a high-speed driver chip with an output enable pin are used to control the pulse output of the low-jitter periodic signal, generating a low-jitter pulse signal. Taking advantage of the large pulse period and the large setup and hold timing margin of the enable signal, the FPGA's I / O controls the output switching of the driver chip, reducing time jitter compared to directly outputting pulse signals via ordinary FPGA I / O.

[0037] This invention features extremely low output signal jitter: it utilizes a specialized low-jitter clock phase-locked loop chip and a clock fan-out chip to generate a periodic clock signal that inherently possesses extremely low jitter, typically ranging from hundreds of femtoseconds (fs) to picoseconds (ps). The final output pulse signal is essentially a time slice of this high-quality clock signal. By ensuring that the jitter of the control slice enable signal PULSE_EN does not affect the precise timing of the slice action, the jitter of the output pulse is locked at the jitter level of the CLK_OUT signal, achieving ultra-low jitter output at the picosecond level.

[0038] This invention eliminates the reliance on high-end FPGAs: it can be implemented using only conventional FPGAs or even low-cost FPGAs with general-purpose I / O and dedicated clock input pins. The FPGA primarily handles configuration management and low-frequency enable signal generation, with minimal requirements for its internal operating frequency and performance, significantly reducing system hardware costs.

[0039] This invention offers excellent timing margin and reliability: by setting the pulse period T to be much larger than the pulse width Tw, the edge transition of the FPGA-generated enable control signal PULSE_EN can have a very relaxed setup / hold time window. Even if there is some delay uncertainty in the FPGA's internal logic, i.e., its own I / O output has jitter, it can be completely ensured that this jitter will not cause metastability or erroneous switching actions at the enable terminal of the driver chip. Thus, the system design completely blocks the transmission path of FPGA jitter to the final output signal, ensuring stable and reliable system operation.

[0040] This invention offers high flexibility and scalability: the pulse width Tw can be continuously or incrementally adjusted by configuring the phase-locked loop (PLL) output frequency; the pulse period T can be flexibly set by modifying the modulus of the internal counter in the FPGA. Furthermore, a single low-jitter clock PLL chip can output multiple clock signals, a single clock fan-out chip can provide multiple fan-out signals, and a single driver chip may integrate multiple drivers. Therefore, the architecture of this invention can be easily expanded into a multi-channel low-jitter pulse generator with excellent synchronization characteristics between channels and low expansion costs.

[0041] This invention supports both internal and external clock references, making it suitable for a wide range of applications: the circuit design supports both internal crystal oscillator and external reference clock modes. The internal crystal oscillator mode ensures independent operation of the device; the external reference clock mode allows the device to lock onto a higher-level system master clock, achieving ultra-precise synchronization between multiple devices, which is particularly suitable for large-scale distributed systems.

[0042] Furthermore, the pulse width of the pulse signal generated by the FPGA chip U1 is set by the register of the low-jitter clock phase-locked loop chip U2, and the period of its output clock signal is twice the pulse width.

[0043] This invention sets a specific frequency clock output by a phase-locked loop (PLL), so that the duration of half a cycle of this clock signal, i.e., the high or low level, is exactly equal to the desired pulse width.

[0044] Furthermore, the FPGA chip U1 contains an enable signal generation logic module.

[0045] The enable signal generation logic module uses the first clock output CLK_TO_FPGA provided by the low-jitter clock phase-locked loop chip U2 as the synchronous clock to generate a periodic enable control signal PULSE_EN. The effective level duration of the enable control signal PULSE_EN is equal to the period T of the target pulse signal, and there is a preset time margin between its edge change time and the edge of the clock signal CLK_TO_FANOUT.

[0046] Furthermore, the FPGA chip U1 includes a counter module.

[0047] The counter module counts using the synchronous clock CLK_TO_FPGA as the clock source, and its modulus is determined by the ratio of the target pulse period T to the synchronous clock period; when the counter value is within a specific range, it outputs the valid enable control signal PULSE_EN.

[0048] The specific range is the first count value of the counter, such that the effective level duration of the enable control signal (PULSE_EN) is equal to one of the synchronous clock cycles.

[0049] Furthermore, the low-jitter clock phase-locked loop chip U2 is a phase-locked loop chip with an integrated voltage-controlled oscillator.

[0050] This invention is a single-chip solution that integrates a phase-locked loop (PLL) core and a voltage-controlled oscillator (VCO) within the same package. The PLL is responsible for locking the output frequency of the internal VCO to a more stable external reference clock, sourced from crystal oscillator U5 or external system U6. This process tracks and eliminates the frequency drift of the VCO itself and can generate an output frequency precisely proportional to the reference frequency through a programmable divider N. This is the foundation for achieving precise frequency programmability.

[0051] The voltage-controlled oscillator (VCO) is the actual source of the high-frequency output clock signal. Its oscillation frequency is adjusted by the control voltage generated by the PLL loop filter. The phase noise performance of the VCO itself directly determines the jitter level of the output clock signal.

[0052] Furthermore, the clock fan-out chip U3 is a clock buffer or fan-out buffer with ultra-low added jitter.

[0053] This invention ensures that the noise it introduces is on the same order of magnitude as, or even lower than, the source jitter of U2, so that the total jitter budget of the entire clock chain is still dominated by the best source, U2. This is a necessary guarantee for achieving picosecond-level output jitter. Using a dedicated fan-out buffer ensures multi-channel consistency: the delay difference between each output channel, i.e., the output-to-output offset, is extremely small, such as <20ps, which is crucial for applications requiring multiple strictly synchronized pulses. It also ensures waveform integrity: even when driving multiple loads in the subsequent stage, each output maintains clean, steep clock edges, providing an ideal input signal for U4.

[0054] Furthermore, the high-speed driver chip U4 is a low-voltage differential signal driver, a current-mode logic driver, or a high-speed logic gate array with tri-state outputs.

[0055] Low-voltage differential signal drivers, current-mode logic drivers, or high-speed logic gate arrays with tri-state outputs all support data rates from hundreds of MHz to several GHz. Their extremely fast output edges and short rise / fall times ensure steep output pulse edges, which complements the goal of low jitter—clear edges contribute to accurate timing. All three types of the high-speed driver chip U4 have output enable (OE) or tri-state control: this is the physical basis for implementing FPGA "window gating" control. The OE pin allows an external signal from the FPGA's PULSE_EN to place the output in a high-impedance state (off) or an active state (on). All three types of the high-speed driver chip U4 have low added jitter: as professional high-speed drivers, they are designed and manufactured with low added jitter in mind, and this parameter is clearly stated in their datasheets. They are selected to ensure minimal degradation of signal timing in the final stage of driving the output.

[0056] Furthermore, the FPGA U1 is model XC7Z100-2FFG900I; the low-jitter clock phase-locked loop chip U2 is model HMC7044LP10BE; the clock fan-out chip U3 is model 5PB1110PGG; and the high-speed drive chip U4 is model CDCLVC1102PWR.

[0057] The XC7Z100-2FFG900I integrates an ARM processor and FPGA programmable logic. It not only requires FPGA logic for counting and enable control, but also leverages its processor core for complex register configurations, such as configuring the HMC7044 via SPI or system management. It represents a high-performance, interface-rich programmable platform.

[0058] The core of the HMC7044LP10BE is a PLL+VCO, providing multiple programmable, ultra-low jitter outputs. It perfectly matches the definition of a "low-jitter clock phase-locked loop chip" in the claims and is the core hardware guarantee for achieving the low-jitter source in this invention.

[0059] The 5PB1110PGG is an ultra-low jitter, high-fanout clock fanout buffer. With extremely low jitter (typically <100 fs), it is designed for distributing high-frequency, low-jitter clocks. It ensures that the quality of the high-quality clock signal from the HMC7044 is not degraded during distribution.

[0060] The CDCLVC1102PWR is a low-jitter, general-purpose LVCMOS clock buffer / driver with output enable functionality. It conforms to the description of a high-speed driver chip with an output enable pin, capable of driving signals to standard logic levels with low added jitter and accepting precise FPGA control via the OE pin.

[0061] Furthermore, the crystal oscillator U5 is model NT0503EH3I507EN10; the external clock input interface U6 is of type SMA.

[0062] The TCXO-type NT0503EH3I507EN10 crystal oscillator U5 features high stability and low phase noise: OCXO temperature-controlled crystal oscillators exhibit extremely high frequency stability and extremely low phase noise over a wide temperature range, with phase noise and jitter levels far superior to ordinary XO crystal oscillators and even temperature-compensated crystal oscillators (TCXO). The external clock input interface U6 uses an SMA type connector, clearly indicating that this is a professional interface suitable for high frequencies, typically up to 26.5GHz or higher, requiring impedance matching of 50 ohms and good shielding.

[0063] Furthermore, the digital pulse signal output interface U7 is of type SMA.

[0064] SMA is a widely used semi-rigid, thread-locked RF coaxial connector. Here, it is designated as the output interface, ensuring a high-frequency, high-signal-integrity output channel. Standard impedance: The standard impedance of the SMA interface is 50 ohms. This is completely consistent with the transmission line impedance standard commonly used in high-speed digital circuits and measuring instruments. Wide bandwidth performance: High-quality SMA connectors can operate in a frequency range from DC to 18 GHz or even higher. This means that for pulse edges in the nanosecond and even sub-nanosecond range, with spectral components extending to GHz, the SMA interface can guarantee extremely low insertion loss and reflection, ensuring that the fast edges of pulses pass through without loss. Excellent shielding: The all-metal housing and thread-locked structure provide near-perfect electromagnetic shielding, preventing internal signal leakage and external interference intrusion, protecting the "purity" of low-jitter signals.

[0065] While the present invention has been disclosed above, its scope of protection is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, and all such changes and modifications will fall within the scope of protection of the present invention.

Claims

1. A low-jitter pulse signal generation circuit, characterized in that, It includes an FPGA chip U1, a low-jitter clock phase-locked loop chip U2, a clock fan-out chip U3, and a high-speed driver chip U4; the control port of the low-jitter clock phase-locked loop chip U2 is connected to the general-purpose input / output pin of the FPGA chip U1, and the reference clock input terminal of the low-jitter clock phase-locked loop chip U2 is connected to a crystal oscillator U5 or an external reference clock input interface U6. The first clock output terminal of the low-jitter clock phase-locked loop chip U2 is connected to the dedicated clock input pin of the FPGA chip U1; the input terminal of the clock fan-out chip U3 is connected to the second clock output terminal of the low-jitter clock phase-locked loop chip U2. The data input terminal of the high-speed driver chip U4 is connected to the output terminal of the clock fan-out chip U3, the output enable pin of the high-speed driver chip U4 is connected to the general-purpose input / output pin of the FPGA chip U1, and the data output terminal of the high-speed driver chip U4 is connected to the digital pulse signal output interface U7.

2. The low-jitter pulse signal generation circuit according to claim 1, characterized in that, The pulse width of the pulse signal generated by the FPGA chip U1 is set by the register of the low-jitter clock phase-locked loop chip U2, and the period of its output clock signal is twice the pulse width.

3. The low-jitter pulse signal generation circuit according to claim 2, characterized in that, The FPGA chip U1 contains an enable signal generation logic module.

4. The low-jitter pulse signal generation circuit according to claim 3, characterized in that, The FPGA chip U1 has a built-in counter module.

5. The low-jitter pulse signal generation circuit according to claim 4, characterized in that, The low-jitter clock phase-locked loop chip U2 is a phase-locked loop chip with an integrated voltage-controlled oscillator.

6. The low-jitter pulse signal generation circuit according to claim 5, characterized in that, The clock fan-out chip U3 is a clock buffer or fan-out buffer with ultra-low added jitter.

7. The low-jitter pulse signal generation circuit according to claim 6, characterized in that, The high-speed driver chip U4 is a low-voltage differential signal driver, a current-mode logic driver, or a high-speed logic gate array with tri-state outputs.

8. The low-jitter pulse signal generation circuit according to claim 1, characterized in that, The FPGA U1 is model XC7Z100-2FFG900I; the low-jitter clock phase-locked loop chip U2 is model HMC7044LP10BE; the clock fan-out chip U3 is model 5PB1110PGG; and the high-speed driver chip U4 is model CDCLVC1102PWR.

9. The low-jitter pulse signal generation circuit according to claim 8, characterized in that, The crystal oscillator U5 is model NT0503EH3I507EN10; the external clock input interface U6 is of type SMA.

10. The low-jitter pulse signal generation circuit according to claim 9, characterized in that, The digital pulse signal output interface U7 is of type SMA.

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