Chip detection method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a chip detection method and device, electronic equipment and a storage medium, and can solve the problem that the detection of a digital-analog chip is not accurate enough due to the fact that an existing chip possibly cannot reflect related functions in the digital-analog chip very accurately. Obtaining original simulation data of the to-be-tested chip; based on the original simulation data, a target test chip is run, the target test chip is a chip obtained after the programmable integrated circuit chip simulates the function of the current version of the chip to be tested, and the current version is a version after version iteration; in the running process of the target test chip, running indexes are collected, and the detection result of the to-be-tested chip is determined according to the running indexes.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a chip testing method, apparatus, electronic device and storage medium. Background Technology

[0002] During the development of analog-to-digital (ADC) chips, the digital functions and algorithms of the chips need to be iterated and upgraded multiple times. Therefore, each time an ADC chip is updated or iterated, it needs to be tested. Typically, during testing, commercially available chips with the same functional characteristics as the ADC chip are used to simulate it. However, in some complex scenarios, existing chips may not accurately represent the relevant functions of the ADC chip, resulting in inaccurate ADC chip testing. Summary of the Invention

[0003] To solve the above-mentioned technical problems, or at least partially solve them, embodiments of this application provide a chip detection method, apparatus, electronic device, and storage medium to address the problem that existing chips cannot accurately reflect the relevant functions in analog-to-digital chips, resulting in inaccurate detection of analog-to-digital chips.

[0004] To achieve the above objectives, the technical solutions provided in this application are as follows: In a first aspect, embodiments of this application provide a chip detection method, the method comprising: Obtain the raw analog data of the chip under test; Based on the original simulation data, the target test chip is run. The target test chip is a chip obtained by simulating the current version of the chip under test through a programmable integrated circuit chip. The current version is a version after version iteration. During the operation of the target test chip, operating indicators are collected, and the test results of the chip under test are determined based on the operating indicators.

[0005] As an optional implementation, in a first aspect of this application, acquiring the raw analog data of the chip under test includes: The target test chip and the chip under test (DUT) communicate through a communication link between them. The DUT receives raw analog data sent by the DUT. The communication link is formed by connecting the first interface of the DUT and the second interface of the target test chip.

[0006] As an optional implementation, in the first aspect of the embodiments of this application, after acquiring the raw analog data of the chip under test, the method further includes: The target test chip is used to parse the original simulation data to obtain the analog quantities included in the original simulation data; The step of running the target test chip based on the original simulation data includes: The target test chip is run based on the simulated quantities.

[0007] As an optional implementation, in a first aspect of this application, the step of parsing the original analog data through the target test chip to obtain the analog quantities included in the original analog data includes: The device receives a data protocol sent by the chip under test (DUT), which is the protocol used by the DUT to package the collected analog quantities into the raw analog data. Using the target test chip, the original simulation data is parsed according to the data protocol to obtain the analog quantities included in the original simulation data.

[0008] As an optional implementation, in a first aspect of the embodiments of this application, running the target test chip based on the analog quantity includes: Extract configuration information from the original simulation data; Based on the configuration information, determine the digital logic module corresponding to the configuration information in the target test chip; The analog signal is sent to the digital logic module so that the digital logic module is run based on the analog signal.

[0009] As an optional implementation, in a first aspect of this application, determining the detection result of the chip under test based on the operating indicators includes: The operational indicators are compared with a preset range of indicators to obtain the comparison results; If the comparison result indicates that the operating index is within the preset index range, then the test result of the chip under test is determined to be operating normally; If the comparison result indicates that the operating indicator is not within the preset indicator range, then the detection result of the chip under test is determined to be an abnormal operation.

[0010] As an optional implementation, in the first aspect of the embodiments of this application, after determining the detection result of the chip under test based on the operating indicators, the method further includes: If the detection result indicates that the chip under test is malfunctioning, then malfunction information is output, which is used to instruct maintenance personnel to perform iterative checks on the current version of the chip under test.

[0011] Secondly, embodiments of this application provide a chip testing apparatus, the apparatus comprising: The acquisition module is used to acquire the raw analog data of the chip under test; The processing module is used to run a target test chip based on the original simulation data. The target test chip is a chip obtained by simulating the current version of the chip under test using a programmable integrated circuit chip. The current version is a version after version iteration. The processing module is also used to collect operating indicators during the operation of the target test chip, and determine the test result of the chip under test based on the operating indicators.

[0012] As an optional implementation, in a second aspect of the embodiments of this application, the acquisition module is specifically used to receive raw analog data sent by the chip under test through a communication link between the target test chip and the chip under test, wherein the communication link is obtained by connecting a first interface of the chip under test and a second interface of the target test chip.

[0013] As an optional implementation, in a second aspect of the embodiments of this application, the processing module is further configured to parse the original simulation data through the target test chip to obtain the analog quantities included in the original simulation data; The processing module is specifically used to run the target test chip based on the analog quantity.

[0014] As an optional implementation, in a second aspect of the embodiments of this application, the acquisition module is specifically used to receive a data protocol sent by the chip under test, wherein the data protocol is the protocol used by the chip under test when it packages the collected analog quantities into the original analog data; The processing module is specifically used to parse the original simulation data through the target test chip according to the data protocol to obtain the analog quantities included in the original simulation data.

[0015] As an optional implementation, in a second aspect of the embodiments of this application, the processing module is specifically used to extract configuration information from the original simulation data; The processing module is specifically used to determine, based on the configuration information, the digital logic module corresponding to the configuration information in the target test chip; The processing module is specifically used to send the analog quantity to the digital logic module so that the digital logic module runs based on the analog quantity.

[0016] As an optional implementation, in a second aspect of the embodiments of this application, the processing module is specifically used to compare the operating indicators with a preset indicator range to obtain a comparison result; The processing module is specifically used to determine that the test result of the chip under test is normal if the comparison result indicates that the operating index is within the preset index range; The processing module is specifically used to determine that the detection result of the chip under test is abnormal if the comparison result indicates that the operating index is not within the preset index range.

[0017] As an optional implementation, in a second aspect of the embodiments of this application, the processing module is further configured to output operation abnormality information if the detection result indicates that the chip under test is operating abnormally, and the operation abnormality information is used to instruct maintenance personnel to perform iterative checks on the current version of the chip under test.

[0018] Thirdly, embodiments of this application provide an electronic device, the electronic device comprising: Memory containing executable program code; A processor coupled to the memory; The processor calls the executable program code stored in the memory to execute the chip detection method in the first aspect of the embodiments of this application.

[0019] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that causes a computer to execute the chip detection method of the first aspect of embodiments of this application. The computer-readable storage medium includes ROM / RAM, a magnetic disk, or an optical disk, etc.

[0020] Fifthly, embodiments of this application provide a computer program product that, when run on a computer, causes the computer to perform some or all of the steps of any of the methods of the first aspect.

[0021] Sixthly, embodiments of this application provide an application publishing platform for publishing computer program products, wherein when the computer program product is run on a computer, the computer performs some or all of the steps of any of the methods of the first aspect.

[0022] Compared with the prior art, the embodiments of this application have the following beneficial effects: This application provides a chip testing method, apparatus, electronic device, and storage medium. The method involves acquiring raw simulation data of the chip under test (DUT); running a target test chip based on the raw simulation data. The target test chip is a chip obtained by simulating the current version of the DUT's functionality using a programmable integrated circuit (PLC) chip, where the current version is a version that has undergone iterations. During the execution of the target test chip, operational indicators are collected, and the test results of the DUT are determined based on these indicators. In this solution, the functional characteristics of the DUT are simulated using a PLC chip, transferring the functional testing of the DUT to the PLC chip for execution. Furthermore, by running the version-iterated chip using the raw simulation data of the DUT chip, the target test chip can more closely match the operating state of the DUT chip, effectively improving the detection accuracy of the DUT chip. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a flowchart illustrating a chip detection method provided in an embodiment of this application. Figure 1 ; Figure 2 This is a flowchart illustrating a chip detection method provided in an embodiment of this application. Figure 2 ; Figure 3 This is a schematic diagram of the structure of a chip detection device provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0026] To better understand the above-mentioned objectives, features, and advantages of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features of this application can be combined with each other. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0027] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, rather than to describe a specific order of objects.

[0028] The terms “comprising” and “having”, and any variations thereof, in this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.

[0029] It should be noted that in the embodiments of this application, the words "exemplary" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the words "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0030] A mixed-signal chip (MSC) is a chip that can process both digital and analog signals simultaneously. Digital signals are discrete and discontinuous, typically represented by binary code, such as data in a computer. Analog signals are continuously changing signals, continuous in both time and amplitude, such as the signals generated by sensors after converting physical quantities like sound and temperature. In MSCs, the characteristics of analog IP are determined by factors such as the foundry, chip manufacturing process, selected process components, and analog circuit design. Analog IP refers to pre-designed circuit modules with specific analog functions. These modules can be reused in different chip designs to accelerate the chip design process and reduce design costs and risks. Analog IP covers various analog circuit functions, such as amplifiers, filters, analog-to-digital converters (ADCs), and digital-to-analog converters (DACs). Analog IP has specific performance indicators and interface specifications, and its performance must be considered during design due to factors such as process technology, voltage, and temperature.

[0031] A foundry, also known as a wafer foundry, is responsible for transforming chip design drawings into actual chip products according to design requirements. The process level and production capacity of a foundry directly affect chip performance, cost, and yield. Different foundries may use different manufacturing processes and materials, resulting in differences in the characteristics of the produced chips. Chip manufacturing process typically refers to the linewidth, also known as feature size, in semiconductor manufacturing processes, measured in nanometers (nm). It represents the width of the transistor gate on the chip. A smaller linewidth means more transistors can be integrated on the same chip area, thereby improving chip performance and integration density while reducing power consumption and cost. During chip manufacturing, various process components are selected to implement different circuit functions. These components include transistors, diodes, capacitors, and inductors, and their performance and characteristics are affected by the manufacturing process. The type and parameters of the selected process components directly affect the performance of analog IP, such as gain, bandwidth, and noise. Therefore, when designing analog IP, it is necessary to select appropriate process components based on specific application requirements. Analog circuit design refers to designing circuits for processing analog signals, including functions such as amplification, filtering, conversion, modulation, and demodulation. Analog circuit design needs to consider factors such as signal integrity, noise, and distortion to ensure that the circuit can accurately process analog signals.

[0032] Board-level testing is performed after a chip is soldered onto a printed circuit board (PCB) to verify its functionality and performance in a real-world circuit environment. Board-level testing can detect issues such as chip compatibility with surrounding circuits, signal transmission quality, and power integrity. Finding devices with identical characteristics to simulate the IP characteristics during board-level testing is challenging. For example, many analog-to-digital (ADC) chips integrate analog IP for analog-to-digital conversion. Typically, existing ADC chips on the market are used for ADC conversion during chip verification. However, the characteristics of existing ADC chips and the integrated ADC analog IP within the ADC chip differ significantly. In complex scenarios, existing ADC chips cannot fully demonstrate the characteristics of the integrated ADC analog IP. This discrepancy between the chip verification environment and actual chip usage leads to insufficient and unrealistic verification. Furthermore, the analog-to-digital interface is usually internal to the chip, making it difficult to observe and further complicating board-level verification.

[0033] When iterating the digital functions of analog-digital chips, the inability to provide inputs with the same characteristics as the internal analog IP of the chip design makes it impossible to fully reproduce many of the more complex pre-set usage methods during chip verification. This results in insufficient chip verification scenarios and inadequate verification.

[0034] Given the availability of an initial-generation chip, the characteristics exhibited by differences in process technology, fabrication, and design can be fully realized within that chip. Data acquired through the chip's analog IP can be obtained from the initial-generation chip. Therefore, when iterating over a newer chip, data acquired through analog IP with identical characteristics is already available. At this point, a method combining the initial-generation chip and an FPGA verification platform is needed to complete board-level verification of the iterative chip for practical applications, enabling the iterative chip's digital logic to cover more real-world scenarios.

[0035] To address some or all of the aforementioned technical problems, embodiments of this application provide a chip testing method, apparatus, electronic device, and storage medium. The method involves acquiring raw simulation data of the chip under test (DUT); running a target test chip based on the raw simulation data. The target test chip is a chip obtained by simulating the current version of the DUT's functionality using a programmable integrated circuit (PLC) chip, where the current version is a version that has undergone iterations. During the operation of the target test chip, operational indicators are collected, and the test results of the DUT chip are determined based on these indicators. In this solution, the functional characteristics of the DUT chip are simulated using a PLC chip, transferring the functional testing of the DUT chip to the PLC chip for execution. Furthermore, by running the version-iterated chip using the raw simulation data of the DUT chip, the target test chip can more closely match the operating state of the DUT chip, effectively improving the detection accuracy of the DUT chip.

[0036] Figure 1 A flowchart of a chip detection method provided in this application embodiment, the method may include the following steps: 101. Obtain the raw analog data of the chip under test.

[0037] In this application embodiment, the chip under test can be a digital-to-analog chip that needs to test the characteristics of analog IP. The original analog data can be the analog data of the analog IP collected when the chip under test is in the first generation mode. It can also be understood that the chip under test at this time is the first generation chip, which has not yet undergone functional iteration or algorithm upgrade. The original analog data of the first generation chip can be regarded as the source data of the first generation, which is the data basis for all subsequent upgrades of the chip under test.

[0038] It should be noted that since the analog-to-digital chip includes multiple analog IPs, and each analog IP generates corresponding analog data, the raw analog data obtained here can include the analog data corresponding to at least one analog IP. In other words, if we need to test the characteristic of a particular analog IP of the chip under test, then we can obtain the analog data corresponding to that characteristic of that analog IP.

[0039] 102. Run the target test chip based on the original simulation data.

[0040] In this embodiment, after obtaining the original simulation data, it is necessary to test the chip under test (DUT) which has undergone updates and iterations using the original simulation data. To achieve accurate testing, a target test chip with the same functional characteristics as the DUT can be used for testing. The target test chip can be a Field-Programmable Gate Array (FPGA) chip. The FPGA chip can be directly programmed, meaning that the FPGA chip can be programmed to simulate the functional characteristics of the DUT. Therefore, an original programmable integrated circuit chip (FPGA chip) can be selected to simulate the current version of the DUT's functionality, thereby obtaining the target test chip. At this time, the target test chip can be equivalent to the DUT, and the DUT can be tested by running the target test chip.

[0041] It should be noted that, since the original simulation data can be understood as the initial data of the chip under test (DUT), the DUT has not yet undergone version updates when the original simulation data is collected. Therefore, it is not necessary to test the DUT at this time. Testing is only required when the DUT has undergone version updates. Thus, the current version of the DUT simulated by the target test chip can be a version that has undergone iterations, not the initial version. In other words, the scenario applicable to the embodiments of this application is when the DUT has undergone version updates.

[0042] 103. During the operation of the target test chip, collect operating indicators and determine the test results of the chip under test based on the operating indicators.

[0043] In this embodiment of the application, since the target test chip is obtained by simulating the chip under test, the operating state of the target test chip can reflect the operating state of the chip under test. Therefore, during the operation of the target test chip, the operating indicators of the target test chip can be collected and the operating indicators can be detected to obtain the detection result of the target test chip, which is also the detection result of the chip under test.

[0044] It should be noted that this operating metric can be an indicator that can be used to measure the chip's operating status. Generally speaking, when detecting the chip's operating status, the chip's accuracy or response time will be judged. Therefore, this operating metric can include parameters such as operating accuracy and response time.

[0045] This application provides a chip testing method that acquires raw simulation data of the chip under test (DUT); based on the raw simulation data, a target test chip is run. The target test chip is a chip obtained by simulating the current version of the DUT's functionality using a programmable integrated circuit (PLC) chip, where the current version is a version that has undergone iterations. During the execution of the target test chip, operational indicators are collected, and the test results of the DUT are determined based on these indicators. In this scheme, the functional characteristics of the DUT are simulated using a PLC chip, transferring the functional testing of the DUT to the PLC chip for execution. Furthermore, by running the version-iterated chip using the raw simulation data of the DUT chip, the target test chip can more closely match the operating state of the DUT chip, effectively improving the detection accuracy of the DUT chip.

[0046] like Figure 2 As shown, Figure 2 A flowchart of a chip detection method provided in this application embodiment, the method may further include the following steps: 201. Receive the raw analog data sent by the chip under test through the communication link between the target test chip and the chip under test.

[0047] In this embodiment of the application, when acquiring the original simulation data, since the original simulation data is all collected by the chip under test itself, the chip under test can send the original simulation data, and then the target test chip can receive the original simulation data sent by the chip under test.

[0048] A communication link can be established between the target test chip and the chip under test (DUT). The target test chip receives raw analog data sent by the DUT through this communication link. This communication link can be formed by connecting a first interface of the DUT and a second interface of the target test chip.

[0049] It should be noted that on the chip under test side, an IO logic module with IO multiplexing function can be set up. There is an IO pin on the IO logic module. This IO pin can output the raw analog data that needs to be output to the chip PAD. The chip PAD is the metal area on the chip surface used for electrical connection. It is the key physical interface for the chip to interact with the outside world, that is, the first interface of the chip under test.

[0050] Similarly, on the target test chip side, a logic module can be set up to receive raw analog data via I / O. This module can also have a pin to receive data transmitted from the chip PAD, which is the second interface of the target test chip. Connecting the first interface of the chip under test (DUT) and the second interface of the target test chip creates a communication link between them, allowing the target test chip to receive the raw analog data sent by the DUT.

[0051] 202. Using the target test chip, the original simulation data is analyzed to obtain the analog quantities included in the original simulation data.

[0052] In this embodiment, after the chip under test (DUT) acquires the analog quantity of the simulated IP, it needs to package the analog quantity before sending it. This may involve adding data such as frame headers, frame trailers, and checksums to the analog quantity to form a data packet, which can be called the raw analog data. The DUT can send the entire data packet to the target test chip. After receiving the raw analog data, the target test chip needs to parse the raw analog data and extract the specific analog quantity from it in order to obtain the analog quantity of the specific simulated IP.

[0053] In some embodiments, the target test chip parses the original analog data to obtain the analog quantities included in the original analog data. Specifically, this may include: receiving a data protocol sent by the chip under test; and parsing the original analog data according to the data protocol using the target test chip to obtain the analog quantities included in the original analog data.

[0054] It should be noted that the chip under test (DUT) can use a custom protocol when packaging analog signals to obtain raw analog data. In other words, it can package custom data into analog signals, which is not the commonly used communication protocol. If the target test chip does not know the protocol content, it cannot parse the raw analog data. Therefore, the target test chip also needs to receive the data protocol sent by the DUT. This data protocol can be a protocol negotiated between the target test chip and the DUT. The DUT can use this data protocol when packaging the collected analog signals into raw analog data. Similarly, the target test chip can also use this data protocol when parsing the raw analog data to obtain accurate analog signals.

[0055] 203. Run the target test chip based on analog signals.

[0056] In this embodiment of the application, after parsing the analog quantity, the target test chip can be run based on the analog quantity.

[0057] In some embodiments, running a target test chip based on analog signals may specifically include: extracting configuration information from raw analog data; determining a digital logic module in the target test chip corresponding to the configuration information based on the configuration information; and sending analog signals to the digital logic module so that the digital logic module runs based on the analog signals.

[0058] It should be noted that the chip under test (DUT) can be a digital-to-analog chip, which includes multiple analog IP features. These analog IP features may all need to be tested. Different analog IPs are used to implement different functions, and thus, in the target DUT, they can correspond to different digital logic modules. The analog signals of different analog IPs need to be forwarded to the corresponding digital logic modules for execution. Therefore, configuration information can be extracted from the original analog data. This configuration information can be used to indicate the analog IP corresponding to the original analog data, thereby determining the digital logic module corresponding to the current analog IP based on the configuration information, and then sending the analog signal to the digital logic module to run the digital logic module.

[0059] For example, the analog signals acquired by the chip under test (DUT) through an analog ADC are packaged to obtain raw analog data, which is then sent to the target test chip. After parsing the analog signals, the target test chip can extract configuration information from the raw analog data. This configuration information indicates that the current raw analog data is for the analog ADC. Therefore, the target test chip can send the parsed analog signals to the ADC acquisition and processing circuit. This ADC acquisition and processing circuit can be a digital logic module that completely replicates the analog ADC. The ADC acquisition and processing circuit runs based on the analog signals, thereby detecting the operating status of the analog ADC of the DUT.

[0060] 204. Collect operating indicators during the operation of the target test chip.

[0061] 205. Compare the operating indicators with the preset indicator range to obtain the comparison results.

[0062] In this embodiment of the application, after collecting the operating indicators, since the operating indicators can characterize the operating status of the target test chip and the chip under test, it is necessary to detect the operating indicators to measure whether the operating status of the target test chip and the chip under test is normal. In order to better detect the operating indicators, a preset indicator range can be set for the operating indicators. By judging whether the operating indicators are within the preset indicator range, the operating status of the target test chip and the chip under test can be measured, thereby obtaining the comparison results.

[0063] It should be noted that since there may be more than one operational metric, these metrics may include those used to measure whether the simulated IP function can be implemented (e.g., CPU instruction execution accuracy, FPGA logic gate latency, interface transmission rate, etc.), those used to measure whether the simulated IP function implementation meets the standards (e.g., static leakage current, operating voltage, signal transmission delay, etc.), and those used to measure stability and reliability. Therefore, for each of these operational metrics, corresponding preset metric ranges can be set, and each operational metric can be compared with its corresponding preset metric range to obtain the comparison results for each operational metric.

[0064] 206. If the comparison result indicates that the operating index is within the preset index range, then the test result of the chip under test is determined to be normal operation.

[0065] In this embodiment of the application, after obtaining the comparison result, if the comparison result indicates that the operating index is within the preset index range, it means that the operating index is normal. If all operating indicators are normal, it can be said that the detection result of the target test chip is operating normally. Similarly, the detection result of the chip under test is also operating normally.

[0066] 207. If the comparison result indicates that the operating index is not within the preset index range, then the test result of the chip under test is determined to be an abnormal operation.

[0067] In this embodiment of the application, if the comparison result indicates that the operating index is not within the preset index range, it means that the operating index is abnormal. That is to say, the detection result of the target test chip is abnormal, and similarly, the detection result of the chip under test is also abnormal.

[0068] 208. If the test result indicates that the chip under test is malfunctioning, output the malfunction information. The malfunction information is used to instruct the maintenance personnel to perform iterative checks on the current version of the chip under test.

[0069] In this embodiment of the application, if the detection result indicates that the chip under test is malfunctioning, it means that the current version of the chip under test is abnormal and needs to be detected and maintained. Therefore, the abnormal operation information can be output to inform the operation and maintenance personnel so that the operation and maintenance personnel can perform iterative checks on the current version of the chip under test and modify or optimize the defects in the current version.

[0070] In some embodiments, after iteratively checking and modifying or optimizing the current version, the modified or optimized version can be replicated by the target test chip, and the target test chip can continue to be tested based on analog signals until the test result of the target test chip is found to be running normally. At this point, it is determined that the test result of the chip under test is also running normally.

[0071] This application provides a chip testing method that utilizes the characteristics of the analog IP of the chip under test (DUT) using an existing FPGA chip. This provides analog input signals with the same characteristics for verifying digital functions or algorithm iterations. Based on this FPGA chip, it can provide scenarios more closely aligned with the actual use of the DUT, making the verification of iterative chip digital functions or algorithm upgrades more comprehensive and effectively improving the accuracy of version verification for analog-digital chips.

[0072] like Figure 3 As shown in the figure, this application provides a chip testing device, which may include: The acquisition module 301 is used to acquire the raw analog data of the chip under test; The processing module 302 is used to run the target test chip based on the original simulation data. The target test chip is a chip obtained by simulating the current version of the chip under test through a programmable integrated circuit chip. The current version is the version after version iteration. The processing module 302 is also used to collect operating indicators during the operation of the target test chip, and to determine the test results of the chip under test based on the operating indicators.

[0073] In some embodiments, the acquisition module 301 is specifically used to receive raw analog data sent by the chip under test through a communication link between the target test chip and the chip under test. The communication link is formed by connecting a first interface of the chip under test and a second interface of the target test chip.

[0074] In some embodiments, the processing module 302 is further configured to parse the original simulation data through the target test chip to obtain the analog quantities included in the original simulation data; The processing module 302 is specifically used to run the target test chip based on analog signals.

[0075] In some embodiments, the acquisition module 301 is specifically used to receive the data protocol sent by the chip under test, which is the protocol used by the chip under test to package the collected analog quantities into raw analog data. The processing module 302 is specifically used to parse the original analog data according to the data protocol through the target test chip to obtain the analog quantities included in the original analog data.

[0076] In some embodiments, the processing module 302 is specifically used to extract configuration information from the original simulation data; The processing module 302 is specifically used to determine the digital logic module corresponding to the configuration information in the target test chip according to the configuration information; The processing module 302 is specifically used to send analog signals to the digital logic module so that the digital logic module can run based on the analog signals.

[0077] In some embodiments, the processing module 302 is specifically used to compare the operating indicators with a preset indicator range to obtain a comparison result; The processing module 302 is specifically used to determine that the test result of the chip under test is normal if the comparison result indicates that the operating index is within the preset index range; The processing module 302 is specifically used to determine that the test result of the chip under test is abnormal if the comparison result indicates that the operating index is not within the preset index range.

[0078] In some embodiments, the processing module 302 is further configured to output abnormal operation information if the detection result indicates that the chip under test is malfunctioning. The abnormal operation information is used to instruct maintenance personnel to perform iterative checks on the current version of the chip under test.

[0079] In this embodiment, each module can implement the chip detection method provided in the above method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0080] like Figure 4 As shown in the embodiments of this application, an electronic device is also provided, which may include: Memory 401 storing executable program code; Processor 402 coupled to memory 401; In this process, the processor 402 calls the executable program code stored in the memory 401 to execute the chip detection method performed by the electronic device in the above method embodiments.

[0081] This application provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the various processes of the chip detection method in the above-described method embodiments and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0082] This application also provides a computer program product, which stores a computer program. When the computer program is executed by a processor, it implements each process of the chip detection method in the above method embodiments and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0083] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code.

[0084] It should be understood, in the several embodiments provided in this application, that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0085] In this application, the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0086] In this application, memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, like read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0087] In this application, those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. This program can be stored in a computer-readable storage medium, including permanent and non-permanent, removable and non-removable storage media. The storage medium can implement information storage by any method or technology, and the information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), other types of random access memory (RAM), read-only memory (ROM), one-time programmable read-only memory (OTPROM), electrically-erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile optical disc (DVD) or other optical storage, magnetic tape, disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information that can be accessed by a computing device. As defined in this document, computer-readable media do not include transient media, such as modulated data signals and carrier waves.

[0088] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variations thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0089] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application. The above-mentioned multiple embodiments are not necessarily multiple independent embodiments; they are divided into multiple embodiments only to highlight different technical features in different embodiments. Those skilled in the art should understand that the above-mentioned multiple embodiments can also be combined arbitrarily.

[0090] In the various embodiments of this application, it should be understood that the sequence number of each process does not necessarily imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0091] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they can be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0092] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0093] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-accessible memory. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several requests to cause a computer device (which can be a personal computer, server, or network device, specifically a processor in the computer device) to execute some or all of the steps of the methods described in the various embodiments of this application.

[0094] The above are merely specific embodiments of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to these embodiments, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip detection method, characterized in that, The method includes: Obtain the raw analog data of the chip under test; Based on the original simulation data, the target test chip is run. The target test chip is a chip obtained by simulating the current version of the chip under test through a programmable integrated circuit chip. The current version is a version after version iteration. During the operation of the target test chip, operating indicators are collected, and the test results of the chip under test are determined based on the operating indicators.

2. The method according to claim 1, characterized in that, The acquisition of the raw analog data of the chip under test includes: The target test chip and the chip under test (DUT) communicate through a communication link between them. The DUT receives raw analog data sent by the DUT. The communication link is formed by connecting the first interface of the DUT and the second interface of the target test chip.

3. The method according to claim 1, characterized in that, After acquiring the raw analog data of the chip under test, the method further includes: The target test chip is used to parse the original simulation data to obtain the analog quantities included in the original simulation data; The step of running the target test chip based on the original simulation data includes: The target test chip is run based on the simulated quantities.

4. The method according to claim 3, characterized in that, The process involves parsing the original simulation data using the target test chip to obtain the analog quantities included in the original simulation data, including: The device receives a data protocol sent by the chip under test (DUT), which is the protocol used by the DUT to package the collected analog quantities into the raw analog data. Using the target test chip, the original simulation data is parsed according to the data protocol to obtain the analog quantities included in the original simulation data.

5. The method according to claim 3, characterized in that, The process of running the target test chip based on the analog quantity includes: Extract configuration information from the original simulation data; Based on the configuration information, determine the digital logic module corresponding to the configuration information in the target test chip; The analog signal is sent to the digital logic module so that the digital logic module is run based on the analog signal.

6. The method according to claim 1, characterized in that, Determining the test result of the chip under test based on the operating indicators includes: The operational indicators are compared with a preset range of indicators to obtain the comparison results; If the comparison result indicates that the operating index is within the preset index range, then the test result of the chip under test is determined to be operating normally; If the comparison result indicates that the operating indicator is not within the preset indicator range, then the detection result of the chip under test is determined to be an abnormal operation.

7. The method according to claim 1, characterized in that, After determining the test result of the chip under test based on the operating indicators, the method further includes: If the detection result indicates that the chip under test is malfunctioning, then malfunction information is output, which is used to instruct maintenance personnel to perform iterative checks on the current version of the chip under test.

8. A chip detection device, characterized in that, The device includes: The acquisition module is used to acquire the raw analog data of the chip under test; The processing module is used to run a target test chip based on the original simulation data. The target test chip is a chip obtained by simulating the current version of the chip under test using a programmable integrated circuit chip. The current version is a version after version iteration. The processing module is also used to collect operating indicators during the operation of the target test chip, and determine the test result of the chip under test based on the operating indicators.

9. An electronic device, characterized in that, include: Memory containing executable program code; and the processor coupled to the memory; The processor calls the executable program code stored in the memory to execute the chip detection method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, include: The computer-readable storage medium stores computer instructions that, when executed by a processor, implement the chip detection method as described in any one of claims 1 to 7.

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