Electronic reconnaissance software radio platform based on RFSoC and use method

Abstract

The invention provides an electronic reconnaissance software radio platform based on an RFSoC and a use method, and the platform comprises a power supply module which achieves the protection of an input power supply, the conversion of power supply voltage, and the power-on time sequence control of each power rail; the clock integration module is used for providing a sampling clock and a clock required by signal processing, and has a clock synchronization function in the single boards and between the single boards; the digital signal processing module is used for processing the digital baseband signal, realizing various signal processing algorithms and being provided with a high-capacity cache; the radio frequency signal receiving and transmitting module is used for sampling the analog radio frequency signal, converting the analog radio frequency signal into a digital baseband signal, and outputting the processed data to the peripheral interface module; and the peripheral interface module is used for realizing data transmission with peripheral equipment and debugging and controlling functions on the platform. All the modules are integrated on a board card. The system has the advantages that the system is highly integrated and convenient to deploy; functions are complete, and hardware design is perfect; computing power is sufficient, and deployment is flexible; and heterogeneous cooperation and full-link processing are realized.

Description

Technical Field

[0001] This application belongs to the field of electronic reconnaissance and signal processing technology, specifically relating to an electronic reconnaissance software radio platform based on RFSoC and its usage method. Background Technology

[0002] Electronic reconnaissance, as a crucial technical means for modern radio management and spectrum resource utilization, has wide-ranging applications in spectrum regulation, communication testing, electromagnetic compatibility detection, and radio interference investigation. By receiving, identifying, locating, and analyzing various radio frequency signals in the electromagnetic environment, electronic reconnaissance systems can promptly grasp spectrum usage and signal characteristic parameters, providing technical support for spectrum planning, communication quality assessment, and electromagnetic environment governance. With the rapid development of wireless communication technology and the increasing congestion of the electromagnetic spectrum, modern radio frequency monitoring faces challenges such as diverse signal systems, wide frequency bands, and complex modulation methods, placing higher demands on the performance of monitoring and receiving platforms.

[0003] Radio frequency (RF) signal reception is the first step in a monitoring system, and its performance directly determines the quality of subsequent signal processing and information extraction. The receiver needs to possess characteristics such as wide bandwidth coverage, high sensitivity, and a large dynamic range to accurately capture target signals in complex electromagnetic environments. Simultaneously, the received analog RF signal must undergo high-speed, high-precision analog-to-digital conversion to form a digital baseband signal for subsequent processing. Therefore, the tight integration and efficient collaboration between the RF front-end and the digital processing unit are crucial for building a high-performance electronic reconnaissance platform.

[0004] The digital signal processing stage after signal reception is equally crucial, directly impacting the accuracy and real-time performance of information extraction. Modern electronic reconnaissance requires a series of processes on received complex signals, including parameter estimation, frequency domain analysis, time-frequency feature extraction, and modulation scheme adjustments. This inevitably involves a large number of computationally intensive tasks such as Fast Fourier Transform (FFT), digital filtering, and matrix operations. These algorithms not only place high demands on the processor's computing power but also require ample data cache space to store intermediate results and historical data, posing a severe challenge to the hardware platform's parallel processing capabilities, storage bandwidth, and algorithm deployment flexibility. Therefore, electronic reconnaissance platforms must not only possess high-performance radio frequency sampling capabilities but also integrate powerful programmable digital processing resources to support the real-time implementation of complex algorithms.

[0005] However, traditional electronic reconnaissance receiving platforms still face numerous technical challenges in practical applications. These challenges primarily manifest in several areas: low system integration leading to size and power consumption issues; insufficient clock synchronization accuracy affecting multi-channel collaborative measurements; limited sampling rate and processing bandwidth preventing coverage of wide-band signals; single data transmission interface with insufficient bandwidth; lack of flexible independent operation and distributed deployment capabilities; and limited logic resources and storage capacity of Field Programmable Gate Arrays (FPGAs) restricting the implementation of complex algorithms. These problems gradually render traditional platforms unable to meet the demands of broadband real-time reception and processing, as well as high-capacity data transmission.

[0006] Therefore, it is necessary to develop an electronic reconnaissance software radio platform to overcome the shortcomings of existing technologies in terms of system integration, processing bandwidth, interface expansion, deployment flexibility, and algorithm hardware support, and to meet the actual needs of modern electronic reconnaissance applications. Summary of the Invention

[0007] The purpose of this application is to overcome the limitations of electronic reconnaissance software radio platforms in complex environments.

[0008] To achieve the above objectives, this application proposes an electronic reconnaissance software radio platform based on RFSoC, comprising a power supply module, a clock synthesis module, a digital signal processing module, an RF signal transceiver module, and a peripheral interface module integrated on a single board; wherein, The power supply module is used to realize platform input power protection, power supply voltage conversion and power-on sequence control of each power rail; The clock integration module is used to provide the platform with the sampling clock and the clock required for signal processing, and has clock synchronization functions within and between single boards; The digital signal processing module is used to process digital baseband signals, implement various signal processing algorithms, and is equipped with a large-capacity cache for data storage and algorithm operation; The radio frequency signal transceiver module is used to convert the analog radio frequency signal from the external antenna of the platform into a digital baseband signal after AD sampling, so that the digital signal processing module can process it and output the processed data to the peripheral interface module. The peripheral interface module is used to realize data transmission between the platform and external devices, as well as external debugging and control functions of the platform.

[0009] As an improvement to the aforementioned platform, the power supply module includes a power input protection circuit and a power conversion circuit; wherein, The power input protection circuit adopts voltage clamping and polarity protection design to limit the input power voltage within the set safe range and provides input reverse connection protection function; The power conversion circuit includes multiple DC / DC converter chips to convert the input power into multiple voltages to power the digital logic section of the platform and peripheral circuits; it also includes multiple low-dropout linear regulator converters to convert the input power into multiple low-noise voltages to provide low-noise power to the clock synthesis module and the RF signal transceiver module; and it also includes power-on timing control logic to output each voltage in sequence according to the timing relationship required by the digital signal processing module.

[0010] As an improvement to the aforementioned platform, the digital signal processing module includes a radio frequency data converter, an FPGA programmable logic, and a multi-core ARM processor; The FPGA programmable logic is used to implement various signal processing algorithms, including: Fast Fourier Transform (FFT) is used for frequency domain analysis of signals. FIR / IIR digital filters are used for signal filtering and channel selection; Modulation identification algorithms are used to identify the modulation scheme of received signals; and Parameter estimation algorithms are used to extract characteristic parameters of a signal, including carrier frequency, bandwidth, and symbol rate. The FPGA programmable logic is connected to an external memory via an AXI high-speed bus; the external memory is used to provide cache space for algorithm execution. The multi-core ARM processor is used to run the Linux operating system.

[0011] As an improvement to the aforementioned platform, the peripheral interface module includes a platform debugging interface, a gigabit Ethernet interface, a high-speed fiber optic interface, and a high-speed USB interface; wherein, The platform's debugging interface includes a TTL level serial port and a JTAG interface; wherein... The TTL serial port is used for outputting platform system logs, monitoring operating status, and inputting control commands. The JTAG interface is used for loading programs and online debugging of ARM processors, as well as for loading bitstream files and debugging logic of FPGA programmable logic. The gigabit Ethernet interface is used to access Ethernet and also to connect to the platform control host computer. The high-speed fiber optic interface is used to transmit the raw data collected by the platform to an external host computer in real time for storage and analysis, and is also used for high-speed data exchange between multiple boards. The high-speed USB interface is used to connect to external devices, enabling one-wire connection for data transmission, platform power supply, and control and monitoring functions.

[0012] This application also provides a method for using an RFSoC-based electronic reconnaissance software radio platform, implemented based on the aforementioned platform. The method includes: a distributed heterogeneous processing mode and an independent heterogeneous processing mode; wherein... The distributed heterogeneous processing mode is as follows: the platform works in cooperation with an external host computer. The platform is responsible for receiving, sampling and preliminary processing of radio frequency signals. The data is transmitted to the host computer through a high-speed fiber optic interface or a high-speed USB interface. The host computer then completes more complex signal processing and information extraction tasks, thereby realizing distributed heterogeneous processing of radar signals, communication signals, etc. The independent heterogeneous processing mode is as follows: the platform uses the computing power provided by its integrated multi-core ARM processor and FPGA programmable logic to complete the tasks of signal reception, processing and information output completely independently.

[0013] Compared with existing technologies, the advantages of this application are: 1. Highly integrated and easy to deploy. This invention is based on Radio Frequency System-on-Chip (RFSoC) technology, integrating high-speed analog-to-digital / digital-to-analog converters (A / D converters), FPGA programmable logic, multi-core ARM processors, DDR4 memory, power supply circuits, clock synthesis circuits, and various peripheral interfaces into a compact hardware platform. By optimizing the overall circuit design and system architecture, it achieves Gsps-level sampling rates and GHz-level signal bandwidth processing capabilities, while significantly reducing system size, power consumption, and design complexity. The entire platform hardware size is only 150mm × 100mm, offering excellent portability and deployment flexibility.

[0014] 2. Comprehensive Functionality and Robust Hardware Design. The electronic reconnaissance platform built on RFSoC enables full-process functionality, including RF signal reception, digital processing, and algorithm deployment, within a compact hardware size. The platform is equipped with a robust power management mechanism, including input protection and power-on timing control, effectively improving system reliability. It employs a high-precision clock module, supporting on-board and inter-board clock synchronization to meet the stringent clock consistency requirements of multi-channel collaborative processing. It provides diverse peripheral interfaces such as Gigabit Ethernet, high-speed fiber optic (up to 100Gbps), and high-speed USB / Thunderbolt3 (up to 20Gbps), meeting the demands of high-bandwidth, high-capacity data transmission. These designs effectively address the shortcomings of existing platforms in power reliability, clock synchronization, and interface expansion, providing highly reliable, wide-bandwidth, and high-capacity hardware support for electronic reconnaissance applications.

[0015] 3. Ample computing power and flexible deployment. This invention's platform integrates a multi-core ARM processor and FPGA programmable logic, providing ample computing resources and a heterogeneous design hardware foundation for algorithm deployment. The FPGA is equipped with up to 2GB of DDR4 cache, providing sufficient data caching space for signal processing algorithms such as Fast Fourier Transform, digital filtering, modulation recognition, and parameter estimation. Because the ARM processor and FPGA programmable logic coexist, appropriate processing units can be flexibly selected for deployment based on the algorithm's characteristics, fully leveraging the advantages of heterogeneous computing. In terms of application modes, the platform can either cooperate with a host computer to achieve distributed heterogeneous processing, or it can operate independently and perform signal processing using its own processing capabilities, meeting the deployment needs of different application scenarios.

[0016] 4. Heterogeneous Collaboration, End-to-End Processing. Based on the platform's hardware architecture characteristics, this invention proposes a heterogeneous collaborative software algorithm deployment scheme and a complete signal processing flow for FPGA and ARM processors. This encompasses RF signal reception and digitization, FPGA real-time signal processing and parameter extraction, ARM high-level algorithm processing and result analysis, and multi-interface data output, achieving end-to-end processing capabilities from antenna reception to result output. This scheme fully leverages the heterogeneous computing advantages of FPGA real-time parallel processing and ARM's flexible control, achieving real-time performance and accuracy in radar signal reconnaissance processing, and providing an efficient hardware solution and software deployment scheme for electronic reconnaissance applications. Attached Figure Description

[0017] Figure 1 The diagram shown is an overall hardware block diagram of an electronic reconnaissance software radio platform based on RFSoC. Figure 2 The diagram shown is a schematic of the PCB layout. Detailed Implementation

[0018] The technical solution of this application will be described in detail below with reference to the accompanying drawings.

[0019] This invention proposes an electronic reconnaissance software radio platform based on RFSoC. The platform has high system integration, broadband real-time processing capabilities, diverse data transmission interfaces, and flexible deployment and operation modes to meet the comprehensive requirements of modern electronic reconnaissance applications for high performance, miniaturization, and easy deployment.

[0020] The RFSoC-based electronic reconnaissance software radio platform includes a power supply module, a clock integration module, a digital signal processing module, an RF signal transceiver module, and a peripheral interface module.

[0021] The power supply module is used to protect the platform's input power, convert the power supply voltage, and control the power-on sequence of each power rail. This module protects the platform from damage caused by abnormal external power input through power input protection and power conversion circuits, provides the required operating voltage to each hardware chip, and controls the output sequence of each voltage to ensure safe and stable system startup.

[0022] The clock integration module provides the platform with sampling clocks and clocks required for signal processing, and enables clock synchronization within and between individual boards. This module can dynamically configure the clock output frequency, supports synchronization with external clock references, and meets the clock consistency requirements of multi-channel collaborative processing.

[0023] The digital signal processing module is the core module of the platform. It is mainly used to process the digital baseband signals received by the radio frequency signal transceiver module, including signal processing algorithms such as parameter estimation, fast Fourier transform, digital filtering, and modulation recognition. It is also equipped with a large-capacity cache for data storage and algorithm operation.

[0024] The radio frequency (RF) signal transceiver module is used to receive and transmit RF signals. This module converts the analog RF signal from the external antenna of the platform into a digital baseband signal after AD sampling for processing by the digital signal processing module.

[0025] The peripheral interface module includes a platform debugging interface, a gigabit Ethernet interface, a high-speed fiber optic interface, and a high-speed USB interface, which are used to realize data transmission between the platform and external devices, as well as external debugging and control functions of the platform.

[0026] The platform debugging interface is used to enable software debugging and operational monitoring of the platform.

[0027] The gigabit Ethernet interface is used to connect to the platform control host computer to realize the control of the platform and the monitoring of its health status, and supports real-time parameter configuration and status query.

[0028] The high-speed fiber optic interface enables data transmission bandwidth of up to 100Gbps, which is used to transmit platform-collected data to an external host computer at high speed.

[0029] The high-speed USB interface allows the platform to connect to a host computer via a single USB cable, enabling data transmission, platform control, and monitoring functions, thus improving the platform's flexibility and portability. This interface is compatible with USB 2.0, USB 3.0, and Thunderbolt 3 protocols, with a maximum data transmission bandwidth of 20Gbps.

[0030] Example 1 like Figure 1As shown, the RFSoC-based electronic reconnaissance software radio platform provided in this embodiment consists of a power supply module, a clock integration module, a digital signal processing module, an RF signal transceiver module, and a peripheral interface module.

[0031] 1. Power supply module The power supply module includes a power input protection circuit and a power conversion circuit.

[0032] The power input protection circuit employs voltage clamping and polarity protection design, limiting the input power supply voltage to a safe range of 5-12V and providing reverse connection protection. When the input power supply voltage exceeds the normal operating range or the positive and negative terminals of the input power supply are reversed, the power input protection circuit can promptly cut off the power supply, effectively protecting the internal components of the platform from damage and improving the system's reliability in complex power supply environments.

[0033] The power conversion circuit uses multiple DC / DC converter chips to efficiently convert the input power into multiple voltages, including 0.85V, 1.8V, 3.3V, and 5V, to power the digital logic section of the RFSoC platform and peripheral circuits. Multiple low-dropout linear regulators (LDOs) are used to convert the input power into low-noise voltages, such as 0.9V, 2.5V, and 3.3V, specifically providing low-noise power to the platform's clock synthesis module and RF transceiver module, ensuring their low-noise characteristics. The power conversion circuit also integrates power-on timing control logic, outputting each voltage sequentially according to the timing requirements of the RFSoC chip, preventing chip damage or malfunctions due to incorrect power-on sequence.

[0034] 2. Clock Integration Module The clock synthesis module can be implemented using TI's LMK04832 high-performance multi-channel clock synthesizer chip. This chip uses the platform's onboard 100MHz temperature-compensated crystal oscillator (TCXO) as the reference clock source and synthesizes multiple clock signals of different frequencies through an internal phase-locked loop (PLL) circuit.

[0035] Specifically, the clock synthesis module outputs include: a sampling clock for the AD / DA converter, an operation clock for the digital signal processing module, and other system auxiliary clocks. The ARM processor in the digital signal processing module can configure the registers of the LMK04832 chip via the SPI serial bus interface to dynamically adjust the clock output frequency to adapt to different sampling rates and processing bandwidth requirements. Furthermore, this module provides an external clock input interface, which can synchronize each output clock with an externally input reference clock, achieving clock synchronization between multiple boards and meeting the stringent clock consistency requirements of distributed multi-channel signal processing systems.

[0036] 3. Digital Signal Processing Module The digital signal processing module is the core of the platform and can be implemented using Xilinx's XCZU27DR RFSoC chip. This module features an RF data converter, FPGA programmable logic, and a multi-core ARM processor, enabling a high degree of integration between RF sampling and digital processing.

[0037] The XCZU27DR RFSoC chip integrates multiple high-speed AD / DA converters, with the AD converters achieving a sampling rate of up to 4.096 Gsps, supporting direct sampling of wideband RF signals. The chip's internal multi-core ARM Cortex-A53 processor runs a streamlined embedded Linux operating system, responsible for the platform's system management, control, and scheduling functions, including configuring the clock synthesis module, setting sampling parameters, and running signal processing algorithms.

[0038] The FPGA programmable logic section inside the chip is responsible for implementing various signal processing algorithms, including but not limited to: Fast Fourier Transform (FFT) for frequency domain analysis of signals, FIR / IIR digital filters for signal filtering and channel selection, modulation identification algorithms for identifying the modulation scheme of received signals, and parameter estimation algorithms for extracting characteristic parameters such as carrier frequency, bandwidth, and symbol rate of signals. Depending on specific application requirements, more complex algorithms such as signal sorting, target detection, and individual recognition can also be deployed in the FPGA. Simultaneously, the FPGA is connected to an external 2GB DDR4 SDRAM memory via an AXI high-speed bus. This memory provides ample data cache space for algorithm implementation, supporting temporary storage, processing, and readback operations of large amounts of data. This cache enables the platform to handle signal processing algorithms that require large amounts of historical data.

[0039] 4. Radio frequency signal transceiver module The RF transceiver module converts RF analog signals to digital baseband signals. This module uses an RF balun transformer as an impedance matching device to convert the single-ended antenna RF signal into a differential signal, achieving impedance matching and signal coupling with the AD / DA transceiver inside the RFSoC chip. The RF analog signal from the external antenna, after passing through the balun transformer, is directly input to the high-speed AD converter inside the RFSoC chip for sampling, converting it into a digital baseband signal for subsequent processing by the FPGA programmable logic.

[0040] 5. Peripheral interface module The peripheral interface module includes a platform debugging interface, a gigabit Ethernet interface, a high-speed fiber optic interface, and a high-speed USB interface.

[0041] 1) Platform debugging interface The platform's debugging interfaces include a TTL level serial port and a JTAG interface.

[0042] The TTL serial port is brought out from the System Processor (PS) pin of the RFSoC chip and, after level conversion, is connected to the platform's debug interface connector. This serial port is used for outputting platform system logs, monitoring operating status, and inputting control commands.

[0043] The JTAG interface connects to the JTAG debug port of the RFSoC chip, which can be used for program loading and online debugging of the ARM processor in the PS section, as well as for bitstream file loading and logic debugging of the FPGA in the PL section, providing complete debugging support for the platform's software and hardware development.

[0044] 2) Gigabit Ethernet interface The Gigabit Ethernet interface can use the RTL8211F Gigabit Ethernet Phy chip for the PS-side Ethernet access function of the RFSoC chip, which can be used to connect to the host computer for platform control.

[0045] The Gigabit Ethernet interface can be implemented using Realtek's RTL8211F Gigabit Ethernet Physical Layer (PHY) chip. This chip connects to the Gigabit Ethernet MAC controller on the PS side of the RFSoC chip via the RGMII interface to achieve Gigabit Ethernet communication functionality. This interface is mainly used to connect to the platform control host computer, enabling remote control, parameter configuration, status query, and health monitoring of the platform via the TCP / IP protocol.

[0046] 3) High-speed fiber optic interface High-speed fiber optic interfaces can be implemented using the high-speed GTY transceiver integrated on the PL side of the RFSoC chip. The GTY transceiver supports a single-channel transmission rate of up to 32.75Gbps and can be routed through PCB traces to the platform's QSFP28 (Quad SmallForm-factor Pluggable 28) optical module connector.

[0047] The QSFP28 connector supports the connection of various fiber optic modules, with a total bandwidth of up to 100Gbps. This interface is compatible with the Xilinx Aurora high-speed point-to-point communication protocol and the 100G Ethernet protocol, and can be flexibly configured according to application requirements. The high-speed fiber optic interface is primarily used to transmit raw data collected by the platform to an external host computer in real time for storage and analysis, and can also be used for high-speed data exchange between multiple boards.

[0048] 4) High-speed USB interface The USB interface uses a Type-C physical connector and is compatible with USB 2.0, USB 3.0, and Thunderbolt 3.0 protocol standards, providing a data transfer bandwidth of up to 20Gbps. This interface allows the platform to connect directly to laptops or desktops via a single Type-C cable, enabling a one-wire connection for data transfer, platform power supply, control, and monitoring, greatly improving the platform's portability and ease of use.

[0049] Example 2 The platform of this invention supports multiple usage modes, which can be flexibly selected according to actual application needs.

[0050] In the distributed heterogeneous processing mode, the platform works in conjunction with an external host computer. The platform is responsible for receiving, sampling, and initially processing radio frequency signals, and transmits the data to the host computer via a high-speed fiber optic interface or a high-speed USB interface. The host computer then performs more complex signal processing and information extraction tasks, enabling distributed heterogeneous processing of radar signals, communication signals, and other data. This mode fully utilizes the powerful computing capabilities and storage capacity of the host computer, making it suitable for applications requiring offline analysis of large datasets.

[0051] In standalone heterogeneous processing mode, the platform leverages the computing power provided by the multi-core ARM processor and FPGA programmable logic integrated within the RFSoC chip to independently complete signal reception, processing, and information output tasks without the need for external host computer support. In this mode, the signal processing algorithm is deployed locally on the platform for hardware acceleration, and the processing results are output via a gigabit Ethernet interface. Standalone operation mode is suitable for applications requiring low latency and high real-time performance, as well as portable or embedded applications that cannot be equipped with a host computer.

[0052] The hardware size of the platform of this invention is only 150mm×100mm. It has a compact overall structure, light weight, low power consumption, and features high miniaturization and flexible use. It is easy to integrate into various electronic reconnaissance equipment and is also suitable as a general software radio platform for various application fields such as wireless communication, spectrum monitoring, and radar signal processing.

[0053] Example 3 The following uses radar signal reconnaissance processing as an example to illustrate the algorithm deployment scheme and signal processing flow of the platform of this invention, such as... Figure 2 The diagram shown is a corresponding illustration.

[0054] After the radio frequency (RF) signal emitted by the radar radiation source is received by the platform's external antenna, it undergoes impedance matching and differential conversion via the balun converter in the RF signal transceiver module. It is then input to the high-speed AD converter integrated within the RFSoC chip for direct sampling. The AD converter converts the analog RF signal into a digital baseband signal or a digital intermediate frequency (IF) signal, with the sampling rate adjustable from several hundred Msps to 4.096 Gsps depending on the target radar signal bandwidth.

[0055] The digitized signal is first processed in the FPGA programmable logic. The FPGA sequentially performs digital down-conversion, FIR digital filtering, Fast Fourier Transform (FFT) spectrum analysis, Constant False Alarm Rate (CFAR) signal detection, and pulse parameter measurement, extracting basic pulse descriptor parameters such as the time of arrival (TOA), pulse width (PW), carrier frequency (RF), and pulse amplitude (PA) of the radar pulse. These algorithms are deployed in the FPGA because they require real-time parallel processing of high-speed data streams. The FPGA's pipeline structure and parallel computing capabilities can meet the real-time processing requirements at high sampling rates, ensuring no radar pulse signal is lost. Intermediate data during processing is stored in a 2GB DDR4 cache mounted on the FPGA, providing support for large-capacity data caching and algorithm computation.

[0056] The pulse descriptor parameters and digital signals extracted by the FPGA are transferred to the memory space of the ARM multi-core processor via the AXI high-speed on-chip interconnect bus inside the RFSoC chip using DMA. After receiving the pulse descriptor and digital pulse signals, the ARM processor executes subsequent algorithms for radar signal sorting, pulse signal modulation identification, radiation source localization, and individual radiation source identification. Specifically, the ARM processor first uses a multi-parameter correlation sorting algorithm based on the pulse descriptor parameters (TOA, PW, RF, PA, etc.) to cluster and separate pulse sequences belonging to the same radar radiation source; then, it identifies the intra-pulse modulation type of the sorted pulse sequences, determining whether it is a conventional pulse, linear frequency modulation, phase coding, or frequency coding modulation; furthermore, it uses multi-channel or multi-platform data to perform spatial localization calculations for the radiation source; finally, it extracts unintentional modulation features of the radiation source for individual identification. These algorithms are deployed on the ARM processor because they involve complex serial processing processes such as parameter correlation, pattern recognition, decision-making, and iterative optimization, requiring flexible control flow and rich mathematical library support. The Linux operating system running on the ARM processor can easily call various algorithm libraries and machine learning libraries, making it suitable for implementing complex high-level signal processing algorithms.

[0057] The processed radar signal parameters, sorting results, identification results, and positioning information are output to external devices through the peripheral interface module. For real-time monitoring and control needs, the processing results are transmitted to the host computer via a gigabit Ethernet interface; for applications requiring the transmission of raw sampled data or large batch processing results, a high-speed fiber optic interface can be used to achieve data transmission with a bandwidth of up to 100Gbps; for portable field applications, a laptop can be connected via a high-speed USB interface using a single Type-C cable to achieve data transmission and platform control.

[0058] The processed radar signal parameters, sorting results, identification results, and positioning information are output to external devices through different transmission paths, depending on the data volume and real-time requirements. When real-time requirements are low and the data volume is small, the processing results can be directly transmitted to the host computer via the gigabit Ethernet interface controlled by the ARM processor. For raw sampling data or large-scale processing results requiring high-speed transmission, the ARM processor sends the data back to the FPGA via the AXI bus, and the FPGA then outputs the data through its connected high-speed fiber optic interface or high-speed USB interface. This fully utilizes the high bandwidth transmission capabilities of these interfaces to achieve a maximum data throughput of 100Gbps (fiber optic interface) or 20Gbps (USB interface), meeting the high-speed transmission needs of massive amounts of data.

[0059] This algorithm deployment scheme fully leverages the advantages of FPGA in high-speed parallel processing and the flexibility of ARM processor in complex algorithm implementation, achieving real-time performance and accuracy in radar signal reconnaissance processing, and providing an efficient hardware solution for electronic reconnaissance applications.

[0060] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application do not depart from the spirit and scope of the technical solutions of this application, and should all be covered within the scope of the claims of this application.

Claims

1. An electronic reconnaissance software radio platform based on RFSoC, characterized in that, This includes a power supply module, a clock integration module, a digital signal processing module, an RF transceiver module, and a peripheral interface module integrated on a single board; among which, The power supply module is used to realize platform input power protection, power supply voltage conversion and power-on sequence control of each power rail; The clock integration module is used to provide the platform with the sampling clock and the clock required for signal processing, and has clock synchronization functions within and between single boards. The digital signal processing module is used to process digital baseband signals, implement various signal processing algorithms, and is equipped with a large-capacity cache for data storage and algorithm operation. The radio frequency signal transceiver module is used to convert the analog radio frequency signal from the external antenna of the platform into a digital baseband signal after AD sampling for processing by the digital signal processing module, and output the processed data to the peripheral interface module. The peripheral interface module is used to realize data transmission between the platform and external devices, as well as external debugging and control functions of the platform.

2. The RFSoC-based electronic reconnaissance software radio platform according to claim 1, characterized in that, The power supply module includes a power input protection circuit and a power conversion circuit; wherein... The power input protection circuit adopts voltage clamping and polarity protection design to limit the input power voltage within the set safe range and provides input reverse connection protection function; The power conversion circuit includes multiple DC / DC converter chips to convert the input power into multiple voltages to power the digital logic section of the platform and peripheral circuits; it also includes multiple low-dropout linear regulator converters to convert the input power into multiple low-noise voltages to provide low-noise power to the clock synthesis module and the RF signal transceiver module; and it also includes power-on timing control logic to output each voltage in sequence according to the timing relationship required by the digital signal processing module.

3. The RFSoC-based electronic reconnaissance software radio platform according to claim 1, characterized in that, The digital signal processing module includes a radio frequency data converter, an FPGA programmable logic, and a multi-core ARM processor; The FPGA programmable logic is used to implement various signal processing algorithms, including: Fast Fourier Transform (FFT) is used for frequency domain analysis of signals. FIR / IIR digital filters are used for signal filtering and channel selection; Modulation identification algorithms are used to identify the modulation scheme of received signals; and Parameter estimation algorithms are used to extract characteristic parameters of a signal, including carrier frequency, bandwidth, and symbol rate. The FPGA programmable logic is connected to an external memory via an AXI high-speed bus; the external memory is used to provide cache space for algorithm execution. The multi-core ARM processor is used to run the Linux operating system.

4. The RFSoC-based electronic reconnaissance software radio platform according to claim 3, characterized in that, The peripheral interface module includes a platform debugging interface, a gigabit Ethernet interface, a high-speed fiber optic interface, and a high-speed USB interface; among which... The platform's debugging interface includes a TTL level serial port and a JTAG interface; wherein... The TTL serial port is used for outputting platform system logs, monitoring operating status, and inputting control commands. The JTAG interface is used for loading programs and online debugging of ARM processors, as well as for loading bitstream files and debugging logic of FPGA programmable logic. The gigabit Ethernet interface is used to access Ethernet and also to connect to the platform control host computer. The high-speed fiber optic interface is used to transmit the raw data collected by the platform to an external host computer in real time for storage and analysis, and is also used for high-speed data exchange between multiple boards. The high-speed USB interface is used to connect to external devices, enabling one-wire connection for data transmission, platform power supply, and control and monitoring functions.

5. A method of using an RFSoC-based electronic reconnaissance software radio platform, implemented based on any one of the platforms described in claims 1-4, the method comprising: Distributed heterogeneous processing mode and independent heterogeneous processing mode; among them... The distributed heterogeneous processing mode is as follows: the platform works in cooperation with an external host computer. The platform is responsible for receiving, sampling and preliminary processing of radio frequency signals. The data is transmitted to the host computer through a high-speed fiber optic interface or a high-speed USB interface. The host computer then completes more complex signal processing and information extraction tasks, thereby realizing distributed heterogeneous processing of radar signals, communication signals, etc. The independent heterogeneous processing mode is as follows: the platform uses the computing power provided by its integrated multi-core ARM processor and FPGA programmable logic to complete the tasks of signal reception, processing and information output completely independently.

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