SRAM (Static Random Access Memory) test structure
By modifying the connection path of the SRAM test structure, the leakage current contributed by parasitic transistors is eliminated, solving the inaccuracy problem of the contribution path in the gate tunneling leakage current test, and realizing accurate monitoring and optimization of the static power consumption of SRAM bits.
Patent Information
- Application Number
- CN202411630123.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-14
- Publication Date
- 2026-05-19
AI Technical Summary
Existing technologies cannot accurately determine the contribution path of gate tunneling leakage current in the static power consumption of SRAM bits, making it difficult to optimize device performance and reliability.
By modifying the connection path of the SRAM test structure, the leakage current contributed by parasitic transistors is eliminated. Smaller contact plugs are used to connect the gate of the pull-down transistor to the metal line and to the test pad through conductive vias, thus eliminating the influence of leakage current from parasitic transistors.
Accurate monitoring of the static power consumption of MOSFETs in SRAM bits provides a clear path for leakage current contribution, offering direction for subsequent process optimization and improving device performance and reliability.
Smart Images
Figure CN122069703A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device testing technology, and in particular to an SRAM testing structure. Background Technology
[0002] Static Random-Access Memory (SRAM) can retain its internally stored data without requiring a refresh circuit, making it a commonly used high-speed cache. The static power consumption (Istandby) of SRAM mainly includes gate-tunnel leakage current (Iginv), gate-induced drain leakage current (GIDL), and subthreshold leakage current. Gate-tunnel leakage current (Iginv) is formed by the charge on the gate tunneling through the gate oxide layer into the substrate. As device dimensions continue to shrink, the gate oxide layer thickness also decreases, leading to a rapid increase in gate-tunnel leakage current, thus affecting the device's static power consumption, reliability, and operating performance.
[0003] Currently, in the SRAM development process, the gate tunneling leakage current Iginv of the MOSFETs in an SRAM bitcell is generally monitored using the testkey of the Wafer Acceptance Test (WAT). However, when measuring abnormal gate tunneling leakage currents of the pull-up transistors (PU) and pull-down transistors (PD) in the testkey, it is currently impossible to accurately determine the static power consumption of the SRAM bit itself, making it difficult to find the leakage current contribution path in the SRAM's static power consumption. Summary of the Invention
[0004] The purpose of this invention is to provide an SRAM test structure that can eliminate the leakage current contributed by parasitic transistors on the corresponding connection path, thereby making the gate tunneling leakage current test results accurate.
[0005] To achieve the above objectives, the present invention provides an SRAM test structure, which includes at least one first test unit formed on a substrate and to be connected to a test pad. The first test unit includes a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, and a second pull-down transistor formed on the substrate with their active regions spaced apart from each other.
[0006] The first pull-up transistor and the first pull-down transistor share a first gate;
[0007] The second pull-up transistor and the second pull-down transistor share a second gate;
[0008] In this test unit, the first gate is connected to the first metal line via a contact plug with a size no larger than a standard contact plug. The first metal line is connected to the second metal line via a corresponding conductive via. The second metal line is connected to the corresponding test pad.
[0009] Optionally, the first test unit further includes a first transmission transistor, a second transmission transistor, a third transmission transistor, and a fourth transmission transistor formed in the substrate with their active regions spaced apart from each other; wherein the active regions of the first transmission transistor and the first pull-down transistor are integrated, and the active regions of the fourth transmission transistor and the second pull-down transistor are integrated; the source of the first transmission transistor, the drain of the first pull-up transistor, the drain of the first pull-down transistor, and the second gate of the first test unit are electrically connected through corresponding standard contact plugs and corresponding first metal lines; the source of the third transmission transistor, the source of the fourth transmission transistor, the drain of the second pull-up transistor, and the drain of the second pull-down transistor are electrically connected through corresponding standard contact plugs and corresponding first metal lines.
[0010] Optionally, the second transmission transistor and the fourth transmission transistor share the same word line gate, and the first transmission transistor and the third transmission transistor share the same word line gate.
[0011] Optionally, the source of the second transmission transistor is also electrically connected to the second gate via a shared contact plug, the shared contact plug being larger than the standard contact plug.
[0012] Optionally, the first pull-up transistor and the first pull-down transistor are connected to form an inverter, and the second pull-up transistor and the second pull-down transistor are connected to form another inverter.
[0013] Optionally, the drain of the first pull-down transistor is connected to the first metal line via a corresponding standard contact plug, and further connected to the second metal line via a corresponding conductive via, to connect to the corresponding test pad; and / or, the drain of the first pull-up transistor is connected to the first metal line via a corresponding standard contact plug, and further connected to the second metal line via a corresponding conductive via, to connect to the corresponding test pad.
[0014] Optionally, the SRAM test structure further includes at least one second test unit formed on the substrate and not connected to the test pad. The second test unit includes a first to a fourth transfer transistor, a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, and a second pull-down transistor. The first pull-up transistor and the first pull-down transistor in the second test unit share another first gate. The second pull-up transistor and the second pull-down transistor in the second test unit share another second gate.
[0015] The first gate of the second test unit is connected to the drain of the second pull-up transistor and the source of the third transmission transistor of the second test unit through a corresponding shared contact plug.
[0016] Optionally, the second gate of the second test unit is connected to the drain of the first pull-up transistor and the source of the second transmission transistor of the second test unit through a corresponding shared contact plug.
[0017] Optionally, the active region layout and gate layout of each transistor in the second test unit are the same as those of the transistors in the first test unit.
[0018] Optionally, the first pull-up transistor and the first pull-down transistor in the second test unit are connected to form an inverter, and the second pull-up transistor and the second pull-down transistor in the second test unit are connected to form another inverter, and the two inverters in the second test unit are cross-coupled.
[0019] Compared with the prior art, the technical solution of the present invention, based on the current test structure layout, removes all shared contact plugs on the gate terminals of pull-down transistors (or pull-up transistors) that need to be connected (i.e., connected to test pads), and replaces them with smaller contact plugs. The gate terminal of the pull-down transistor is connected to the first layer of metal lines through the contact plugs, then connected to the second layer of metal lines through vias, and finally connected to the corresponding test pads. This modifies the connection path relative to the current test structure, eliminates the leakage current contributed by parasitic transistors in the current test structure, solves the problem of the source of each leakage current contribution during the test of gate tunneling leakage current Iginv, and thus timely monitors the electrical problems of the MOS transistors in the SRAM bitcell, accurately determines the leakage current contribution path under the static power consumption of the SRAM bitcell, provides a clearer direction for subsequent process optimization of Iginv, and can also provide timely guidance for the optimization of the gate oxide layer process. Attached Figure Description
[0020] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:
[0021] Figure 1 This is a schematic diagram of the existing SRAM bit test structure with metal layers M1 and M2 omitted.
[0022] Figure 2 This is a schematic diagram of the existing SRAM bit test structure with metal layers M1 and M2.
[0023] Figure 3 yes Figure 1 The diagram shows the equivalent circuit diagram of the test structure for the SRAM bits.
[0024] Figure 4 This is a schematic diagram of the SRAM bit test structure according to an embodiment of the present invention with metal layers M1 and M2 omitted.
[0025] Figure 5 This is a schematic diagram of the layout of an SRAM bit test structure with metal layers M1 and M2 according to an embodiment of the present invention.
[0026] Figure 6 yes Figure 4 The diagram shows the equivalent circuit diagram of the test structure for the SRAM bits.
[0027] Figure 7 This is a schematic diagram of the SRAM bit test structure of another embodiment of the present invention with metal layers M1 and M2 omitted.
[0028] Figure 8 This is a schematic diagram of the layout of the SRAM bit test structure with metal layers M1 and M2, according to another embodiment of the present invention.
[0029] Figure 9 This is a schematic diagram of the SRAM bit test structure of another embodiment of the present invention with metal layers M1 and M2 omitted. Detailed Implementation
[0030] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.
[0031] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0032] Please refer to Figures 1 to 3Currently (e.g., at the 40nm node), an SRAM test structure used to test the gate tunneling leakage current Iginv of pull-down transistors (PD) and pull-up transistors (PU) in SRAM bits includes: two pull-down transistors PD1 and PD2, two pull-up transistors PU1 and PU2, and four transfer transistors PG1a, PG1b, PG2a, and PG2b. In this configuration, PD1 and PU1 share the same polysilicon POLY gate G1 (i.e., PD1 and PU1 share a common gate), PD2 and PU2 share the same polysilicon POLY gate G2 (i.e., PD2 and PU2 share a common gate), PG1a and PG2a share the same polysilicon POLY word line gate WLA (i.e., PG1a and PG2a share a common gate), and PG1b and PG2b share the same polysilicon POLY word line gate WLB (i.e., PG1b and PG2b share a common gate). Gate G1 is connected to the first layer metal line M1 via a shared contact plug SCT, then to the second layer metal line M2 via a conductive via V1, and finally to the corresponding test pad (PAD, not shown). Because the shared contact plug SCT connected to gate G1 is also connected to the drain of PU2 and the source of PG2a, a parasitic diode exists at the drain of PU2 (i.e., the source of PG2a). This parasitic diode causes abnormal leakage current in Iginv during the Iginv test. The other components in this SRAM test structure that need to be electrically led upwards can be electrically led upwards through the corresponding standard contact plugs (CTs) set on their tops. This is common knowledge in the field and will not be described in detail here.
[0033] In this SRAM test structure, the standard contact plug (CT) is a contact plug manufactured using a standard-sized contact hole. It typically overlaps with one component (e.g., gate, source, or drain) within the SRAM test structure, allowing that component to be electrically led upwards independently. The dimensions of each shared contact plug (SCT) (i.e., the opening area of the shared contact hole containing the shared contact plug SCT) are larger than the standard size. Each shared contact plug SCT will simultaneously overlap with two or more components (e.g., gate and source, or gate and drain) within the SRAM test structure, serving as a shared contact plug for these two or more components, thus allowing them to be electrically led upwards simultaneously.
[0034] Based on this, the present invention, based on the current test structure layout, removes all shared contact plugs on the gate terminals of pull-down transistors (or pull-up transistors) that need to be connected (i.e., connected to the test pads), and replaces them with smaller contact plugs (the contact plugs can be standard contact plugs or small contact plugs smaller than standard contact plugs). The gate terminal of the pull-down transistor is then connected to the first layer of metal lines through the contact plugs, then to the second layer of metal lines through vias, and finally to the test pads. This modifies the connection path, eliminates leakage current contributed by parasitic transistors, solves the problem of the sources of various leakage current contributions during Iginv testing, and provides a clearer direction for subsequent Iginv optimization.
[0035] Please refer to Figures 4 to 6 An embodiment of the present invention provides an SRAM test structure, which includes at least one first test unit formed on a substrate (not shown) and connected to corresponding test pads (not shown). The first test unit includes a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, and a second pull-down transistor PD2 formed on the substrate with their active regions spaced apart from each other.
[0036] The first pull-up transistor PU1 and the first pull-down transistor PD1 share a first gate G1 (which can be made of polysilicon POLY), and the first pull-up transistor PU1 and the first pull-down transistor PD1 are electrically connected through corresponding standard contact plugs CT and first metal lines M1 to form an inverter.
[0037] The second pull-up transistor PU2 and the second pull-down transistor PD2 share a second gate G2 (which can be made of polysilicon POLY), and the second pull-up transistor PU2 and the second pull-down transistor PD2 are electrically connected through corresponding standard contact plugs CT, the first metal line M1, etc., to form another inverter.
[0038] In this embodiment, in the first test unit, its first gate G1 is connected to the first metal line M1 through a contact plug CTa (which can be a standard contact plug or a small contact plug smaller than the standard contact plug) with a size not larger than the standard contact plug CT. The first metal line M1 connected to the top of the contact plug CTa is connected to the second metal line M2 through a corresponding conductive via V1b. The second metal line M2 connected to the top of the conductive via V1b is further connected to the corresponding test pad (PAD, not shown).
[0039] In this embodiment, the active region layouts of the first pull-up transistor PU1 and the second pull-up transistor PU2 are the same, and the active region layouts of the first pull-down transistor PD1 and the second pull-down transistor PD2 are the same.
[0040] Optionally, the first test unit further includes a first transmission transistor PG1a, a second transmission transistor PG1b, a third transmission transistor PG2a, and a fourth transmission transistor PG2b formed in the substrate with their active regions spaced apart from each other. The active regions of the first transmission transistor PG1a and the first pull-down transistor PD1 are integrated, achieving a connection between the source of the first transmission transistor PG1a and the drain of the first pull-down transistor PD1 (i.e., the source of PG1a and the drain of PD1 share the same active region component); the active regions of the fourth transmission transistor PG2b and the second pull-down transistor PD2 are integrated, achieving a connection between the source of the fourth transmission transistor PG2b and the drain of the second pull-down transistor PD2 (i.e., the source of PG2b and the drain of PD2 share the same active region component). The second transmission transistor PG1b and the fourth transmission transistor PG2b share the same word line gate WLB, the first transmission transistor PG1a and the third transmission transistor PG2a share the same word line gate WLA, and the word line gate WLA and the word line gate WLB are respectively connected to the first metal line M1 through corresponding standard contact plugs CT.
[0041] Furthermore, the source of the first transmission transistor PG1a, the drain of the first pull-up transistor PU1, the drain of the first pull-down transistor PD1, and the second gate G2 of the first test unit are electrically connected through corresponding standard contact plugs CT and corresponding first metal lines M1; the source of the third transmission transistor PG2a, the source of the fourth transmission transistor PG2b, the drain of the second pull-up transistor PU2, and the drain of the second pull-down transistor PD2 are electrically connected through corresponding standard contact plugs CTa and corresponding first metal lines M1.
[0042] Optionally, the source of the second transmission transistor PG1b is also electrically connected to the second gate G2 via a shared contact plug SCT, which is larger than the standard contact plug CT. That is, the source of the second transmission transistor PG1b and the second gate G2 share the same contact plug (i.e., a shared contact plug SCT) and are electrically connected to the corresponding first metal line M1 through the shared contact plug SCT.
[0043] contrast Figure 1 and Figure 4 It can be seen that the test structure in this embodiment differs from the prior art in the following ways:
[0044] (1) In the existing test structure, one end of the first gate G1 (i.e. Figure 1 The lower end of G1 is connected to the source of PG2a via a shared contact plug SCT, and the other end (i.e. Figure 1The upper end of G1 is connected to the drain of PU2 via another shared contact plug. In the test structure of this embodiment, one end of its first gate G1 (i.e....) Figure 4 The lower end of G1 is connected to the source of PG2a via a contact plug CTa, a conductive via V1b (and the first metal wire M1 and the second metal wire M2 connecting CTa and V1b), and the other end (i.e. Figure 4 The shared contact plug is removed from the upper end of G1, and no other standard contact plug is connected to the drain of PU2.
[0045] (2) In the existing test structure, one end of its second gate G2 (i.e. Figure 1 The upper end of G2 is connected to the source of PG1b via a shared contact plug SCT, and the other end (i.e. Figure 1 The lower end of the middle gate G2 is connected to the drain of PU1 via another shared contact plug SCT. In the test structure of this embodiment, one end of its second gate G2 (i.e. Figure 4 The upper end of G2 is connected to the source of PG1b via a shared contact plug SCT, and the other end (i.e. Figure 4 The shared contact plug is removed from the lower end of G2, and no other standard contact plug is connected to the drain of PU1.
[0046] (3) In the existing test structure, the drain region of PD2 is provided with a corresponding conductive via V11, the source region of PD1 is provided with a corresponding conductive via V12, and the area where the drain region of PD1 and the source region of PG1 meet is provided with a corresponding conductive via V13. In the test structure of this embodiment, the drain region of PD1 is provided with a corresponding conductive via V1c to connect M1 through a corresponding standard contact plug CT, and further connected to M2 through the conductive via V1c to connect to the corresponding test pad (e.g., to receive the output signal); the source region of PU1 is provided with a corresponding conductive via V1a to connect M1 through a corresponding standard contact plug CT, and further connected to M2 through the conductive via V1c to connect to the corresponding test pad (e.g., to VDD).
[0047] Please refer to Figure 6 In this embodiment, the drain of PG1a is connected to bit line BL_A, the drain of PG2a is connected to bit line BLB_A, the drain of PG1b is connected to bit line BL_B, the drain of PG2b is connected to bit line BLB_B, the source of PU1 and PU2 is connected to the power supply voltage VDD, and the source of PD1 and PD2 is connected to the low voltage VSS (which can be the system ground).
[0048] The gate tunneling leakage current Iginv of PU1 and PD1 was tested using the existing test structure and the test structure of this embodiment. The test results are shown in the table below:
[0049]
[0050] As can be seen from the table above, in this embodiment, all shared contact plugs on the gate of PD1 (i.e., the first gate G1) that needs to be connected are removed and replaced with contact plugs CTa. These contact plugs CTa can be standard contact plugs or smaller contact plugs (i.e., contact plugs smaller than standard contact plugs). When connected to M1 via CTa, and then to M2 via V1b, and finally connected to the test pad PAD for testing, compared with the test structure of the existing technology, parasitic transistors on the connection path of the gate of PD1, the gate of PU1, and the source of PG2a and the drain of PU2 can be eliminated. This eliminates the leakage current contributed by parasitic transistors in the current test structure, solves the problem of the source of each leakage current contribution during the test of gate tunneling leakage current Iginv, and thus timely monitors the electrical problems of the MOS transistors in the SRAM bitcell, accurately determines the leakage current contribution path under the static power consumption of the SRAM bitcell, and provides a clearer direction for subsequent process optimization of Iginv.
[0051] It should be understood that in the test structure of this embodiment, the dimensions of each shared contact plug SCT can be the same or different; the dimensions of each standard contact plug CT can be exactly the same or slightly different due to process errors. However, the dimensions of each shared contact plug SCT (the opening area of the shared contact hole it is located in) are all larger than the dimensions of the standard contact plug CT. Each shared contact plug SCT will overlap with two or more components (e.g., gate and source, or gate and drain) and serve as a shared contact plug for these two or more components, so that the two or more components can be electrically led upwards simultaneously. In contrast, each standard contact plug CT will only overlap with one component (e.g., gate, source, or drain) so that the single component can be electrically led upwards alone.
[0052] Figures 4 to 5 The test structure shown is merely an example layout of the test structure of the present invention, and does not imply that the test structure of the present invention only includes the above structure.
[0053] For example, in the SRAM test structure of another embodiment of the present invention, please refer to... Figures 7 to 8 A corresponding conductive via V1d is provided on the drain region of PD2 to connect M1 through a corresponding standard contact plug CT, and further connect to M2 through the conductive via V1d.
[0054] For example, in yet another embodiment of the present invention, please refer to Figure 9The SRAM test structure also includes at least one second test unit 20 formed on the substrate and not connected to a corresponding test pad. The second test unit 20 includes first to fourth transfer transistors (PG1a, PG1b, PG2a, PG2b), a first pull-up transistor (PU1), a second pull-up transistor (PU2), a first pull-down transistor (PD1), and a second pull-down transistor (PD2). In the second test unit 20, the first pull-up transistor (PU1) and the first pull-down transistor (PD1) share another first gate (G1); the second pull-up transistor (PU2) and the second pull-down transistor (PD2) share another second gate (G2). The first pull-up transistor (PU1) and the first pull-down transistor (PD1) form an inverter, and the second pull-up transistor (PU2) and the second pull-down transistor (PD2) form another inverter, with the two inverters cross-coupled.
[0055] In this embodiment, the active region layout and gate layout of each transistor in the second test unit 20 are the same as those of the corresponding transistors in the first test unit 10. Optionally, in adjacent first test units 10 and second test units 20, the active region of PD2 in the first test unit 10 is connected to the active region of PD2 in the second test unit 20, the active region of PU2 in the first test unit 10 is connected to the active region of PU2 in the second test unit 20, the active region of PG1a in the first test unit 10 is connected to the active region of PG1a in the second test unit 20, the active region of PG2a in the first test unit 10 is connected to the active region of PG2a in the second test unit 20, and the active regions of PG1b in the first test unit 10 and PG1b in the second test unit 20 are spaced apart from each other.
[0056] Please refer to Figure 1 and Figure 9 In this embodiment, the layout structure of each transistor and contact plug in the second test unit 20 of the test structure can be compared with... Figure 1 The test structures shown are identical. Specifically, the first gate G1 of the second test unit 20 is connected to the drain of the second pull-up transistor PU2 and the source of the third transmission transistor PG2a via a corresponding shared contact plug SCT. The second gate G2 of the second test unit 20 is connected to the drain of the first pull-up transistor PU1 and the source of the second transmission transistor PG1b via a corresponding shared contact plug SCT. Specifically, in each second test unit 20, one end of its first gate G1 (i.e....) Figure 9 The lower end of G1 in PG2a is connected to the source of PG2a via a shared contact plug SCT, and the other end (i.e. Figure 9The upper end of G1 in G20 is connected to the drain of PU2 via another shared contact plug. One end of the second gate G2 (i.e. Figure 9 The upper end of G2 in the middle 20) is connected to the source of PG1b via a shared contact plug, and the other end (i.e. Figure 9 The lower end of G2 in 20 is connected to the drain of PU1 via another shared contact plug SCT.
[0057] In summary, the SRAM test structure of this invention, based on the layout of the current test structure, removes all shared contact plugs on the gate terminals of pull-down transistors (or pull-up transistors) that need to be connected (i.e., connected to the test pads), replacing them with smaller contact plugs. The gate terminal of the pull-down transistor is then connected to the first layer of metal lines through these contact plugs, and then to the second layer of metal lines through vias, finally connecting to the corresponding test pads. This modifies the connection path compared to the current test structure, eliminates the leakage current contributed by parasitic transistors in the current test structure, solves the problem of the source of various leakage current contributions during the gate tunneling leakage current Iginv test, and thus monitors the electrical problems of the MOS transistors in the SRAM bitcell in a timely manner. It accurately determines the leakage current contribution path under the static power consumption of the SRAM bitcell, providing a clearer direction for subsequent process optimization of Iginv, and also providing timely guidance for the optimization of the gate oxide layer process.
[0058] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.
Claims
1. An SRAM test structure, characterized in that, Includes at least one first test unit formed on a substrate and required to be connected to a test pad, the first test unit including a first pull-up transistor, a second pull-up transistor, a first pull-down transistor and a second pull-down transistor formed on the substrate and having active regions spaced apart from each other; The first pull-up transistor and the first pull-down transistor share a first gate; The second pull-up transistor and the second pull-down transistor share a second gate; In this test unit, the first gate is connected to the first metal line via a contact plug with a size no larger than a standard contact plug. The first metal line is connected to the second metal line via a corresponding conductive via. The second metal line is connected to the corresponding test pad.
2. The SRAM test structure as described in claim 1, characterized in that, The first test unit further includes a first transmission transistor, a second transmission transistor, a third transmission transistor, and a fourth transmission transistor formed in the substrate with their active regions spaced apart from each other; wherein the active regions of the first transmission transistor and the first pull-down transistor are integrated, and the active regions of the fourth transmission transistor and the second pull-down transistor are integrated; the source of the first transmission transistor, the drain of the first pull-up transistor, the drain of the first pull-down transistor, and the second gate of the first test unit are electrically connected through corresponding standard contact plugs and corresponding first metal lines; the source of the third transmission transistor, the source of the fourth transmission transistor, the drain of the second pull-up transistor, and the drain of the second pull-down transistor are electrically connected through corresponding standard contact plugs and corresponding first metal lines.
3. The SRAM test structure as described in claim 2, characterized in that, The second transmission transistor and the fourth transmission transistor share the same word line gate, and the first transmission transistor and the third transmission transistor share the same word line gate.
4. The SRAM test structure as described in claim 2, characterized in that, The source of the second transmission transistor is also electrically connected to the second gate via a shared contact plug, the shared contact plug being larger than the standard contact plug.
5. The SRAM test structure as described in claim 2, characterized in that, The first pull-up transistor and the first pull-down transistor are connected to form an inverter, and the second pull-up transistor and the second pull-down transistor are connected to form another inverter.
6. The SRAM test structure as described in any one of claims 1-5, characterized in that, The drain of the first pull-down transistor is connected to the first metal line via a corresponding standard contact plug, and further connected to the second metal line via a corresponding conductive via, to connect to the corresponding test pad; and / or, the drain of the first pull-up transistor is connected to the first metal line via a corresponding standard contact plug, and further connected to the second metal line via a corresponding conductive via, to connect to the corresponding test pad.
7. The SRAM test structure as described in claim 6, characterized in that, It also includes at least one second test unit formed on the substrate and not connected to the test pad, the second test unit including a first to a fourth transfer transistor, a first pull-up transistor, a second pull-up transistor, a first pull-down transistor and a second pull-down transistor; wherein, the first pull-up transistor and the first pull-down transistor in the second test unit share another first gate; the second pull-up transistor and the second pull-down transistor in the second test unit share another second gate; The first gate of the second test unit is connected to the drain of the second pull-up transistor and the source of the third transmission transistor of the second test unit through a corresponding shared contact plug.
8. The SRAM test structure as described in claim 7, characterized in that, The second gate of the second test unit is connected to the drain of the first pull-up transistor and the source of the second transmission transistor of the second test unit through a corresponding shared contact plug.
9. The SRAM test structure as described in claim 7, characterized in that, The active region layout and gate layout of each transistor in the second test unit are the same as those of the corresponding transistor in the first test unit.
10. The SRAM test structure as described in claim 7, characterized in that, The first pull-up transistor and the first pull-down transistor in the second test unit are connected to form an inverter, and the second pull-up transistor and the second pull-down transistor in the second test unit are connected to form another inverter. The two inverters in the second test unit are cross-coupled.