Semiconductor device

Abstract

A semiconductor device is disclosed. The semiconductor device may include a first interlayer insulating layer on a semiconductor substrate, a first conductive pattern penetrating the first interlayer insulating layer, a second interlayer insulating layer on the first interlayer insulating layer, a second conductive pattern disposed in the second interlayer insulating layer and coupled to the first conductive pattern, and separation insulating patterns disposed between the second conductive patterns in the second interlayer insulating layer. A portion of the second interlayer insulating layer may be between a side surface of the separation insulating pattern and a side surface of the second conductive pattern.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0164567, filed on November 18, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0004] Higher integration levels are needed in semiconductor devices to meet consumer demand for superior performance and low prices. In the case of semiconductor devices, integration level is a crucial factor in determining product price. In the case of two-dimensional or planar semiconductor devices, because their integration level is primarily determined by the area occupied by a single memory cell, it is greatly influenced by the level of fine patterning technology. Therefore, various studies are underway to overcome the technological limitations associated with the scaling down of semiconductor devices and to achieve high-performance semiconductor devices. Summary of the Invention

[0005] One or more embodiments provide a semiconductor device having a simplified structure and which can be manufactured by a simplified process.

[0006] According to one aspect of an embodiment, a semiconductor device includes: a first interlayer insulating layer on a semiconductor substrate; a first conductive pattern penetrating the first interlayer insulating layer; a second interlayer insulating layer on the first interlayer insulating layer; a second conductive pattern disposed in the second interlayer insulating layer and coupled to the first conductive pattern; and a separating insulating pattern disposed in the second interlayer insulating layer between the second conductive patterns. A portion of the second interlayer insulating layer lies between a side surface of the separating insulating pattern and a side surface of the second conductive pattern.

[0007] According to another aspect of the embodiments, a semiconductor device includes: a first interlayer insulating layer on a semiconductor substrate; a first conductive pattern penetrating the first interlayer insulating layer; a second interlayer insulating layer on the first interlayer insulating layer and covering a portion of the first conductive pattern; a second conductive pattern in the second interlayer insulating layer and coupled to the first conductive pattern; a separating insulating pattern disposed between the second conductive patterns, wherein the separating insulating pattern penetrates the second interlayer insulating layer; and a capping insulating layer on the top surface of the separating insulating pattern and the top surface of the second conductive pattern. The second conductive pattern includes: a contact portion penetrating the lower portion of the second interlayer insulating layer and contacting the first conductive pattern in the first conductive pattern; and a pad portion in the upper portion of the second interlayer insulating layer, wherein the pad portion is wider than the contact portion. The separating insulating pattern has a first side surface. The pad portion of the second conductive pattern has a second side surface. The distance between the first side surface and the second side surface decreases as the distance from the bottom surface of the second interlayer insulating layer increases in the upward direction.

[0008] According to another aspect of the embodiments, a semiconductor device includes: a semiconductor substrate including a first region and a second region; a device isolation layer in the semiconductor substrate, defining a cell active region in the first region and a peripheral active region in the second region; a word line structure in the semiconductor substrate extending across the cell active region along a first direction; a bit line structure intersecting the cell active region in the first region; buried contact patterns on opposite sides of the bit line structures and connected to the cell active regions; landing pads respectively connected to the buried contact patterns to cover a portion of the bit line structure; a gate structure on the peripheral active region; and source / drain regions on the periphery. The source region is disposed on opposite sides of the gate structure; a first interlayer insulating layer covers the gate structure in a second region; a first conductive pattern is disposed on opposite sides of the gate structure to penetrate the first interlayer insulating layer and is connected to the source / drain region; a second interlayer insulating layer is located on the first interlayer insulating layer in the second region and covers a portion of the first conductive pattern; a second conductive pattern is disposed in the second interlayer insulating layer and coupled to the first conductive pattern; a separating insulating pattern is disposed between the second conductive patterns, wherein the separating insulating pattern penetrates the second interlayer insulating layer; and a capping insulating layer is on the top surface of the separating insulating pattern and the top surface of the second conductive pattern.

[0009] According to another aspect of the embodiments, a method of manufacturing a semiconductor device includes: forming a first interlayer insulating layer to cover a semiconductor substrate; forming a first conductive pattern penetrating the first interlayer insulating layer; forming a second interlayer insulating layer to cover the first conductive pattern; patterning the second interlayer insulating layer to form a separation trench; forming a separation insulating pattern to fill the separation trench; patterning an upper portion of the second interlayer insulating layer to form a pad trench between the separation insulating patterns; patterning a lower portion of the second interlayer insulating layer to form a contact hole connected to the pad trench and exposing the first conductive pattern; forming a second conductive pattern to fill the pad trench and the contact hole; and forming a capping insulating layer to cover the top surface of the second conductive pattern and the top surface of the separation insulating pattern.

[0010] In one embodiment, the pad trench may have a width that decreases in the downward direction.

[0011] In one embodiment, the pad trench may have a second side surface that is spaced apart from the first side surface of the separated insulating pattern.

[0012] In an embodiment, the method of manufacturing a semiconductor device may further include forming an opening in a portion of a second interlayer insulating layer while forming a separation trench. Forming a separation insulating pattern may include: depositing a separation insulating layer to fill the separation trench and conformally cover the opening; and etching the separation insulating layer to expose the top surface of the second interlayer insulating layer and form separation insulating spacers in the opening.

[0013] In an embodiment, the method of manufacturing a semiconductor device may further include: forming a device isolation layer to define a cell active region and a peripheral active region; forming a bit line structure intersecting the cell active region and a gate structure intersecting the peripheral active region; forming buried contact patterns on opposite sides of the bit line structures, wherein the buried contact patterns are connected to the cell active regions; and forming landing pads respectively connected to the buried contact patterns to cover a portion of the bit line structure. The landing pads may be formed simultaneously with the formation of the first conductive pattern. Attached Figure Description

[0014] The above and other aspects, features and advantages of the embodiments will become clearer from the accompanying drawings and the following description.

[0015] Figure 1 This is a plan view illustrating a semiconductor device according to an embodiment.

[0016] Figure 2A This is used to illustrate the edge of the semiconductor device according to the embodiment. Figure 1 The cross-sectional view taken by lines A-A' and D-D'.

[0017] Figure 2B This is used to illustrate the edge of the semiconductor device according to the embodiment. Figure 1The cross-sectional view taken by lines B-B' and C-C'.

[0018] Figure 3A and Figure 3B This illustrates an embodiment. Figure 2B A magnified cross-sectional view of part P1.

[0019] Figures 4 to 16 This is used to illustrate the method of manufacturing a semiconductor device according to an embodiment. Figure 1 The cross-sectional views taken from lines A-A', B-B', and C-C'. Detailed Implementation

[0020] The exemplary embodiments will now be described more fully with reference to the accompanying drawings, which illustrate exemplary embodiments. Each embodiment provided in the following description does not exclude association with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with this disclosure. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element or layer is referred to as being “directly” on, directly connected to, or directly coupled to another element or layer, there are no intermediate elements or layers. Unless otherwise indicated, the terms “higher” and “lower” indicate vertical alignment relative to the drawings. When following a list of elements, terms such as “…”

[0021] The phrase "at least one of" modifies the entire list of elements, not individual elements. For example, the phrase "at least one of a, b, and c" should be understood as including only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. It will also be understood that when a specific operation of manufacturing equipment or structure is described after another operation, that operation may be performed after that other operation, unless the other operation is described as being performed after that operation.

[0022] Figure 1 This is a plan view illustrating a semiconductor device according to an embodiment. Figure 2A This is used to illustrate the edge of the semiconductor device according to the embodiment. Figure 1 The cross-sectional view taken by lines A-A' and D-D'. Figure 2B This is used to illustrate the edge of the semiconductor device according to the embodiment. Figure 1 The cross-sectional view taken by lines B-B' and C-C'. Figure 3A and Figure 3B It is shown Figure 2BA magnified cross-sectional view of part P1.

[0023] Reference Figure 1 , Figure 2A and Figure 2B The semiconductor substrate 100 may be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The semiconductor substrate 100 may include a first region CAR, a second region PCR, and a third region SL.

[0024] The first region, CAR, can be a memory cell array region, on which word lines, bit lines, and memory cells are arranged. The second region, PCR, can be a peripheral circuit region, on which peripheral circuitry controlling the memory cells (e.g., sense amplifiers or word line drivers) is arranged. The third region, SL, can be a scribing region or edge region, on which monitoring and test patterns for manufacturing processes are arranged. Overlay keys, alignment keys, or photolithography keys can be arranged on the third region, SL.

[0025] Device isolation layer 101 may be disposed in the first region CAR to define a cell active region ACT in the semiconductor substrate 100. Device isolation layer 101 may be formed of at least one of silicon oxide, silicon nitride, and silicon oxynitride, or include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The top surface of device isolation layer 101 may be coplanar with the top surface of semiconductor substrate 100.

[0026] In an embodiment, when viewed in a plan view, the active area ACT of the unit can have a rectangular or strip shape and can be arranged two-dimensionally in a first direction D1 and a second direction D2 that intersect each other. For example, the first direction D1 and the second direction D2 can be perpendicular to each other. A third direction D3 can correspond to a vertical direction perpendicular to each of the first direction D1 and the second direction D2. When viewed in a plan view, the active area ACT of the unit can be arranged in a zigzag pattern and can have a major axis extending in a direction diagonally opposite to the first direction D1 and the second direction D2.

[0027] When viewed in a plan view, multiple word line structures (WLS) can be disposed in the semiconductor substrate 100 and can extend in a first direction D1 to intersect with the cell active region ACT and the device isolation layer 101. Each of the cell active regions ACT can intersect with a pair of word line structures (WLS).

[0028] Each of the word line structures WLS may include a word line WL, a gate insulating pattern 103 between the semiconductor substrate 100 and the word line WL, and a gate capping pattern 105 on the word line WL.

[0029] The top surface of the word line WL can be located at a level lower than the top surface of the semiconductor substrate 100. The height of the bottom surface of the word line WL can vary depending on the material of the underlying device. As an example, the portion of the bottom surface of the word line WL disposed on the cell active region ACT can be located at a height higher than other portions disposed on the device isolation layer 101. The top surface of the gate cap pattern 105 can be substantially coplanar with the top surface of the semiconductor substrate 100 and the top surface of the device isolation layer 101.

[0030] The word line WL may include a conductive material. The gate insulating pattern 103 may be formed of at least one of a high-k dielectric material, silicon oxide, silicon nitride, and silicon oxynitride, or may include at least one of a high-k dielectric material, silicon oxide, silicon nitride, and silicon oxynitride. The gate insulating pattern 103 may have a single-layer or multi-layer structure. Here, the high-k dielectric material may include hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0031] The top surface of the gate cap pattern 105 may be located at substantially the same level as the top surface of the semiconductor substrate 100 and the top surface of the device isolation layer 101. The gate cap pattern 105 may be formed of an insulating material different from that of the device isolation layer 101, or may include an insulating material different from that of the device isolation layer 101. The gate cap pattern 105 may be formed of at least one of silicon nitride and / or silicon oxynitride, or may include at least one of silicon nitride and / or silicon oxynitride.

[0032] A first impurity region 1a and a second impurity region 1b can be formed on opposite sides of the word line structure WLS in each cell active region ACT. The bottom surfaces of the first impurity region 1a and the second impurity region 1b can be located at a specific depth from the top surface of the cell active region ACT. The first impurity region 1a can be disposed in the portion of each cell active region ACT located between the word line structures WLS, and the second impurity region 1b can be disposed in the end of each cell active region ACT spaced apart from the first impurity region 1a. The first impurity region 1a and the second impurity region 1b can be doped to have a different conductivity type than the semiconductor substrate 100.

[0033] A first buffer insulating layer 111 and a second buffer insulating layer 113 may be sequentially disposed on the semiconductor substrate 100. As an example, the first buffer insulating layer 111 may be a silicon oxide layer, and the second buffer insulating layer 113 may be a silicon nitride layer. Alternatively, only one of the first buffer insulating layer 111 and the second buffer insulating layer 113 may be disposed. When viewed in a plan view, each of the first buffer insulating layer 111 and the second buffer insulating layer 113 may be an island pattern or an isolation pattern. In an embodiment, the first buffer insulating layer 111 and the second buffer insulating layer 113 may be configured to cover the ends of two adjacent cell active regions ACT and a portion of the device isolation layer 101 between them.

[0034] Bit line structures (BLS) can be disposed on a first region (CAR) of the semiconductor substrate 100 and can extend in a second direction (D2) to intersect with word line structures (WLS). The bit line structures (BLS) can be disposed on a first impurity region (1a). In an embodiment, each bit line structure (BLS) may include a polysilicon pattern 121 extending in the second direction (D2), a bit line 125 on the polysilicon pattern 121, and a hard mask pattern (HM) on the bit line 125.

[0035] The first buffer insulating layer 111 and the second buffer insulating layer 113 can be inserted between the polysilicon pattern 121 and the semiconductor substrate 100. A bit line contact pattern DC can be disposed between the bit line 125 and the first impurity region 1a. The bit line contact pattern DC can contact the first impurity region 1a. The bit line contact pattern DC can be offset from the second impurity region 1b. For example, the bit line contact pattern DC and the second impurity region 1b may not overlap on the third direction D3.

[0036] The bit line contact pattern DC may be formed of or comprise polysilicon, and a silicide pattern 123 may be inserted between the bit line contact pattern DC and the bit line 125, and between the polysilicon pattern 121 and the bit line 125. The silicide pattern 123 may be formed of at least one of titanium silicide, cobalt silicide, and nickel silicide, or may comprise at least one of titanium silicide, cobalt silicide, and nickel silicide. The bit line 125 may be formed of at least one of a conductive metal nitride material (e.g., titanium nitride and tantalum nitride) and a metallic material (e.g., tungsten, titanium, and tantalum), or may comprise at least one of a conductive metal nitride material (e.g., titanium nitride and tantalum nitride) and a metallic material (e.g., tungsten, titanium, and tantalum).

[0037] The bottom surface of the bit line contact pattern DC can be located at a level below the top surface of the semiconductor substrate 100 and above the top surface of the word line WL. For example, the bit line contact pattern DC can be locally disposed in a recessed region RS, which is formed in the semiconductor substrate 100 to expose the first impurity region 1a.

[0038] In a bitline structure (BLS), the hard mask pattern (HM) may include an insulating material (e.g., silicon nitride).

[0039] The bit line contact spacer DCS can fill the remaining space of the recessed region RS that is partially filled by the bit line contact pattern DC. In an embodiment, the bit line contact spacer DCS can cover the opposite side surfaces of the bit line contact pattern DC. For example, the bit line contact spacer DCS may include at least one of silicon oxide, silicon nitride, and / or silicon oxynitride. For example, the bit line contact spacer DCS may have a multilayer structure.

[0040] In an embodiment, bit line spacers 131 and 133 may be disposed on opposite side surfaces of the bit line structure BLS. Bit line spacers 131 and 133 may extend in the second direction D2 and along the side surfaces of the bit line structure BLS. Bit line spacers 131 and 133 may be disposed between the side surfaces of the bit line structure BLS and the embedded contact pattern BC.

[0041] In the first region CAR, the buried contact pattern BC can be disposed between adjacent pairs of bit line structures BLS. The buried contact pattern BC can be formed from at least one of doped polysilicon and a metallic material, or include at least one of doped polysilicon and a metallic material. The buried contact pattern BC can be in direct contact with the second impurity region 1b. When viewed in a plan view, the buried contact pattern BC can be disposed between word line structures WLS and between bit line structures BLS, respectively.

[0042] The embedded contact patterns BC can be arranged in two dimensions and spaced apart from each other. The top surface of the embedded contact patterns BC can be located at a lower level than the top surface of the bit line structure BLS.

[0043] The bottom surface of the embedded contact pattern BC can be located at a level below the top surface of the semiconductor substrate 100 and above the bottom surface of the bit line contact pattern DC. Furthermore, the embedded contact pattern BC can be electrically disconnected from the bit line contact pattern DC via the bit line contact spacer DCS.

[0044] The fence insulation pattern FC can be disposed between the bit line structures BLS, spaced apart from each other in the second direction D2. The fence insulation pattern FC can be disposed between adjacent embedded contact patterns BC along the second direction D2. When viewed in a plan view, the fence insulation pattern FC can overlap with the word line WL. The fence insulation pattern FC can be formed of or comprise an insulating material (e.g., silicon nitride).

[0045] Landing pads LP can be individually positioned on the embedded contact pattern BC. Landing pads LP can be individually electrically connected to the embedded contact pattern BC.

[0046] In an embodiment, a landing pad LP may include a lower portion and an upper portion, the lower portion being formed to fill the space between bit line structures BLS, and the upper portion extending from the lower portion to face a portion of the bit line structure BLS. In this respect, when viewed in a plan view, the upper portion of the landing pad LP may overlap with a portion of the bit line structure BLS. Each of the upper portions of the landing pad LP may cover the top surface of the hard mask pattern HM of the bit line structure BLS and may have a width larger than the buried contact pattern BC. That is, the width of the upper portion of the landing pad LP may be greater than the distance between the bit line structures BLS or the width of the bit line structure BLS. In this case, because the upper portion of the landing pad LP extends to an area on the bit line structure BLS, the top surface of the landing pad LP may have an increased area.

[0047] The top surface of the landing pad LP can be located at a level higher than the top surface of the bit line structure BLS, and the bottom surface of the landing pad LP can be located at a level lower than the top surface of the bit line structure BLS.

[0048] In an embodiment, when viewed in a plan view, the upper part of the landing pad LP may have an elliptical shape with a major axis and a minor axis, and here, the major axis of the upper part of the landing pad LP may be inclined in a direction diagonally opposite to both the first direction D1 and the second direction D2. In an embodiment, the upper part of the landing pad LP may have a rounded rhombus, a rounded trapezoid, or a rounded quadrilateral.

[0049] Each of the landing pads LP may include a barrier metal pattern and a metal pattern. The barrier metal pattern may be formed of at least one of conductive metal nitride materials (e.g., titanium nitride, tantalum nitride, and tungsten nitride), or may include at least one of conductive metal nitride materials (e.g., titanium nitride, tantalum nitride, and tungsten nitride). The metal pattern may be formed of at least one of metallic materials (e.g., tungsten, titanium, and tantalum), or may include at least one of metallic materials (e.g., tungsten, titanium, and tantalum). Furthermore, a metal silicide layer (e.g., titanium silicide, cobalt silicide, nickel silicide, tungsten silicide, platinum silicide, or molybdenum silicide) may be inserted between the barrier metal pattern and the buried contact pattern BC of each landing pad LP.

[0050] The pad insulating pattern 181 can fill the area between the upper portions of the landing pads LP. The pad insulating pattern 181 can have a rounded bottom surface, and the bottom surface of the pad insulating pattern 181 can partially contact the bit line spacers 131 and 133. The top surface of the pad insulating pattern 181 can be coplanar with the top surface of the landing pads LP. The pad insulating pattern 181 can be formed of at least one of silicon oxide, silicon nitride, and / or silicon oxynitride, or include at least one of silicon oxide, silicon nitride, and / or silicon oxynitride. The pad insulating pattern 181 can be configured to have a single-layer or multi-layer structure.

[0051] The capacitor CAP, used as a data storage element in the memory cell, can be disposed on the landing pad LP. In an embodiment, a variable resistance pattern can be used instead of the capacitor CAP as a data storage element, which can be switched to one of two different resistance states by an electrical pulse.

[0052] A capacitor CAP may include a bottom electrode BE, a top electrode TE, and a dielectric layer CIL inserted therebetween.

[0053] The bottom electrode BE can be electrically connected to the second impurity region 1b via the landing pad LP and the buried contact pattern BC, respectively. In an embodiment, when viewed in a plan view, the bottom electrode BE can be arranged to form a honeycomb shape or a zigzag shape.

[0054] The bottom electrode BE can be disposed on the landing pad LP. The bottom electrode BE can be cylindrical or cylindrical. The bottom electrode BE can be formed of at least one of the following materials: metallic material (e.g., ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo) and / or tungsten (W)), conductive metal nitride material (e.g., titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN) and / or tungsten nitride (WN)), and conductive metal oxide material (e.g., iridium oxide (IrO2), ruthenium oxide (RuO2) and / or strontium ruthenium oxide (SrRuO3)), or including at least one of the above materials.

[0055] Support patterns SP1 and SP2 can be disposed on the side surface of the bottom electrode BE. Support patterns SP1 and SP2 can be vertically spaced apart from each other. Support patterns SP1 and SP2 can contact and connect to the side surface of the bottom electrode BE. Support patterns SP1 and SP2 can physically support the bottom electrode BE, thereby preventing the bottom electrode BE from collapsing or tilting. Support patterns SP1 and SP2 can be formed of at least one of silicon oxide, silicon nitride, and / or silicon oxynitride, or can include at least one of silicon oxide, silicon nitride, and / or silicon oxynitride.

[0056] A dielectric layer CIL can be disposed on the bottom electrode BE. The dielectric layer CIL can be disposed on the side surface of the bottom electrode BE and the top and bottom surfaces of the support patterns SP1 and SP2. The dielectric layer CIL can conformally cover the side surface of the bottom electrode BE and the top and bottom surfaces of the support patterns SP1 and SP2. The dielectric layer CIL can have a single-layer or multi-layer structure. The dielectric layer CIL can be formed from at least one of a metal oxide material, a perovskite dielectric material, and / or a combination thereof, or include at least one of a metal oxide material, a perovskite dielectric material, and / or a combination thereof. In embodiments, the metal oxide material may include HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and / or TiO2. The perovskite dielectric material may include SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT, and / or PLZT.

[0057] The top electrode TE can be disposed on the dielectric layer CIL facing the bottom electrode BE. In embodiments, the top electrode TE can be formed of at least one of a doped semiconductor material, a metallic material, a metal nitride material, and a metal silicide material, or include at least one of a doped semiconductor material, a metallic material, a metal nitride material, and a metal silicide material. The semiconductor material can include silicon, germanium, and / or silicon-germanium.

[0058] In this embodiment, various peripheral circuits for operating the memory cells may be disposed on the second region PCR of the semiconductor substrate 100. The peripheral circuits may be electrically connected to the memory cells. In this embodiment, the peripheral circuits may include a sense amplifier circuit and a sub-word line driver circuit. The peripheral circuits may also include a power supply circuit and a grounding circuit for driving the sense amplifier, but the embodiment is not limited thereto.

[0059] More specifically, the peripheral active region ACT1 can be defined in the second region PCR by means of the device isolation layer 101.

[0060] A peripheral gate structure GS may be disposed on a peripheral active region ACT1, and a source / drain region SD may be disposed on opposite sides of the peripheral gate structure GS in the semiconductor substrate 100. The source / drain region SD may contain impurities of a first conductivity type (e.g., n-type) doped into the semiconductor substrate 100.

[0061] The peripheral gate structure GS may include a peripheral polysilicon pattern 122, a peripheral silicide pattern 124, a peripheral metal pattern 126 and a peripheral hard mask pattern PHM stacked sequentially.

[0062] The peripheral polysilicon pattern 122 may have substantially the same thickness as the polysilicon pattern 121 in the first region CAR. The peripheral silicide pattern 124 may have substantially the same thickness as the silicide pattern 123 in the first region CAR, and may include the same metallic material as the silicide pattern 123. The peripheral metal pattern 126 may have substantially the same thickness as the bit line 125 in the first region CAR, and may include the same metallic material as the bit line 125.

[0063] A first gate insulating pattern 112 and a second gate insulating pattern 114 can be interposed between a peripheral polysilicon pattern 122 and a semiconductor substrate 100. The first gate insulating pattern 112 may have substantially the same thickness as the first buffer insulating layer 111 in the first region CAR and may comprise the same material as the first buffer insulating layer 111. The second gate insulating pattern 114 may have substantially the same thickness as the second buffer insulating layer 113 in the first region CAR and may comprise the same material as the second buffer insulating layer 113.

[0064] The first interlayer insulating layer 160 may cover the peripheral gate structure GS and the semiconductor substrate 100 in the second region PCR and the third region SL. The first interlayer insulating layer 160 may include an insulating material. As an example, the first interlayer insulating layer 160 may be formed of at least one of silicon oxide, silicon nitride, tetraethyl orthosilicate (TEOS), and a low-k dielectric material, or may include at least one of silicon oxide, silicon nitride, tetraethyl orthosilicate (TEOS), and a low-k dielectric material.

[0065] In the second region PCR and the third region SL, a first etch stop layer 143 can be disposed on the semiconductor substrate 100. The first etch stop layer 143 can conformally cover the peripheral gate structure GS.

[0066] The first etch stop layer 143 may be formed of an insulating material having etch selectivity relative to the first interlayer insulating layer 160 and the semiconductor substrate 100. For example, the first etch stop layer 143 may be formed of silicon nitride and / or silicon oxynitride, or may include silicon nitride and / or silicon oxynitride.

[0067] The peripheral gate spacer SS can be disposed on the opposite side surface of the peripheral gate structure GS. The peripheral gate spacer SS can be formed of at least one of silicon oxide, silicon nitride and / or silicon oxynitride, or include at least one of silicon oxide, silicon nitride and / or silicon oxynitride.

[0068] In this embodiment, the first conductive pattern CP1 can penetrate the first interlayer insulating layer 160 and the first etch stop layer 143 on the opposite side of the peripheral gate structure GS, and can be coupled to the source / drain region SD. The first conductive pattern CP1 in the second region PCR can connect the bit line 125 in the first region CAR to the peripheral circuitry. As an example, the bit line 125 in the first region CAR can be electrically connected to the source / drain region SD in the second region PCR via the first conductive pattern CP1.

[0069] Each of the first conductive patterns CP1 may include a contact portion and a pad portion. The contact portion penetrates the first interlayer insulating layer 160 and contacts the source / drain region SD. The pad portion is disposed on the first interlayer insulating layer 160 and connected to the contact portion. The pad portion of each first conductive pattern CP1 may have a side surface that directly contacts the first insulating pattern 183.

[0070] The top surface of the first conductive pattern CP1 (i.e., the top surface of the pad portion of the first conductive pattern CP1) is substantially coplanar with the top surface of the landing pad LP in the first region CAR.

[0071] The first conductive pattern CP1 may be formed from at least one of a conductive metal nitride material (e.g., titanium nitride and tantalum nitride) and a metallic material (e.g., tungsten, titanium and tantalum), or may include at least one of a conductive metal nitride material (e.g., titanium nitride and tantalum nitride) and a metallic material (e.g., tungsten, titanium and tantalum).

[0072] For details, refer to Figure 3A and Figure 3B The first conductive pattern CP1 may include a barrier metal pattern BM and a metal pattern ME on the barrier metal pattern BM. The barrier metal pattern BM may have a substantially constant thickness. The barrier metal pattern BM and the metal pattern ME may have side surfaces in direct contact with the first insulating pattern 183. Furthermore, a metal silicide pattern may be inserted between the first conductive pattern CP1 and the source / drain region SD.

[0073] A first insulating pattern 183 may be disposed between first conductive patterns CP1. The first insulating pattern 183 may be disposed between the pad portions of the first conductive patterns CP1. The first insulating pattern 183 may be in direct contact with the side surface of the pad portion of the first conductive patterns CP1. The top surface of the first insulating pattern 183 may be substantially coplanar with the top surface of the first conductive patterns CP1.

[0074] The first insulating pattern 183 may cover the top surface of the first interlayer insulating layer 160 in the third region SL. In embodiments, the first insulating pattern 183 may be formed of at least one of silicon oxide, silicon nitride, and / or silicon oxynitride, or include at least one of silicon oxide, silicon nitride, and / or silicon oxynitride. The first insulating pattern 183 may be configured to have a single-layer or multi-layer structure. The first insulating pattern 183 may include the same insulating material as the pad insulating pattern 181 of the first region CAR.

[0075] A second etch stop layer 190 may be disposed on the semiconductor substrate 100. The second etch stop layer 190 may cover the top surface of the pad insulating pattern 181 in the first region CAR, and may cover the top surface of the first conductive pattern CP1 and the top surface of the first insulating pattern 183 in the second region PCR and the third region SL. The second etch stop layer 190 may be formed of silicon nitride and / or silicon oxynitride, or may include silicon nitride and / or silicon oxynitride.

[0076] In the second region PCR and the third region SL, a second interlayer insulating layer 200 may be disposed on the second etch stop layer 190. The second interlayer insulating layer 200 may include an insulating material. In an embodiment, the second interlayer insulating layer 200 may be formed of at least one of silicon oxide, silicon nitride, TEOS, and a low-k dielectric material, or may include at least one of silicon oxide, silicon nitride, TEOS, and a low-k dielectric material.

[0077] Separating insulating patterns 215 can be configured to vertically penetrate the second interlayer insulating layer 200. Each of the separating insulating patterns 215 can be disposed between adjacent second conductive patterns CP2 in the second conductive patterns CP2. Each of the separating insulating patterns 215 can be formed of, or include, silicon nitride or silicon oxynitride. Each of the separating insulating patterns 215 can have a single-layer structure. Each of the separating insulating patterns 215 can have a width that gradually decreases from its top surface to its bottom surface.

[0078] For more details, see [link to relevant documentation]. Figure 3A and Figure 3B Each of the separate insulating patterns 215 may have a first side surface SW1, and the first side surface SW1 of each separate insulating pattern 215 may be inclined at an acute angle (e.g., a first angle θ1) relative to the bottom surface of the second interlayer insulating layer 200. The first angle θ1 may range from about 1° to about 89°.

[0079] The second conductive pattern CP2 can be disposed in the second interlayer insulating layer 200 and in the second region PCR, and can be coupled to the first conductive pattern CP1. The second conductive pattern CP2 can be formed of at least one of conductive metal nitride materials (e.g., titanium nitride and tantalum nitride) and metallic materials (e.g., tungsten, titanium, and tantalum), or include at least one of conductive metal nitride materials (e.g., titanium nitride and tantalum nitride) and metallic materials (e.g., tungsten, titanium, and tantalum).

[0080] The second conductive pattern CP2 may be laterally spaced from the separation insulating pattern 215. For example, a portion of the second interlayer insulation layer 200 may be disposed between the first side surface SW1 of the separation insulating pattern 215 and the second side surface SW2 of the second conductive pattern CP2.

[0081] The distance between the first side surface SW1 of each separating insulating pattern 215 and the second side surface SW2 of each second conductive pattern CP2 can decrease as the distance from the bottom surface of the second interlayer insulating layer 200 increases in the upward direction. For example, between the second conductive pattern CP2 and the separating insulating pattern 215, a portion of the second interlayer insulating layer 200 can have a pointed (i.e., become a point) or truncated (i.e. have a flat upper surface) angle or wedge shape.

[0082] For details, refer to Figure 3A and Figure 3B Each of the second conductive patterns CP2 may include a contact portion Pa and a pad portion Pb. The contact portion Pa penetrates the second interlayer insulating layer 200 and the second etch stop layer 190 and contacts one of the first conductive patterns CP1. The pad portion Pb is disposed in the second interlayer insulating layer 200 and connected to the contact portion Pa. The top surface of the pad portion Pb of each second conductive pattern CP2 may have a first width W1, and the bottom surface of the pad portion Pb may have a second width W2 that is smaller than the first width W1.

[0083] Each pad portion Pb of the second conductive pattern CP2 may have a second side surface SW2. The second side surface SW2 of the second conductive pattern CP2 may be inclined at an obtuse angle (e.g., a second angle θ2) relative to the bottom surface of the second interlayer insulating layer 200. The second angle θ2 may be in the range of approximately 91° to 179°.

[0084] The top surface of the second conductive pattern CP2 can be substantially coplanar with the top surface of the separate insulating pattern 215.

[0085] Each of the second conductive patterns CP2 may include a first metal pattern ME1 and a first barrier metal pattern BM1, the first barrier metal pattern BM1 being disposed between the side surface of the first metal pattern ME1 and the second interlayer insulating layer 200, and having a substantially constant thickness.

[0086] Reference Figure 3A The width of each second conductive pattern CP2 may be less than the minimum distance between adjacent separating insulating patterns 215 in the separating insulating patterns 215. That is, the side surface of the first barrier metal pattern BM1 may be spaced apart from the separating insulating patterns 215. (Refer to...) Figure 3B The minimum distance between adjacent separating insulating patterns 215 in the separating insulating pattern 215 can be substantially equal to the width of each second conductive pattern CP2. For example, at least a portion of the first barrier metal pattern BM1 of each second conductive pattern CP2 can be in contact with the separating insulating pattern 215.

[0087] The capping insulating layer 240 can cover the top surface of the second conductive pattern CP2 and the top surface of the separation insulating pattern 215 with a substantially constant thickness. The capping insulating layer 240 can be formed of silicon nitride and / or silicon oxynitride, or include silicon nitride and / or silicon oxynitride.

[0088] In the third zone SL, the second interlayer insulation layer 200 may have an opening, and a separating insulation spacer 217 may be disposed on the side surface of the opening. The separating insulation spacer 217 may comprise the same insulating material as the separating insulation pattern 215.

[0089] In the third zone SL, the alignment key pattern AK can be disposed in the opening provided in the separation insulating spacer 217. The alignment key pattern AK can include the same conductive material as the second conductive pattern CP2.

[0090] The alignment key pattern AK may have a U-shaped cross-section defining a recessed area, and the recessed area may be filled with a gap-filling insulating pattern 231. The capping insulating layer 240 may cover the alignment key pattern AK and the gap-filling insulating pattern 231 in the third region SL.

[0091] In the second region PCR and the third region SL, a third interlayer insulating layer 251 can be disposed on the capping insulating layer 240. The third interlayer insulating layer 251 can be configured to have a single-layer or multi-layer structure. The third interlayer insulating layer 251 can be formed of at least one of borophosphosilicate glass (BPSG), tonnen silazane (TOSZ), undoped silicate glass (USG), spin-coated glass (SOG), flowable oxide (FOX), TEOS, high-density plasma chemical vapor deposition (HDP CVD) oxide, and hydrosilsesquioxane (HSQ), or include at least one of these materials. The thickness of the third interlayer insulating layer 251 in the first region CAR can vary depending on the vertical length of the bottom electrode BE.

[0092] The first upper insulating layer 253 can be disposed on the semiconductor substrate 100. The first upper insulating layer 253 can cover the top electrode TE in the first region CAR, and can cover the third interlayer insulating layer 251 in the second region PCR and the third region SL.

[0093] The unit contact plug CCP can be disposed in the first region CAR to penetrate the first upper insulating layer 253 and can be coupled to the top electrode TE. In the second region PCR, the third conductive pattern CP3 can penetrate the third interlayer insulating layer 251 and the first upper insulating layer 253 and can be coupled to the second conductive pattern CP2 respectively. The unit contact plug CCP and the third conductive pattern CP3 can be formed of at least one of tungsten (W), titanium (Ti), tantalum (Ta) and their nitride materials, or include at least one of tungsten (W), titanium (Ti), tantalum (Ta) and their nitride materials.

[0094] In the first region CAR, the cell metal wire CM can be disposed on the first upper insulating layer 253 and can be connected to the cell contact plug CCP. In the second region PCR, the peripheral metal wire PM can be disposed on the first upper insulating layer 253 and can be connected to the third conductive pattern CP3. The second upper insulating layer 260 can be disposed on the first upper insulating layer 253 to surround or cover the cell metal wire CM and the peripheral metal wire PM.

[0095] Figures 4 to 16 This is used to illustrate the method of manufacturing a semiconductor device according to an embodiment. Figure 1 The cross-sectional views taken from lines A-A', B-B', and C-C'.

[0096] Reference Figure 1 and Figure 4The semiconductor substrate 100 may be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The semiconductor substrate 100 may include a first region CAR, a second region PCR, and a third region SL. As described above, the first region CAR may be a memory cell array region, and the second region PCR may be a peripheral circuit region. The third region SL may be a scribing region or an edge region, on which monitoring patterns and test patterns for manufacturing processes are formed.

[0097] Device isolation layer 101 can be formed in the first region CAR and the second region PCR of semiconductor substrate 100 to define the unit active region ACT and the peripheral active region ACT1.

[0098] The formation of device isolation layer 101 may include: forming an etching mask on semiconductor substrate 100, etching semiconductor substrate 100 using the etching mask to form trenches, forming an insulating layer to fill the trenches, and planarizing the insulating layer to expose the top surface of semiconductor substrate 100. Device isolation layer 101 may include an insulating material. Device isolation layer 101 may be formed of at least one of silicon oxide, silicon nitride, and silicon oxynitride, or may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. Semiconductor substrate 100 may be formed of at least one of silicon and germanium, or may include at least one of silicon and germanium.

[0099] In an embodiment, the active unit region ACT can be rectangular or strip-shaped and can be arranged in two dimensions along a first direction D1 and a second direction D2. When viewed in a plan view, the active unit region ACT can be arranged in a zigzag pattern and can have a major axis extending in a direction diagonally opposite to the first direction D1 and the second direction D2.

[0100] In the first region CAR, multiple word line structures can be formed in the semiconductor substrate 100 (e.g., Figure 2A The WLS) allows multiple word line structures to extend in the first direction D1.

[0101] Specifically, a gate recess region extending in the first direction D1 can be formed by patterning the active region ACT of the cell and the device isolation layer 101, and can be sequentially formed in the gate recess region (e.g., Figure 2A The gate insulating pattern 103 and the word line WL can be formed in the gate recess region where the word line WL is provided (e.g., Figure 2A (The) gate cap pattern 105.

[0102] After forming the word line structure WLS, a first impurity region 1a and a second impurity region 1b can be formed on opposite sides of the word line structure WLS within the cell active region ACT. The first impurity region 1a and the second impurity region 1b can be formed by performing an ion implantation process and can have a different conductivity type than that of the cell active region ACT. The first impurity region 1a can be formed in the central portion of each cell active region ACT, and the second impurity region 1b can be formed at opposite ends of each cell active region ACT.

[0103] Next, refer to Figure 1 and Figure 4 Bit line contact pattern DC and bit line structure BLS can be formed on the first region CAR of semiconductor substrate 100, and peripheral gate structure GS can be formed on the second region PCR of semiconductor substrate 100.

[0104] Alternatively, a first buffer insulating layer 111 and a second buffer insulating layer 113 may be sequentially formed on the semiconductor substrate 100. The first buffer insulating layer 111 and the second buffer insulating layer 113 may be formed by an oxidation process, a nitriding process, and / or a deposition process.

[0105] The first buffer insulating layer 111 may cover the top surface of the device isolation layer 101 and the top surface of the semiconductor substrate 100. The first buffer insulating layer 111 and the second buffer insulating layer 113 may include, for example, a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer. As an example, the first buffer insulating layer 111 may be a silicon oxide layer, and the second buffer insulating layer 113 may be a silicon nitride layer. Alternatively, one of the first buffer insulating layer 111 and the second buffer insulating layer 113 may be omitted. The second buffer insulating layer 113 may be thicker than the first buffer insulating layer 111.

[0106] Next, the semiconductor substrate 100 and the first buffer insulating layer 111 and the second buffer insulating layer 113 can be patterned to form a recessed region RS exposing the first impurity region 1a. When performing an anisotropic etching process to form the recessed region RS, the device isolation layer 101 and the gate cap pattern 105 adjacent to the first impurity region 1a can be partially etched (e.g., as shown in the image). Figure 2A (As shown).

[0107] Bit line structure BLS can be formed in the first region CAR, and peripheral gate structure GS can be formed in the second region PCR.

[0108] The formation of the bit line structure BLS and the peripheral gate structure GS may include: forming a conductive layer on the second buffer insulating layer 113 to fill the recessed region RS; forming a second conductive layer on the conductive layer; forming a hard mask layer on the second conductive layer; forming a bit line mask pattern on the hard mask layer; and sequentially etching the conductive layer, the second conductive layer, and the hard mask layer using the bit line mask pattern and the peripheral mask pattern. Next, the bit line mask pattern and the peripheral mask pattern may be removed. Here, the conductive layer may be a doped semiconductor layer (e.g., a doped polysilicon layer), and the second conductive layer may be a metal layer (e.g., a tungsten layer, an aluminum layer, a titanium layer, or a tantalum layer). Furthermore, a metal silicide layer may be formed between the conductive layer and the second conductive layer.

[0109] As a result of the above process, the bit line structure BLS can extend along the second direction D2 on the second buffer insulating layer 113 having the recessed region RS. The bit line structure BLS may include a polysilicon pattern 121, a silicide pattern 123, a bit line 125, and a hard mask pattern HM stacked sequentially. Here, a portion of the polysilicon pattern 121 may be locally formed in the recessed region RS to form a bit line contact pattern DC that is in direct contact with the first impurity region 1a. Furthermore, the side surfaces of the polysilicon pattern 121 may be spaced apart from the side surfaces of the recessed region RS.

[0110] The peripheral gate structure GS may include a first gate insulating pattern 112 and a second gate insulating pattern 114, a peripheral polysilicon pattern 122, a peripheral silicide pattern 124, a peripheral metal pattern 126 and a peripheral hard mask pattern PHM stacked sequentially.

[0111] After the peripheral gate structure GS is formed, the peripheral source / drain region SD can be formed by implanting dopants into the portion of the peripheral active region ACT1 on the opposite side of the peripheral gate structure GS.

[0112] After forming the bit line structure BLS and the peripheral source / drain region SD, a first etch stop layer 143 can be formed to conformally cover the peripheral gate structure GS. In an embodiment, the first etch stop layer 143 can be formed by depositing a silicon nitride layer.

[0113] Subsequently, bit line spacers 131 and 133 can be formed on the side surface of the bit line structure BLS.

[0114] The formation of bit line spacers 131 and 133 may include: sequentially depositing a first spacer layer and a second spacer layer to conformally cover the bit line structure BLS, and sequentially and anisotropically etching the first spacer layer and the second spacer layer. The first and second spacer layers may also be formed in the second region PCR and the third region SL, and may conformally cover the peripheral gate structure GS in the second region PCR. Here, the second spacer layer may include an insulating material having etch selectivity relative to the first spacer layer. As an example, the first spacer layer may be a silicon oxide layer, and the second spacer layer may be a silicon nitride layer. When the second spacer layer is anisotropically etched, the first spacer layer may serve as an etch stop layer, and when the first spacer layer is anisotropically etched, the second buffer insulating layer 113 may serve as an etch stop layer.

[0115] Bit line spacers 131 and 133 may extend along opposite side surfaces of the bit line structure BLS and in a second direction D2. In an embodiment, portions of bit line spacers 131 and 133 may be formed to fill the recessed region RS. During the formation of bit line spacers 131 and 133, peripheral gate spacers SS may be formed on the side surface of the peripheral gate structure GS.

[0116] After forming bit line spacers 131 and 133 and peripheral gate spacers SS, an insulating pad layer 150 may be formed on the semiconductor substrate 100. The insulating pad layer 150 may be formed of silicon nitride and / or silicon oxynitride, or may include silicon nitride and / or silicon oxynitride.

[0117] Reference Figure 1 and Figure 5 A first interlayer insulating layer 160 can be formed on the semiconductor substrate 100 to expose the first region CAR and cover the second region PCR and the third region SL.

[0118] The formation of the first interlayer insulating layer 160 may include: forming an insulating layer to cover the semiconductor substrate 100, and performing a planarization process to expose a first etch stop layer 143 on the peripheral gate structure GS. The first interlayer insulating layer 160 may be formed of at least one of BPSG, TOSZ, USG, SOG, FOX, TEOS, HDP CVD oxide, and HSQ, or may include at least one of BPSG, TOSZ, USG, SOG, FOX, TEOS, HDP CVD oxide, and HSQ.

[0119] An embedded contact pattern BC connected to the second impurity region 1b can be formed in the first region CAR. Furthermore, in the first region CAR, embedded contact patterns BC adjacent to each other along the second direction D2 can be formed (e.g., Figure 2A FC fence insulation pattern.

[0120] More specifically, the first interlayer insulating layer 160 can be removed from the first region CAR, and an anisotropic etching process can be performed on the first buffer insulating layer 111 and the second buffer insulating layer 113 using bit line spacers 131 and 133 and the bit line structure BLS as etching masks. Because the first buffer insulating layer 111 and the second buffer insulating layer 113 are anisotropically etched, a linear gap region extending in the second direction D2 can be formed between the bit line structures BLS. The top surface of the second impurity region 1b can be exposed through the linear gap region.

[0121] A contact conductive layer can be formed in the linear gap region. The contact conductive layer can be in direct contact with the second impurity region 1b. In embodiments, the contact conductive layer can be formed of at least one of a doped semiconductor material (e.g., doped silicon), a metallic material (e.g., tungsten, aluminum, titanium and / or tantalum), a conductive metal nitride material (e.g., titanium nitride, tantalum nitride and / or tungsten nitride), and a metal-semiconductor compound material (e.g., metal silicide), or include at least one of a doped semiconductor material (e.g., doped silicon), a metallic material (e.g., tungsten, aluminum, titanium and / or tantalum), a conductive metal nitride material (e.g., titanium nitride, tantalum nitride and / or tungsten nitride), and a metal-semiconductor compound material (e.g., metal silicide).

[0122] In one embodiment, forming the contact conductive layer may include depositing a doped polysilicon layer and performing a planarization process to expose the top surface of the bit line structure (BLS). The contact conductive layer may be formed to fill the linear gap region. Next, a mask pattern extending along a first direction D1 may be formed on the bit line structure (BLS) and the contact conductive layer. The mask pattern may be disposed between word line structures (WLS).

[0123] By using a mask pattern as an etching mask to anisotropically etch the contact conductive layer, exposures can be formed (e.g., Figure 2A The gate cap pattern 105 has a buried contact hole. A buried contact pattern BC can be formed in the buried contact hole. The buried contact patterns BC can be spaced apart from each other in the second direction D2 between the bit line structures BLS. In an embodiment, the bit line structures BLS and bit line spacers 131 and 133 can be partially etched during an anisotropic etching process of the contact conductive layer.

[0124] The fence insulation pattern FC can be formed before and after the formation of the embedded contact pattern BC. (For example, Figure 2AThe formation of the gate insulating pattern FC may include: forming a gate insulating layer between bit line structures BLS to fill a linear gap region extending in the second direction D2; forming a mask pattern extending in the first direction D1 on the gate insulating layer; and anisotropically etching the gate insulating layer using the mask pattern as an etching mask to expose the second impurity region 1b in the cell active region ACT. (For example, Figure 2A The fence insulation pattern FC can be formed of or include an insulating material (e.g., silicon nitride).

[0125] Reference Figure 1 and Figure 6 After the buried contact pattern BC is formed, the first mask pattern 165 can be formed on the semiconductor substrate 100.

[0126] In an embodiment, the first mask pattern 165 may be formed from an amorphous carbon layer (ACL) or a hard spin-coated (SOH) mask material (e.g., SOH silicon oxide).

[0127] The first mask pattern 165 can fill the region between the upper parts of the first region CAR median line structure BLS, and can be formed on the top surface of the first interlayer insulating layer 160 in the second region PCR and the third region SL. The first mask pattern 165 can have an opening formed on the second region PCR and corresponding to the peripheral source / drain region SD.

[0128] Subsequently, by using the first mask pattern 165 as an etching mask, contact holes CH can be formed to penetrate the first interlayer insulating layer 160 in the second region PCR and expose the peripheral source / drain regions SD.

[0129] Reference Figure 1 and Figure 7 The first mask pattern 165 can be removed, and the first conductive layer 170 can be deposited on the semiconductor substrate 100.

[0130] The formation of the first conductive layer 170 may include: depositing a barrier metal layer to conformally cover the embedded contact pattern BC and bit line spacers 131 and 133 in the first region CAR and the contact hole CH in the second region PCR, and depositing a metal layer on the barrier metal layer to fill the contact hole CH.

[0131] Reference Figure 1 and Figure 8 The first conductive layer 170 can be patterned to form a landing pad LP in the first region CAR and a first conductive pattern CP1 in the second region PCR. The landing pad LP can be formed on the buried contact pattern BC, and the first conductive pattern CP1 can be connected to the peripheral source / drain regions SD.

[0132] The formation of the landing pad LP and the first conductive pattern CP1 may include: forming a mask pattern on the first conductive layer 170, and using the mask pattern as an etching mask to etch a portion of the first conductive layer 170 to form a pad recess in the first region CAR and a separation recess in the second region PCR.

[0133] When the pad recesses are formed in the first region CAR, the pad recesses may have a bottom surface that is located at a level lower than the top surface of the bit line structure BLS, so that the landing pads LP can be spaced apart from each other. Furthermore, during the formation of the pad recesses, the bit line spacers 131 and 133 may be partially etched.

[0134] In the second region PCR, the separation recess can extend in the second direction D2 to form a first conductive pattern CP1 spaced apart from each other in the first direction D1. The separation recess can be formed as a portion exposing the peripheral gate structure GS.

[0135] Next, an insulating layer can be deposited to fill the pad recess and the separation recess, and a planarization process can be performed on the insulating layer to expose the top surface of the landing pad LP and the first conductive pattern CP1. Therefore, a pad insulating pattern 181 formed of insulating material can be formed in the pad recess, and a first insulating pattern 183 can be formed in the separation recess. The first insulating pattern 183 can directly contact the side surface of the pad portion of the first conductive pattern CP1.

[0136] Subsequently, a second etch stop layer 190 can be deposited on the semiconductor substrate 100 with a constant thickness. The second etch stop layer 190 may cover the top surface of the pad insulating pattern 181, the landing pad LP, the first conductive pattern CP1, and the first insulating pattern 183. The second etch stop layer 190 may be formed of or comprise an insulating material (e.g., silicon nitride).

[0137] Reference Figure 9 A second interlayer insulating layer 200 can be formed on the second etch stop layer 190. In an embodiment, the second interlayer insulating layer 200 can be formed of at least one of BPSG, TOSZ, USG, SOG, FOX, TEOS, HDP CVD oxide, and HSQ, or include at least one of BPSG, TOSZ, USG, SOG, FOX, TEOS, HDP CVD oxide, and HSQ.

[0138] The second interlayer insulating layer 200 can be patterned to form a first opening OP1 in the second region PCR and a second opening OP2 in the third region SL. The formation of the first opening OP1 and the second opening OP2 may include: forming a mask pattern on the second interlayer insulating layer 200, and anisotropically etching the second interlayer insulating layer 200 to expose the second etch stop layer 190. In the second region PCR, each of the first openings OP1 may have a width that decreases in the downward direction and may have a sloping side surface.

[0139] Next, refer to Figure 10 An insulating gap filling layer 210 can be formed to fill the first opening OP1. The insulating gap filling layer 210 can be formed of an insulating material different from, or include an insulating material different from, the second interlayer insulating layer 200. For example, the insulating gap filling layer 210 can be formed of, or include, silicon nitride or silicon oxynitride. The insulating gap filling layer 210 can be formed of a single insulating material.

[0140] The insulating gap filler layer 210 may be deposited with a thickness approximately half the width of the first opening OP1. In the third region SL, the insulating gap filler layer 210 may cover the inner surface of the second opening OP2 with a constant or uniform thickness.

[0141] Reference Figure 11 An etch-back or planarization process can be performed on the top surface of the second interlayer insulation layer 200. Therefore, a separation insulation pattern 215 can be formed in the first opening OP1, and a separation insulation spacer 217 can be formed on the side surface of the second opening OP2.

[0142] Reference Figure 12 After forming the separation insulating pattern 215 in the second region PCR, a second mask pattern 225 can be formed on the second interlayer insulating layer 200. The second mask pattern 225 can cover the first region CAR and the third region SL, and expose a portion of the second interlayer insulating layer 200 in the second region PCR.

[0143] The upper portion of the second interlayer insulating layer 200 can be anisotropically etched using the second mask pattern 225 as an etching mask. Therefore, pad trenches PT can be formed in the second region PCR. The etching depth of the pad trenches PT can be less than approximately half the thickness of the second interlayer insulating layer 200. As a result of the anisotropic etching process, the pad trenches PT can have sloping side surfaces. Furthermore, the side surfaces of the pad trenches PT can be spaced apart from the separation insulating pattern 215.

[0144] After the pad trench PT is formed, the second mask pattern 225 can be removed to expose the second interlayer insulating layer 200.

[0145] Reference Figure 13 A mask structure MS can be formed on the second interlayer insulating layer 200 with pad trenches PT.

[0146] The mask structure MS may include a first mask layer MS1 on the second interlayer insulating layer 200, a second mask layer MS2 on the first mask layer MS1, and a third mask pattern MS3 on the second mask layer MS2.

[0147] The first mask layer MS1 may include, for example, ACL. The second mask layer MS2 may include a material with etch selectivity relative to the first mask layer MS1. As an example, the second mask layer MS2 may be formed of silicon (Si) or oxide nitride (SiON), or may include silicon (Si) or oxide nitride (SiON). The third mask pattern MS3 may be a photoresist pattern. The formation of the third mask pattern MS3 may include: forming a photoresist layer on the second mask layer MS2, and performing an exposure process and a development process on the photoresist layer.

[0148] Subsequently, the second mask layer MS2 and the first mask layer MS1 can be sequentially etched using the third mask pattern MS3 as an etching mask, thereby exposing the bottom surface of the pad trench PT.

[0149] Next, refer to Figure 14 By using a mask structure MS as an etch mask to anisotropically etch the second interlayer insulating layer 200, a pad contact hole PH can be formed in the lower part of the second interlayer insulating layer 200. The pad contact hole PH can penetrate the second interlayer insulating layer 200 and the second etch stop layer 190 in the second region PCR, and can expose the top surface of the first conductive pattern CP1.

[0150] After forming the pad contact hole PH, the mask structure MS can be removed.

[0151] Reference Figure 15 A second conductive layer 230 can be deposited on the second interlayer insulating layer 200 to fill the pad contact holes PH and pad trenches PT. In the third region SL, the second conductive layer 230 can cover the second opening OP2 in which the separating insulating spacer 217 is formed with a constant thickness.

[0152] The formation of the second conductive layer 230 may include: depositing a barrier metal layer to conformally cover the pad contact holes PH and pad trenches PT in the second region PCR and the top surface of the second interlayer insulating layer 200. The formation of the second conductive layer 230 may further include: depositing a metal layer on the barrier metal layer to fill the pad contact holes PH and pad trenches PT. Here, the second conductive layer 230 may be formed of a doped semiconductor layer (e.g., a doped polysilicon layer), and the second conductive layer 230 may be formed of a metal layer (e.g., a tungsten layer, an aluminum layer, a titanium layer, or a tantalum layer).

[0153] Reference Figure 16 An etching process can be performed on the second conductive layer 230 to expose the top surface of the second interlayer insulating layer 200 and the top surface of the separation insulating pattern 215. Therefore, in the second region PCR, the second conductive pattern CP2 can be formed in the second interlayer insulating layer 200. The second conductive pattern CP2 can be connected to the first conductive pattern CP1.

[0154] In the third region SL, an insulating gap-filling layer can be formed to fill the second opening OP2 before the etch-back process of the second conductive layer 230. The insulating gap-filling layer in the third region SL can be planarized during the etch-back process of the second conductive layer 230, and an alignment key pattern AK can be formed in the second opening OP2 in the third region SL.

[0155] Next, a capping insulating layer 240 can be deposited on the top surface of the second interlayer insulating layer 200, the top surface of the second conductive pattern CP2, and the top surface of the separation insulating pattern 215. The capping insulating layer 240 can be deposited to have a substantially constant thickness. The capping insulating layer 240 can be formed of silicon nitride and / or silicon oxynitride, or include silicon nitride and / or silicon oxynitride.

[0156] After that, as Figure 2A and Figure 2B As shown, a capacitor CAP can be formed in the first region CAR, and a third conductive pattern CP3 connected to the second conductive pattern CP2 can be formed in the second region PCR.

[0157] According to an embodiment, the second conductive pattern can be coupled to the first conductive pattern connected to the peripheral circuit, and the number of photolithography and etching processes performed when forming the second conductive pattern can be reduced. Therefore, the process difficulty and manufacturing cost in manufacturing semiconductor devices can be reduced.

[0158] Although various aspects of the exemplary embodiments have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: The first interlayer insulating layer is located on the semiconductor substrate; A first conductive pattern that penetrates the first interlayer insulating layer; The second interlayer insulation layer is on top of the first interlayer insulation layer; The second conductive pattern is disposed in the second interlayer insulating layer and coupled to the first conductive pattern; as well as A separate insulating pattern is disposed between the second conductive patterns in the second interlayer insulating layer. A portion of the second interlayer insulating layer is located between the side surface of the separated insulating pattern and the side surface of the second conductive pattern.

2. The semiconductor device according to claim 1, wherein, Each of the second conductive patterns includes: The contact portion penetrates the lower part of the second interlayer insulating layer and contacts one of the first conductive patterns; and The pad portion is located on top of the second interlayer insulating layer and is connected to the contact portion. The top surface of the pad portion has a first width, and The bottom surface of the pad portion has a second width that is smaller than the first width.

3. The semiconductor device according to claim 1, wherein, The top surface of the second conductive pattern is coplanar with the top surface of the separated insulating pattern.

4. The semiconductor device according to claim 1, wherein, The separated insulating pattern has a single-layer structure and includes an insulating material different from the second interlayer insulating layer.

5. The semiconductor device according to claim 1, wherein, Each of the second conductive patterns includes a metal pattern and a barrier metal pattern, wherein the barrier metal pattern is disposed between the side surface of the metal pattern and the second interlayer insulating layer and has a constant thickness.

6. The semiconductor device according to claim 1, wherein, Each of the first conductive patterns includes: The contact portion penetrates the first interlayer insulating layer and contacts the source / drain region of the semiconductor device; and The pad portion is disposed on the first interlayer insulating layer and connected to the contact portion.

7. The semiconductor device of claim 6, further comprising a first insulating pattern between the pad portions of the first conductive pattern. in, The top surface of the first insulating pattern is coplanar with the top surface of the first conductive pattern.

8. The semiconductor device according to claim 7, wherein, Each of the first conductive patterns includes a barrier metal pattern and a metal pattern on the barrier metal pattern, and The side surface of the metal pattern is in contact with the side surface of the first insulating pattern.

9. The semiconductor device according to claim 1, further comprising: A device isolation layer that is located in the semiconductor substrate and defines an active region; A gate structure, which is located on the active region; as well as The source / drain regions are located on opposite sides of the gate structure. The first conductive pattern is coupled to the source / drain region.

10. A semiconductor device, comprising: The first interlayer insulating layer is located on the semiconductor substrate; A first conductive pattern that penetrates the first interlayer insulating layer; A second interlayer insulating layer is on the first interlayer insulating layer and covers a portion of the first conductive pattern; A second conductive pattern is located in the second interlayer insulating layer and coupled to the first conductive pattern; A separation insulating pattern is disposed between the second conductive patterns, wherein the separation insulating pattern penetrates the second interlayer insulating layer; as well as An insulating layer is sealed on the top surface of the separated insulating pattern and the top surface of the second conductive pattern. The second conductive pattern in the second conductive pattern includes: The contact portion penetrates the lower part of the second interlayer insulating layer and contacts the first conductive pattern in the first conductive pattern; and The pad portion, located above the second interlayer insulating layer, is wider than the contact portion. Wherein, the separation insulating pattern in the separation insulating pattern has a first side surface, and the pad portion of the second conductive pattern has a second side surface, and The distance between the first side surface and the second side surface decreases as the distance from the bottom surface of the second interlayer insulating layer increases in the upward direction.

11. The semiconductor device according to claim 10, wherein, The pad portion of the second conductive pattern has a width that increases from its bottom surface to its top surface.

12. The semiconductor device of claim 10, further comprising: A device isolation layer is provided in the semiconductor substrate and defines a cell active region and a peripheral active region. Bitline structure, which intersects with the active region of the unit; A gate structure that intersects with the peripheral active region; as well as The source / drain regions are located in the peripheral active region on opposite sides of the gate structure. The first conductive pattern is coupled to the source / drain region.

13. The semiconductor device of claim 12, further comprising: An embedded contact pattern is placed on the opposite side of the bit line structure and connected to the cell active region; as well as Landing pads, which are respectively connected to the buried contact pattern, are configured to cover a portion of the bit line structure. The top surface of the first conductive pattern is coplanar with the top surface of the landing pad.

14. A semiconductor device, comprising: A semiconductor substrate, comprising a first region and a second region; A device isolation layer is provided in the semiconductor substrate, which defines a cell active region in the first region and a peripheral active region in the second region. A word line structure that extends in the semiconductor substrate and across the cell active region along a first direction; The bitline structure intersects with the active region of the cell in the first region; An embedded contact pattern is placed on the opposite side of the bit line structure and connected to the cell active region; Landing pads, which are respectively connected to the buried contact pattern to cover a portion of the bit line structure; A gate structure is located on the peripheral active region; Source / drain regions are disposed on opposite sides of the gate structure in the peripheral active region; A first interlayer insulating layer covers the gate structure in the second region; A first conductive pattern is disposed on opposite sides of the gate structure to penetrate the first interlayer insulating layer and is connected to the source / drain region; A second interlayer insulating layer is located on top of the first interlayer insulating layer in the second region and covers a portion of the first conductive pattern; A second conductive pattern is located in the second interlayer insulating layer and coupled to the first conductive pattern; A separation insulating pattern is disposed between the second conductive patterns, wherein the separation insulating pattern penetrates the second interlayer insulating layer; as well as An insulating layer is sealed on the top surface of the separated insulating pattern and the top surface of the second conductive pattern.

15. The semiconductor device according to claim 14, wherein, The top surface of the second conductive pattern is coplanar with the top surface of the separated insulating pattern.

16. The semiconductor device of claim 14, wherein, The top surface of the second conductive pattern is further away from the semiconductor substrate than the top surface of the landing pad.

17. The semiconductor device according to claim 14, wherein, The top surface of the first conductive pattern is coplanar with the top surface of the landing pad.

18. The semiconductor device according to claim 14, wherein, Each of the first conductive patterns includes: The contact portion penetrates the first interlayer insulation layer and contacts the source / drain region; and The pad portion is located on the first interlayer insulating layer and is connected to the contact portion.

19. The semiconductor device of claim 18, further comprising a first insulating pattern between the pad portions of the first conductive pattern. in, The top surface of the first insulating pattern is coplanar with the top surface of the first conductive pattern.

20. The semiconductor device of claim 14, wherein, The second conductive pattern in the second conductive pattern includes: The contact portion penetrates the lower part of the second interlayer insulating layer and contacts the first conductive pattern in the first conductive pattern; and The pad portion, located above the second interlayer insulating layer, is wider than the contact portion. The separated insulating pattern in the separated insulating pattern has a first side surface. Wherein, the pad portion of the second conductive pattern has a second side surface, and The distance between the first side surface and the second side surface decreases as the distance from the bottom surface of the second interlayer insulating layer increases in the upward direction.

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