Semiconductor device, method of manufacturing semiconductor device, and memory system

Abstract

The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method of the semiconductor device and a storage system. The semiconductor device comprises a stacking structure and a separation structure penetrating through the stacking structure, and the stacking structure comprises a plurality of first dielectric layers and gate layers which are alternately stacked; the stack structure is divided into a connection region and a core region along a first direction, and a gate layer of the connection region comprises a first conductive layer; the separation structure is located between the connection area and the core area, the size of the separation structure in the second direction is larger than that of the first conductive layer in the second direction, and the first direction is perpendicular to the stacking direction of the stacking structure; the second direction is perpendicular to the first direction and the stacking direction of the stacking structure. The size of the separation structure along the second direction is larger than that of the first conductive layer along the second direction, so that the first conductive layer is limited in the connection region, the separation structure can play a role in protecting the first conductive layer, and the performance of the semiconductor device can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a method for manufacturing a semiconductor device, and a memory system. Background Technology

[0002] In the process architecture of fabricating multiple contact holes of different depths using SCT (stair contact) technology and then forming contacts within the contact holes, sacrificial material needs to be removed step by step. The process of removing sacrificial material step by step still needs to be optimized to improve the stability of semiconductor devices. Summary of the Invention

[0003] The purpose of this disclosure is to provide a semiconductor device, a method for manufacturing a semiconductor device, and a memory system to improve the performance of the semiconductor device.

[0004] To achieve the above objectives, this disclosure provides a semiconductor device including a stacked structure and a partition structure extending through the stacked structure. The stacked structure includes a plurality of alternately stacked first dielectric layers and gate layers. The stacked structure is divided into a connection region and a core region along a first direction. The gate layer of the connection region includes a first conductive layer. The partition structure is located between the connection region and the core region. The dimension of the partition structure along a second direction is larger than the dimension of the first conductive layer along the second direction. The first direction is perpendicular to the stacking direction of the stacked structure, and the second direction is perpendicular to both the first direction and the stacking direction of the stacked structure.

[0005] In one embodiment of this disclosure, the semiconductor device further includes a gate line isolation structure that extends through the stacked structure; the gate line isolation structure extends along a first direction within a first defined plane, and the separator extends along a second direction; the dimension of the separator along the second direction is greater than the dimension of the gate line isolation structure along the second direction; wherein the first defined plane is perpendicular to the stacking direction of the stacked structure.

[0006] In one embodiment of this disclosure, the end of the separator structure is located on the side of the first conductive layer away from the gate isolation structure.

[0007] In one embodiment of this disclosure, the grid isolation structure is located on both sides of the separation structure along the first direction.

[0008] In one embodiment of this disclosure, the semiconductor device further includes a plurality of contacts located in the connection region, the contacts being connected to the gate layer of the corresponding core region via the first conductive layer.

[0009] In one embodiment of this disclosure, a plurality of contacts arranged side by side along the first direction are connected to different gate layers near the gate line isolation structure.

[0010] In one embodiment of this disclosure, the first conductive layer is in contact with the separation structure along the first direction.

[0011] In one embodiment of this disclosure, the core region includes multiple channel structures, all of which penetrate the stacked structure.

[0012] In one embodiment of this disclosure, the semiconductor device further includes a plurality of dummy channel structures located in the connection region and penetrating the first conductive layer.

[0013] In one embodiment of this disclosure, the projection of the partition structure in a second defined plane covers the projection of the dummy channel structure in the second defined plane, wherein the second defined plane is perpendicular to the first direction.

[0014] Based on the above objectives, this disclosure also provides a method for manufacturing a semiconductor device, comprising: providing a stacked structure, the stacked structure including alternatingly stacked first dielectric layers and second dielectric layers, the stacked structure being divided into a connection region and a core region along a first direction; forming a plurality of first channel vias penetrating the stacked structure, the plurality of first channel vias being arranged along the first direction; forming a plurality of second channel vias penetrating the stacked structure, the plurality of second channel vias being located between the connection region and the core region, the plurality of second channel vias being arranged along a second direction; connecting the plurality of first channel vias to form a gate line gap; connecting the plurality of second channel vias to form an isolation trench; filling the isolation trench with a first sacrificial layer to form a separator structure; removing a portion of the second dielectric layer in the connection region via the gate line gap, the dimension of the removed second dielectric layer along the second direction being smaller than the dimension of the separator structure along the second direction; wherein, the first direction is perpendicular to the stacking direction of the stacked structure, and the second direction is perpendicular to both the first direction and the stacking direction of the stacked structure.

[0015] In one embodiment of this disclosure, forming a plurality of first channel holes penetrating the stacked structure includes: forming a plurality of first sub-channel holes in the connection region, forming a plurality of second sub-channel holes in the core region, the plurality of first sub-channel holes and the plurality of second sub-channel holes being arranged along the first direction, and all of the plurality of first sub-channel holes and the plurality of second sub-channel holes penetrating the stacked structure.

[0016] In one embodiment of this disclosure, connecting a plurality of first channel holes to form a grid line slot includes: connecting a plurality of first sub-channel holes to form a first grid line slot; and connecting a plurality of second sub-channel holes to form a second grid line slot; wherein, along the first direction, the first grid line slot and the second grid line slot are respectively located on both sides of the second channel hole.

[0017] In one embodiment of this disclosure, after forming the first gate line gap and the second gate line gap, the method further includes filling the first gate line gap and the second gate line gap with a second sacrificial layer.

[0018] In one embodiment of this disclosure, before removing a portion of the second dielectric layer in the connection region via the gate wire gap, the method further includes: removing a second sacrificial layer within the first gate wire gap to expose the second dielectric layer of the connection region.

[0019] In one embodiment of this disclosure, after removing a portion of the second dielectric layer in the connection region via the gate gap, the method further includes filling a third sacrificial layer into the first gap formed by removing the second sacrificial layer and the portion of the second dielectric layer in the connection region.

[0020] In one embodiment of this disclosure, after filling the first gap with a third sacrificial layer, the method further includes: removing the second sacrificial layer within the second gate gap to expose the second dielectric layer in the core region; and removing the second dielectric layer in the core region to form the second gap.

[0021] In one embodiment of this disclosure, after removing the second dielectric layer in the core region, the method further includes: removing the third sacrificial layer to form a third void, the third void comprising interconnected first gate line gaps and cavities between two adjacent first dielectric layers in the connection region.

[0022] In one embodiment of this disclosure, after removing the third sacrificial layer, the method further includes filling the cavity and the second gap with conductive material to form a first conductive layer in the connection region and a gate layer in the core region, respectively.

[0023] In one embodiment of this disclosure, after filling the cavity and the second gap with conductive material, the method further includes: forming a plurality of contact holes in the stacked structure of the connection region, the plurality of contact holes extending from the surface of the stacked structure and reaching a target second dielectric layer in a plurality of second dielectric layers; removing a portion of the target second dielectric layer to form a fourth gap and expose a corresponding target first conductive layer; forming a second conductive layer in the hole wall of the contact holes and in the fourth gap, the second conductive layer being connected to the gate layer of the corresponding core region through the target first conductive layer.

[0024] In one embodiment of this disclosure, connecting a plurality of second channel holes to form an isolation groove includes etching from the hole wall of the second channel hole toward a direction away from the center of the second channel hole to form an enlarged hole, wherein two adjacent enlarged holes are connected.

[0025] In one embodiment of this disclosure, connecting a plurality of second channel holes to form an isolation trench includes: removing a portion of the second dielectric layer to form a fourth void; and forming an oxide layer within the fourth void.

[0026] In one embodiment of this disclosure, the method for manufacturing the semiconductor device further includes: forming a third channel hole and a fourth channel hole through the stacked structure, wherein the third channel hole and the fourth channel hole are formed simultaneously with the first channel hole and the second channel hole; wherein the third channel hole is located in the core region and the fourth channel hole is located in the connection region.

[0027] In view of the above objectives, this disclosure also provides a storage system including a controller and the semiconductor device, wherein the controller is coupled to the semiconductor device and controls the semiconductor device.

[0028] The main beneficial effects of this disclosure are:

[0029] The semiconductor device provided in this disclosure has a separator structure located between the connection region and the core region. The size of the separator structure along the second direction is larger than the size of the first conductive layer along the second direction, which ensures that the first conductive layer is confined in the connection region. The separator structure can protect the first conductive layer, thereby improving the performance of the semiconductor device.

[0030] The semiconductor device manufacturing method disclosed herein forms an isolation structure between the connection region and the core region. When a portion of the second dielectric layer in the connection region is removed via the gate line gap, the size of the removed second dielectric layer along the second direction is smaller than the size of the isolation structure along the second direction. This effectively prevents the second dielectric layer in the connection region from extending into the core region during removal, reducing the risk of forming corner cavities near the core region and improving the performance of the semiconductor device. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the specific embodiments of this disclosure or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0032] Figure 1 A top view of a semiconductor structure provided in an embodiment of this disclosure;

[0033] Figure 2 The edge of the semiconductor device provided in the embodiments of this disclosure Figure 1 A cross-sectional view taken from line A-A';

[0034] Figure 3 Another cross-sectional view of the semiconductor device provided in the embodiments of this disclosure;

[0035] Figure 4 The edge of the semiconductor device provided in the embodiments of this disclosure Figure 3 A cross-sectional view taken from line B-B' in the middle;

[0036] Figure 5 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure;

[0037] Figures 6 to 19 This is a partial structural schematic diagram of a semiconductor structure formed after performing certain steps in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0038] Figure 20 This is a block diagram of an exemplary system with a memory according to an embodiment of this disclosure;

[0039] Figure 21A An exemplary block diagram of a storage system is shown;

[0040] Figure 21B A block diagram of another storage system is shown as an example. Detailed Implementation

[0041] The technical solutions of this disclosure will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0042] Generally, terms can be understood, at least in part, based on their use in context. For example, the term "one or more," depending at least in part on the context, can be used to describe any feature, structure, or characteristic in the singular or in the plural form to describe a combination of features, structures, or characteristics. Similarly, terms such as "a" or "described" in this document can also be understood, at least in part on the context, to convey either a singular or plural usage. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, again, depending at least in part on the context.

[0043] It should be readily understood that, in the description of this disclosure, it is necessary to clarify that the meanings of “on,” “above,” and “above” should be interpreted in the broadest sense, such that “on” not only means “directly on” something, but also includes the meaning of being “on” something with an intermediate feature or layer between them. Furthermore, “above” or “above” not only means “on” or “above” something, but can also include it being “on” or “above” something without an intermediate feature or layer between them (i.e., directly on something).

[0044] Furthermore, for ease of description, this document uses spatially relative terms such as "below," "below," "lower layer," "above," "upper layer," etc., to describe the relationship between one element or feature and another element or feature as shown in the figure. Spatially related terms are intended to include different orientations of the device in use or process steps (in addition to the orientation shown in the figure). The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted accordingly.

[0045] In the description of this disclosure, the term "substrate" refers to a material on which subsequent material layers are added. A substrate includes a front side and a back side. The front side of the substrate is typically where a semiconductor device is formed; unless otherwise stated, the semiconductor device is formed on the front side of the substrate, and the back side is opposite to the front side. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0046] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend integrally over the structure of a bottom or upper layer, or may have a range smaller than that of the bottom or upper layer. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers therein, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnects, and / or vertical interconnect pathways are formed) and one or more dielectric layers.

[0047] In this disclosure, the terms “horizontal / horizontally / laterally” mean nominally parallel to the lateral surface of the substrate, and the terms “vertical” or “perpendicularly” mean nominally perpendicular to the lateral surface of the substrate.

[0048] In a process architecture that uses SCT (stair contact) technology to fabricate multiple contact holes of varying depths and then form contacts within those holes, it's necessary to first remove a portion of the dielectric layer in the connection area, then fill it with sacrificial material, and finally remove the dielectric layer in the core area. If, during the removal of the dielectric layer in the connection area, the process extends towards the core area and forms a corner cavity, it may lead to poor filling of the sacrificial material. Simultaneously, removing the dielectric layer in the core area can also create defects at the corner cavities, ultimately degrading the performance of the semiconductor device.

[0049] To improve the performance of semiconductor devices, see Figures 1 to 4 As shown, this embodiment provides a semiconductor device including a stacked structure 10 and a partition structure 20 penetrating the stacked structure 10. The stacked structure 10 includes a plurality of alternately stacked first dielectric layers 11 and gate layers 12. The stacked structure 10 is divided into a connection region and a core region along a first direction. The gate layer 12 of the connection region includes a first conductive layer 121. The partition structure 20 is located between the connection region and the core region. The dimension D2 of the partition structure 20 along a second direction is greater than the dimension D1 of the first conductive layer 121 along the second direction. The first direction is perpendicular to the stacking direction of the stacked structure 10. The second direction is perpendicular to both the first direction and the stacking direction of the stacked structure 10.

[0050] In this embodiment, see Figure 1 and Figure 2 As shown, the X direction represents the first direction, the Y direction represents the second direction, and the Z direction represents the stacking direction of the stacked structure 10.

[0051] The semiconductor device provided in this embodiment has a separation structure located between the connection region and the core region. The size of the separation structure along the second direction is larger than the size of the first conductive layer along the second direction, which ensures that the first conductive layer is confined in the connection region. The separation structure can protect the first conductive layer, thereby improving the performance of the semiconductor device.

[0052] In some embodiments, the semiconductor device further includes a substrate 100, on which the stacked structure 10 may be formed. The substrate 100 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material.

[0053] In the initial stage, the stacked structure 10 may include a vertically interleaved first dielectric layer 11 and a second dielectric layer 12', the first dielectric layer 11 and the second dielectric layer 12' being made of different materials, and the first dielectric layer 11 and the second dielectric layer 12' may be stacked alternately in the Z direction. Exemplarily, the first dielectric layer 11 may include a silicon oxide layer, which is used as an isolation stacking layer, and the second dielectric layer 12' may include a silicon nitride layer, which is used as a sacrificial stacking layer. The sacrificial stacking layer is then etched and replaced with a conductive material. Exemplarily, the stacked structure 10 may undergo a full gate replacement process in the core region to replace all of the second dielectric layers with a conductive material layer, but in the connection region, the stacked structure 10 undergoes a partial gate replacement process to replace a portion of the second dielectric layers with a first conductive layer 121, retaining the remaining portion of the second dielectric layers. The conductive material layer in the core region and the first conductive layer 121 in the connection region together form the gate layer 12.

[0054] The conductive material layer and the first conductive layer can be made of the same material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polycrystalline silicon, doped silicon, silicide, or any combination thereof.

[0055] It should be understood that in actual products, the edge of the first conductive layer 121 extending along the X direction is generally wavy. Therefore, the size of the first conductive layer 121 along the second direction is not unique. In this embodiment, the size of the first conductive layer 121 along the second direction can be understood as the maximum size of the first conductive layer 121 along the second direction.

[0056] In some embodiments, the semiconductor device further includes a third dielectric layer located on the side of the stacked structure away from the substrate.

[0057] In one embodiment, the semiconductor device further includes a gate isolation structure that extends through the stacked structure 10; within a first defined plane, the gate isolation structure extends along a first direction, and the separator structure extends along a second direction; the dimension of the separator structure along the second direction is larger than the dimension of the gate isolation structure along the second direction; wherein, the first defined plane is perpendicular to the stacking direction of the stacked structure, that is, the first defined plane is... Figure 1 The XY plane in the middle.

[0058] It should be understood that in actual products, the edge of the gate isolation structure extending along the X direction is generally wavy. Therefore, the size of the gate isolation structure along the second direction is not unique. The size of the gate isolation structure along the second direction in this embodiment can be understood as the maximum size of the gate isolation structure along the second direction.

[0059] In one embodiment, see Figure 1As shown, the end of the separator structure is located on the side of the first conductive layer away from the gate isolation structure, so as to protect the first conductive layer and ensure that the first conductive layer is confined to the connection area.

[0060] In one embodiment, see Figure 1 As shown, along the first direction, the first conductive layer 121 contacts the separation structure 20, ensuring that the first conductive layer is confined to the connection area.

[0061] In one embodiment, see Figure 1 and Figure 2 As shown, along the first direction, the grid isolation structure is located on both sides of the separator structure 20.

[0062] Figure 2 yes Figure 1 See the sectional view along line A-A'. Figure 2 As shown, the gate isolation structure includes a first gate isolation structure 30a and a second gate isolation structure 30b. The first gate isolation structure 30a is located on one side of the partition structure 20, and the second gate isolation structure 30b is located on the other side of the partition structure 20. For example, the first gate isolation structure 30a is located in the core region, and the second gate isolation structure 30b is located in the connection region.

[0063] In some embodiments, the semiconductor device may include one or more blocks arranged in the Y direction and separated by gate slot structures. For example, the semiconductor device may be a NAND flash memory device, where each block is the smallest erasable cell of the NAND flash memory device. Each block may further include a plurality of fingers separated in the Y direction by some gate slot structures.

[0064] In one embodiment, see Figure 3 and Figure 4 As shown, the semiconductor device also includes a plurality of contacts 40, which are located in the connection region and are connected to the gate layer 12 of the corresponding core region through the first conductive layer 121.

[0065] For example, the outline shape of the contact portion 40 in the XY plane can be, but is not limited to, circular. The contact portion 40 includes a first conductive portion extending along the Z direction through a stacked structure to the location of the corresponding gate layer, an insulating sidewall located around the first conductive portion, and a second conductive portion connected to the first conductive portion and extending along the XY plane. The first conductive portion and the second conductive portion can be made of the same material and can be formed by deposition. The second conductive portion is connected to the gate layer 12 in the core region, which is in the same layer as the first conductive layer 121, through the first conductive layer 121.

[0066] In one embodiment, a plurality of contacts arranged side by side along a first direction are connected to different gate layers near the gate line isolation structure.

[0067] In some embodiments, each finger includes a plurality of contact portions 40 arranged side by side along a first direction, and each contact portion 40 is respectively connected to a different gate layer 12.

[0068] For example, Figure 3 The smaller and larger cross-sectional areas of the contact portion 40 can be respectively connected to the gate layer in the two fingers. Of course, the cross-sectional areas of the contacts in different fingers can also be the same.

[0069] In one embodiment, the core area includes a plurality of channel structures 50, all of which penetrate the stacked structure 10.

[0070] For example, each channel structure 50 may extend vertically through the stacked structure 10 and into the substrate 100. The channel structure 50 includes a channel hole filled with a semiconductor layer and a composite dielectric layer.

[0071] In some implementations, the semiconductor layer may serve as a channel layer, which includes silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. For example, the channel layer may include polycrystalline silicon.

[0072] In some implementations, the composite dielectric layer can serve as a memory layer, which includes a tunneling layer, a storage layer (also referred to as a "charge trap layer"), and a barrier layer. The remaining space of the channel via can be partially or completely filled with a filler, including a dielectric material such as silicon oxide and / or air gaps. The channel structure can have a cylindrical shape (e.g., a cylindrical shape).

[0073] In some embodiments, the filler, channel layer, tunneling layer, storage layer, and barrier layer of the memory layer are arranged radially from the center of the pillar outwards in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, or any combination thereof. In one example, the memory layer may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0074] In one embodiment, the semiconductor device further includes a plurality of dummy channel structures 60 located in the connection region and penetrating the first conductive layer 121 to provide mechanical support and / or load balancing.

[0075] In some embodiments, the dummy channel structure 60 has the same structure as the channel structure 50, and they are formed in the same manufacturing process. The dummy channel structure 60 does not perform the same memory functions as the channel structure 50.

[0076] It should be noted that the dummy channel structure 60 and the channel structure 50 can also have different structures and can be formed in different manufacturing processes. For example, the dummy channel structure 60 can be filled with a dielectric material without a semiconductor material (such as a channel layer).

[0077] It should be understood that during the gate replacement process, both the dummy channel structure 60 and the channel structure 50 can perform the function of mechanically supporting the stacked structure 10.

[0078] In one embodiment, see Figure 1 As shown, the projection of the partition structure in the second set plane (YZ plane) covers the projection of the dummy channel structure 60 in the second set plane, wherein the second set plane is perpendicular to the first direction.

[0079] See Figure 5 As shown, this embodiment also provides a method for manufacturing a semiconductor device, which may include the following steps:

[0080] Step S502, a stacked structure 10 is provided, the stacked structure 10 includes a first dielectric layer 11 and a second dielectric layer 12' that are alternately stacked, and the stacked structure 10 is divided into a connection area and a core area along a first direction;

[0081] Step S504: A plurality of first channel holes are formed through the stacked structure 10, and the plurality of first channel holes are arranged along a first direction;

[0082] Step S506: A plurality of second channel holes 2011 are formed through the stacked structure 10. The plurality of second channel holes 2011 are all located between the connection area and the core area, and the plurality of second channel holes 2011 are arranged along the second direction.

[0083] Step S508: Connect the multiple first channel holes to form grid line slots;

[0084] Step S510: Connect the multiple second channel holes 2011 to form an isolation groove 201;

[0085] Step S512: Fill the isolation trench 201 with a first sacrificial layer 202 to form a separation structure 20;

[0086] Step S514: Remove a portion of the second dielectric layer 12' in the connection area via the gate gap. The size of the removed second dielectric layer 12' along the second direction is smaller than the size of the separator structure 20 along the second direction. The first direction is perpendicular to the stacking direction of the stacked structure 10, and the second direction is perpendicular to both the first direction and the stacking direction of the stacked structure 10.

[0087] The semiconductor device manufacturing method provided in this embodiment forms an isolation structure between the connection region and the core region. When a portion of the second dielectric layer in the connection region is removed through the gate line gap, the size of the removed second dielectric layer along the second direction is smaller than the size of the isolation structure along the second direction. This effectively prevents the second dielectric layer in the connection region from extending into the core region, reducing the risk of forming corner cavities near the core region and improving the performance of the semiconductor device.

[0088] It should be understood that, Figure 5 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 5 The steps shown can be adjusted in order according to actual needs. Figures 6 to 19 This is a partial structural schematic diagram of a semiconductor structure formed after performing certain steps in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. The following is in conjunction with... Figure 5 , Figures 6 to 19 The method for manufacturing a semiconductor device provided in the embodiments of this disclosure will be described in detail.

[0089] In some exemplary processes prior to step S502, the process further includes providing a substrate 100. The provided substrate 100 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0090] It should be understood that substrate 100 can be retained, removed, or thinned.

[0091] In step S502, the stacked structure 10 is formed on the substrate 100.

[0092] The materials of the first dielectric layer 11 and the second dielectric layer 12' are different. For example, the method of forming the first dielectric layer 11 and the second dielectric layer 12' can be one or a combination of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0093] In step S504, a plurality of first channel holes are formed through the stacked structure 10, including: forming a plurality of first sub-channel holes 3011 in the connection region and forming a plurality of second sub-channel holes 3021 in the core region, see [link to relevant documentation]. Figure 6As shown, a plurality of first sub-channel holes 3011 and a plurality of second sub-channel holes 3021 are arranged along a first direction, and the plurality of first sub-channel holes 3011 and the plurality of second sub-channel holes 3021 all penetrate the stacked structure 10.

[0094] See also Figure 6 In step S506, a plurality of second channel holes 2011 are formed through the stacked structure 10. The plurality of second channel holes 2011 are all located between the connection area and the core area, and the plurality of second channel holes 2011 are arranged along the second direction.

[0095] In some embodiments, the second channel hole 2011 and the first channel hole can be formed in the same process.

[0096] In some exemplary processes, the method of manufacturing a semiconductor device further includes: forming a third channel via 501 and a fourth channel via 601 through the stacked structure 10, wherein the third channel via 501 and the fourth channel via 601 are formed simultaneously with the first channel via and the second channel via 2011; see also Figure 6 As shown, the third channel hole 501 is located in the core area, and the fourth channel hole 601 is located in the connecting area.

[0097] For example, see Figure 7 As shown, after the first channel hole, the second channel hole 2011, the third channel hole 501 and the fourth channel hole 601 are all fabricated by etching process, sacrificial material is filled into all the channel holes.

[0098] Among them, the third channel hole 501 and the fourth channel hole 601, which are filled with sacrificial material, form the channel structure 50 and the virtual channel structure 60, respectively.

[0099] In step S508, connecting multiple first channel holes to form grid line slots includes: connecting multiple first sub-channel holes 3011 to form a first grid line slot 301; and connecting multiple second sub-channel holes 3021 to form a second grid line slot 302; see [link to previous step]. Figure 8 As shown, along the first direction, the first grid line slot 301 and the second grid line slot 302 are located on both sides of the second channel hole 2011, respectively.

[0100] For example, an oxide material can be deposited first on the side of the stacked structure away from the substrate, then the oxide material at the corresponding position of the first channel hole can be removed, and then the sacrificial material in the first sub-channel hole 3011 can be removed. Etching can be performed from the hole wall of the first sub-channel hole 3011 in a direction away from the center of the first sub-channel hole 3011 to form an enlarged hole. Two adjacent enlarged holes can be connected to form a first gate line gap 301. Then the sacrificial material in the second sub-channel hole 3021 can be removed, and etching can be performed from the hole wall of the second sub-channel hole 3021 in a direction away from the center of the second sub-channel hole 3021 to form an enlarged hole. Two adjacent enlarged holes can be connected to form a second gate line gap 302.

[0101] See Figure 9 As shown, in some exemplary processes after forming the first gate line slot 301 and the second gate line slot 302, the process further includes filling the first gate line slot 301 and the second gate line slot 302 with a second sacrificial layer 303.

[0102] In step S510, multiple second channel holes 2011 are connected to form an isolation groove, including at least the following two implementation methods.

[0103] In some exemplary processes, etching can be performed from the wall of the second channel hole 2011 toward the center of the second channel hole 2011 to form an enlarged hole, and two adjacent enlarged holes are connected to form an isolation groove 201.

[0104] In some other exemplary processes, a portion of the second dielectric layer 12' may be removed to form a fourth void; an oxide layer 1220 may be formed within the fourth void.

[0105] It should be understood that, see Figure 11 As shown, the oxide layer 1220 and the first dielectric layer 11 can be made of the same material; for example, both can be made of silicon oxide. There is typically no clear interface between the oxide layer 1220 and the first dielectric layer 11.

[0106] In step S512, see Figure 10 As shown, a first sacrificial layer 202 is filled into the isolation groove to form a separation structure 20.

[0107] See also Figure 10 In some exemplary processes prior to removing a portion of the second dielectric layer 12' in the connection region via the gate gap, the process further includes removing the second sacrificial layer 303 within the first gate gap 301 to expose the second dielectric layer 12' in the connection region.

[0108] For example, the second sacrificial layer 303 within the first gate line gap 301 can be removed using, for example, a dry or wet etching process. In the etching process, structures such as mask layers formed on the stacked structure are well known and easily implemented by those skilled in the art, and therefore will not be described in detail in this embodiment.

[0109] See Figure 11 As shown, Figure 11 for Figure 10 A cross-sectional view along line C-C', in step S514, a portion of the second dielectric layer 12' in the connection area is removed via the first gate gap 301, wherein the dimension D1 of the removed second dielectric layer 12' along the second direction is smaller than the dimension D2 of the separator structure 20 along the second direction; wherein... Figure 10 In the diagram, the X direction represents the first direction, the Z direction represents the stacking direction of the stacked structure 10, and the Y direction represents the second direction.

[0110] After removing the second sacrificial layer 303 within the first gate gap 301 and removing a portion of the second dielectric layer 12' in the connection area via the first gate gap 301, a first void 1a is formed at the corresponding location.

[0111] See Figure 12 As shown, some exemplary processes after removing a portion of the second dielectric layer 12' in the connection region via the gate gap also include filling the first void 1a with a third sacrificial layer 1210.

[0112] See Figure 13 and Figure 14 As shown, some exemplary processes after filling the first void 1a with the third sacrificial layer 1210 further include: removing the second sacrificial layer 303 within the second gate gap 302 to expose the second dielectric layer 12' in the core region; and removing the second dielectric layer 12' in the core region to form the second void 1b.

[0113] For example, see Figure 13 As shown, the second sacrificial layer 303 within the second gate gap 302 can be removed using, for example, dry or wet etching processes to expose the second dielectric layer 12' in the core region. See also Figure 14 As shown, the second dielectric layer 12' in the core region is removed via the second gate line gap 302 to form the second void 1b.

[0114] See Figure 15 As shown, some exemplary processes after removing the second dielectric layer 12' in the core region also include: removing the third sacrificial layer 1210 to form a third void, the third void including interconnected first gate line slots 301 and cavities 1c between two adjacent first dielectric layers 11 in the connection region.

[0115] For example, the third sacrificial layer 1210 can be removed using, for example, a dry or wet etching process.

[0116] See Figure 16 As shown, in some exemplary processes after removing the third sacrificial layer 1210, the process further includes filling the cavity 1c and the second gap 1b with conductive material to form the first conductive layer 121 in the connection region and the gate layer 12 in the core region, respectively.

[0117] For example, a high-dielectric-constant material such as alumina (not shown) may be deposited before filling with conductive material. Subsequently, a binder layer such as titanium nitride (not shown) is deposited. One or more combinations of CVD, PVD, and ALD may be used in the deposition process. The conductive material for the first conductive layer 121 and the gate layer 12 within the core region may be tungsten; alternatively, other conductive materials such as molybdenum, ruthenium, cobalt, copper, aluminum, titanium, tantalum, tantalum nitride, doped silicon, or any combination thereof may be used to form the first conductive layer 121 and the gate layer 12 within the core region.

[0118] The high dielectric constant material can be formed prior to the formation of the first conductive layer 121, such that the first conductive layer 121 can be surrounded by the high dielectric constant material. The high dielectric constant material may include, for example, alumina, hafnium oxide, zirconium oxide, or any combination thereof.

[0119] See also Figure 16 In some exemplary processes following the filling of conductive material into cavity 1c and gap 1b, the process further includes filling the gate line gap with semiconductor material, such as polysilicon, to form a first gate line isolation structure 30a and a second gate line isolation structure 30b.

[0120] In some exemplary processes following the filling of the cavity 1c and the second gap 1b with conductive material, the process further includes: forming a plurality of contact holes 401 in the stacked structure 10 of the connection region, the plurality of contact holes 401 extending from the surface of the stacked structure 10 and reaching a target second dielectric layer 12' in a plurality of second dielectric layers 12'; removing a portion of the target second dielectric layer 12' to form a fourth gap and expose a corresponding target first conductive layer 121; forming a second conductive layer in the hole wall of the contact hole 401 and in the fourth gap, the second conductive layer being connected to the gate layer 12 of the corresponding core region through the target first conductive layer 121.

[0121] For example, Figure 17 The diagram shows a top view of a semiconductor structure in which multiple contact holes 401 are formed in the stacked structure 10 of the connection region. Figure 18 What is shown is Figure 17 A sectional view along line E-E'.

[0122] In some embodiments, contact holes 401 may be formed in the stacked structure using, for example, dry or wet etching processes. Contact holes 401 extend from the surface of the stacked structure 10 along the Z-direction and reach a target second dielectric layer 12' among a plurality of second dielectric layers 12'. In some embodiments, the cross-sectional shape of contact holes 401 in the XY plane may be circular. In other embodiments, the cross-sectional shape of contact holes 401 in the XY plane may also be other shapes, such as rectangular. First dielectric layers 11 and second dielectric layers 12' are exposed on the sidewalls of contact holes 401. As previously mentioned, the second dielectric layer 12' may be a silicon nitride layer. An insulating layer 402 is formed by depositing a dielectric material (e.g., silicon oxide or aluminum oxide) on the sidewalls and bottom of the contact holes using CVD or ALD. The bottom insulating layer is then removed, leaving the target second dielectric layer 12', and the insulating layer on the retained sidewalls serves as an insulating sidewall. Then, the exposed second dielectric layer 12' is etched to form a gap, retaining the high-dielectric-constant layer material outside the first conductive layer 121 corresponding to the connection area. This portion of the high-dielectric-constant layer material is then removed to expose the first conductive layer 121. See also Figure 19 As shown, a filling layer such as a conductive material layer is deposited into the contact hole and the gap to form a contact portion 40, wherein the conductive material layer is connected to the first conductive layer 121.

[0123] The method for creating contact holes 401, insulating layer 402, and filling layer is repeated, and the resulting multiple contact holes reach the corresponding second dielectric layer 12'. The insulating layer in each contact hole can be made of the same material, and the filling layer in each contact hole can be made of the same material.

[0124] See also Figure 19 As shown, in some embodiments where the substrate 100 is removed, a new semiconductor layer is formed, which can serve as a common source layer 110. The material of the common source layer can be single-crystal silicon, single-crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, and other suitable semiconductor materials. Furthermore, it can be formed by a thin-film deposition process, which can be one or a combination of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and electroplating.

[0125] In addition, after removing the substrate 100, the channel structure can be exposed, so the formed common source layer 110 can contact the exposed channel structure to achieve coupling between the common source layer 110 and the channel layer in the channel structure 50.

[0126] In some embodiments, a lead-out structure (not shown) coupled to the channel layer of the channel structure is also included, which may serve as the drain lead-out structure of the channel structure 50.

[0127] It should be noted that the semiconductor device provided in this embodiment can be manufactured using the semiconductor device manufacturing method provided in this embodiment.

[0128] This embodiment also provides a storage system, characterized in that it includes a controller and a semiconductor device provided in this embodiment, wherein the controller is coupled to the semiconductor device and controls the semiconductor device.

[0129] Figure 20 The diagram shown is a block diagram of an exemplary system with a storage system according to this embodiment. System 700 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality device, augmented reality device, or any other suitable electronic device having memory therein.

[0130] See Figure 20 As shown, system 700 may include a host 708 and a storage system 702, the storage system 702 having a controller 706 and one or more memories 704. The memories 704 may be semiconductor devices provided in this embodiment; the host 708 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor) of an electronic device. The host 708 may be configured to send data to the memories 704, or receive data from the memories 704.

[0131] The memory 704 in this embodiment can be any memory, such as non-volatile memory. Non-volatile memory can be NAND flash memory (e.g., 3D NAND flash memory).

[0132] In some embodiments, controller 706 is coupled to memory 704 and host 708 and is configured to control memory 704. Controller 706 can manage data stored in memory 704 and communicate with host 708.

[0133] In some embodiments, the controller 706 is configured to send a command to the memory 704 to cause the memory 704 to perform a memory operation method.

[0134] In some embodiments, the memory controller 706 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0135] In some embodiments, the memory controller 706 is designed to operate in high duty cycle environments, such as solid-state drives (SSDs) or embedded multimedia cards (eMMCs), which can be used as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. The controller 706 can be configured to send commands to the memory 704 to cause the memory 704 to perform operations, such as read, erase, and program operations.

[0136] The controller 706 can also be configured to manage various functions related to data stored or to be stored in the memory 704, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0137] In some embodiments, controller 706 is also configured to process error correction codes (ECC) regarding data read from or written to memory 704. Controller 706 may also perform any other suitable functions, such as formatting memory 704. Controller 706 may communicate with external devices (e.g., host 708) according to a specific communication protocol. For example, controller 706 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0138] The controller 706 and one or more memories 704 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the storage system 702 can be implemented and packaged into different types of end electronic products.

[0139] Figure 21A A block diagram of a memory system is shown as an example. See also Figure 21A As shown, controller 706 and a single memory 704 can be integrated into memory card 212. Memory card 212 may include PC cards (also known as PCMCIA cards, Personal Computer Memory Card International Association cards), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (such as MMC cards, RS-MMC cards, MMCmicro cards, etc.), SD cards (such as SD cards, miniSD cards, microSD cards, SDHC cards, etc.), UFS cards, etc. Memory card 212 may also include a connector for connecting memory card 212 to a host computer (e.g., ...). Figure 16The memory card connector 214 is coupled to the host 708.

[0140] Figure 21B A block diagram of another memory system is shown as an example. See also Figure 21B As shown, the controller 706 and multiple memories 704 can be integrated into the SSD 216. The SSD 216 may also include components for connecting the SSD 216 to a host computer (e.g., ...). Figure 20 The SSD connector 218 is coupled to the host 708 in the host. In some embodiments, the storage capacity and / or operating speed of the SSD 216 is greater than the storage capacity and / or operating speed of the memory card 212.

[0141] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A stacked structure comprising a plurality of alternatingly stacked first dielectric layers and gate layers; The stacked structure is divided into a connection region and a core region along a first direction, and the gate layer of the connection region includes a first conductive layer. as well as A partition structure extends through the stacked structure, the partition structure being located between the connection region and the core region, the dimension of the partition structure along the second direction being larger than the dimension of the first conductive layer along the second direction, wherein the first direction is perpendicular to the stacking direction of the stacked structure; the second direction is perpendicular to both the first direction and the stacking direction of the stacked structure.

2. The semiconductor device according to claim 1, characterized in that, It also includes a gate line isolation structure that extends through the stacked structure; Within a first defined plane, the gate isolation structure extends along the first direction, and the partition structure extends along the second direction; the dimension of the partition structure along the second direction is greater than the dimension of the gate isolation structure along the second direction; wherein, the first defined plane is perpendicular to the stacking direction of the stacked structure.

3. The semiconductor device according to claim 2, characterized in that, The end of the separation structure along the second direction is located on the side of the first conductive layer away from the gate isolation structure.

4. The semiconductor device according to claim 2, characterized in that, Along the first direction, the grid isolation structure is located on both sides of the separation structure.

5. The semiconductor device according to claim 2, characterized in that, It also includes multiple contact portions located in the connection region, and the contact portions are connected to the gate layer of the corresponding core region through the first conductive layer.

6. The semiconductor device according to claim 5, characterized in that, At a location near the gate line isolation structure, a plurality of contacts arranged side by side along the first direction are connected to different gate layers.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, Along the first direction, the first conductive layer is in contact with the separation structure.

8. The semiconductor device according to any one of claims 1 to 6, characterized in that, The core area includes multiple channel structures, all of which penetrate the stacked structure.

9. The semiconductor device according to any one of claims 1 to 6, characterized in that, It also includes multiple dummy channel structures, which are located in the connection area and penetrate the first conductive layer.

10. The semiconductor device according to claim 9, characterized in that, The projection of the dividing structure in the second set plane covers the projection of the dummy channel structure in the second set plane, wherein the second set plane is perpendicular to the first direction.

11. A method for manufacturing a semiconductor device, characterized in that, include: A stacked structure is provided, the stacked structure comprising alternating stacked first dielectric layers and second dielectric layers, the stacked structure being divided into a connection region and a core region along a first direction; A plurality of first channel holes are formed through the stacked structure, and the plurality of first channel holes are arranged along the first direction; A plurality of second channel holes are formed through the stacked structure, and the plurality of second channel holes are all located between the connection area and the core area, and the plurality of second channel holes are arranged along a second direction; Connect multiple first channel holes to form grid line slots; Connect multiple second channel holes to form an isolation groove; A first sacrificial layer is filled into the isolation groove to form a separation structure; A portion of the second dielectric layer in the connection region is removed via the gate gap, wherein the dimension of the removed second dielectric layer along the second direction is smaller than the dimension of the separator structure along the second direction; wherein the first direction is perpendicular to the stacking direction of the stacked structure, and the second direction is perpendicular to both the first direction and the stacking direction of the stacked structure.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that, Forming a plurality of first channel holes through the stacked structure, including: Multiple first sub-channel holes are formed in the connection area, and multiple second sub-channel holes are formed in the core area. The multiple first sub-channel holes and multiple second sub-channel holes are arranged along the first direction, and all of the multiple first sub-channel holes and multiple second sub-channel holes penetrate the stacked structure.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that, Connecting multiple first channel holes to form grid line slots includes: Connect multiple first sub-channel holes to form a first grid line slot; Connect multiple second sub-channel holes to form a second grid line slot; Along the first direction, the first grid line gap and the second grid line gap are located on both sides of the second channel hole.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that, After forming the first grid line gap and the second grid line gap, the process also includes: A second sacrificial layer is filled into the first gate line gap and the second gate line gap.

15. The method for manufacturing a semiconductor device according to claim 14, characterized in that, Before removing a portion of the second dielectric layer in the connection region via the gate wire gap, the method further includes: Remove the second sacrificial layer within the first gate gap to expose the second dielectric layer of the connection region.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that, After removing a portion of the second dielectric layer in the connection region via the gate wire gap, the process further includes: A third sacrificial layer is filled into the first void formed by removing the second sacrificial layer and a portion of the second dielectric layer in the connection region.

17. The method for manufacturing a semiconductor device according to claim 16, characterized in that, After filling the first void with a third sacrificial layer, the process further includes: Remove the second sacrificial layer within the second gate gap to expose the second dielectric layer in the core region; The second dielectric layer in the core region is removed to form a second void.

18. The method for manufacturing a semiconductor device according to claim 17, characterized in that, After removing the second dielectric layer in the core region, the process further includes: The third sacrificial layer is removed to form a third void, which includes interconnected first gate line gaps and cavities between two adjacent first dielectric layers in the connection region.

19. The method for manufacturing a semiconductor device according to claim 18, characterized in that, After removing the third sacrificial layer, the process also includes: Conductive material is filled into the cavity and the second gap to form a first conductive layer in the connection region and a gate layer in the core region, respectively.

20. The method for manufacturing a semiconductor device according to claim 19, characterized in that, After filling the cavity and the second gap with conductive material, the process further includes: Multiple contact holes are formed in the stacked structure of the connection area, and the multiple contact holes extend from the surface of the stacked structure and reach the target second dielectric layer in the multiple second dielectric layers; A portion of the target second dielectric layer is removed to form a fourth void and expose the corresponding target first conductive layer; A second conductive layer is formed in the hole wall of the contact hole and in the fourth gap. The second conductive layer is connected to the gate layer of the corresponding core region through the target first conductive layer.

21. A method for manufacturing a semiconductor device according to any one of claims 11 to 20, characterized in that, Connecting multiple second channel holes to form an isolation groove includes: Etching is performed from the wall of the second channel hole toward the center of the second channel hole to form an enlarged hole, with two adjacent enlarged holes connected.

22. The method for manufacturing a semiconductor device according to any one of claims 11 to 20, characterized in that, Connecting multiple second channel holes to form an isolation groove includes: Part of the second dielectric layer is removed to form a fourth void; An oxide layer is formed within the fourth void.

23. The method for manufacturing a semiconductor device according to any one of claims 11 to 20, characterized in that, Also includes: A third and a fourth channel hole are formed through the stacked structure, and the third and fourth channel holes are formed simultaneously with the first and second channel holes; wherein the third channel hole is located in the core region and the fourth channel hole is located in the connection region.

24. A storage system, characterized in that, It includes a controller and a semiconductor device according to any one of claims 1 to 10, wherein the controller is coupled to the semiconductor device and controls the semiconductor device.

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